[clk:clk-remove-io.h 8/9] drivers/clk/renesas/r7s9210-cpg-mssr.c:122:10: error: implicit declaration of function 'clk_readl'; did you mean 'csr_read'?

[clk:clk-remove-io.h 8/9] drivers/clk/renesas/r7s9210-cpg-mssr.c:122:10: error: implicit declaration of function 'clk_readl'; did you mean 'csr_read'?

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 4694 bytes --]

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-remove-io.h
head:   91c16d737801d56e258b72c9d71f79c42c613919
commit: f1df560411dd2c32ce1bd1b9d3a90a8d8ae9be9c [8/9] clk: core: replace clk_{readl,writel} with {readl,writel}
config: riscv-allyesconfig (attached as .config)
compiler: riscv64-linux-gcc (GCC) 8.1.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        git checkout f1df560411dd2c32ce1bd1b9d3a90a8d8ae9be9c
        # save the attached .config to linux build tree
        GCC_VERSION=8.1.0 make.cross ARCH=riscv 

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>


All errors (new ones prefixed by >>):

   drivers/clk/renesas/r7s9210-cpg-mssr.c: In function 'r7s9210_update_clk_table':
>> drivers/clk/renesas/r7s9210-cpg-mssr.c:122:10: error: implicit declaration of function 'clk_readl'; did you mean 'csr_read'? [-Werror=implicit-function-declaration]
     frqcr = clk_readl(base + CPG_FRQCR) & 0xFFF;
             ^~~~~~~~~
             csr_read
   cc1: some warnings being treated as errors

vim +122 drivers/clk/renesas/r7s9210-cpg-mssr.c

fde35c9c Chris Brandt 2018-09-07  109  
4cb1480f Chris Brandt 2018-09-24  110  /* The clock dividers in the table vary based on DT and register settings */
4cb1480f Chris Brandt 2018-09-24  111  static void __init r7s9210_update_clk_table(struct clk *extal_clk,
4cb1480f Chris Brandt 2018-09-24  112  					    void __iomem *base)
fde35c9c Chris Brandt 2018-09-07  113  {
4cb1480f Chris Brandt 2018-09-24  114  	int i;
fde35c9c Chris Brandt 2018-09-07  115  	u16 frqcr;
fde35c9c Chris Brandt 2018-09-07  116  	u8 index;
fde35c9c Chris Brandt 2018-09-07  117  
fde35c9c Chris Brandt 2018-09-07  118  	/* If EXTAL is above 12MHz, then we know it is Mode 1 */
4cb1480f Chris Brandt 2018-09-24  119  	if (clk_get_rate(extal_clk) > 12000000)
fde35c9c Chris Brandt 2018-09-07  120  		cpg_mode = 1;
fde35c9c Chris Brandt 2018-09-07  121  
fde35c9c Chris Brandt 2018-09-07 @122  	frqcr = clk_readl(base + CPG_FRQCR) & 0xFFF;
fde35c9c Chris Brandt 2018-09-07  123  	if (frqcr == 0x012)
fde35c9c Chris Brandt 2018-09-07  124  		index = 0;
fde35c9c Chris Brandt 2018-09-07  125  	else if (frqcr == 0x112)
fde35c9c Chris Brandt 2018-09-07  126  		index = 1;
fde35c9c Chris Brandt 2018-09-07  127  	else if (frqcr == 0x212)
fde35c9c Chris Brandt 2018-09-07  128  		index = 2;
fde35c9c Chris Brandt 2018-09-07  129  	else if (frqcr == 0x322)
fde35c9c Chris Brandt 2018-09-07  130  		index = 3;
fde35c9c Chris Brandt 2018-09-07  131  	else if (frqcr == 0x333)
fde35c9c Chris Brandt 2018-09-07  132  		index = 4;
fde35c9c Chris Brandt 2018-09-07  133  	else
fde35c9c Chris Brandt 2018-09-07  134  		BUG_ON(1);	/* Illegal FRQCR value */
fde35c9c Chris Brandt 2018-09-07  135  
fde35c9c Chris Brandt 2018-09-07  136  	for (i = 0; i < ARRAY_SIZE(r7s9210_core_clks); i++) {
fde35c9c Chris Brandt 2018-09-07  137  		switch (r7s9210_core_clks[i].id) {
fde35c9c Chris Brandt 2018-09-07  138  		case R7S9210_CLK_I:
fde35c9c Chris Brandt 2018-09-07  139  			r7s9210_core_clks[i].div = ratio_tab[index].i;
fde35c9c Chris Brandt 2018-09-07  140  			break;
fde35c9c Chris Brandt 2018-09-07  141  		case R7S9210_CLK_G:
fde35c9c Chris Brandt 2018-09-07  142  			r7s9210_core_clks[i].div = ratio_tab[index].g;
fde35c9c Chris Brandt 2018-09-07  143  			break;
fde35c9c Chris Brandt 2018-09-07  144  		case R7S9210_CLK_B:
fde35c9c Chris Brandt 2018-09-07  145  			r7s9210_core_clks[i].div = ratio_tab[index].b;
fde35c9c Chris Brandt 2018-09-07  146  			break;
fde35c9c Chris Brandt 2018-09-07  147  		case R7S9210_CLK_P1:
fde35c9c Chris Brandt 2018-09-07  148  		case R7S9210_CLK_P1C:
fde35c9c Chris Brandt 2018-09-07  149  			r7s9210_core_clks[i].div = ratio_tab[index].p1;
fde35c9c Chris Brandt 2018-09-07  150  			break;
fde35c9c Chris Brandt 2018-09-07  151  		case R7S9210_CLK_P0:
fde35c9c Chris Brandt 2018-09-07  152  			r7s9210_core_clks[i].div = 32;
fde35c9c Chris Brandt 2018-09-07  153  			break;
fde35c9c Chris Brandt 2018-09-07  154  		}
fde35c9c Chris Brandt 2018-09-07  155  	}
fde35c9c Chris Brandt 2018-09-07  156  }
fde35c9c Chris Brandt 2018-09-07  157  

:::::: The code at line 122 was first introduced by commit
:::::: fde35c9c7db5732cc1fbd89fa5eba5a9e0b25f6e clk: renesas: cpg-mssr: Add R7S9210 support

:::::: TO: Chris Brandt <chris.brandt@renesas.com>
:::::: CC: Geert Uytterhoeven <geert+renesas@glider.be>

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 56171 bytes --]