* [PATCH V2] clk: tegra210: Fix default rates for HDA clocks
@ 2019-06-05 14:01 Jon Hunter
[not found] ` <20190607002314.4AEF321019@mail.kernel.org>
2019-06-14 17:43 ` Stephen Boyd
0 siblings, 2 replies; 3+ messages in thread
From: Jon Hunter @ 2019-06-05 14:01 UTC (permalink / raw)
To: Peter De Schrijver, Michael Turquette, Stephen Boyd, Thierry Reding
Cc: linux-clk, linux-tegra, linux-kernel, Sameer Pujar, Jon Hunter, stable
Currently the default clock rates for the HDA and HDA2CODEC_2X clocks
are both 19.2MHz. However, the default rates for these clocks should
actually be 51MHz and 48MHz, respectively. The current clock settings
results in a distorted output during audio playback. Correct the default
clock rates for these clocks by specifying them in the clock init table
for Tegra210.
Cc: stable@vger.kernel.org
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
---
Changes since V1:
- Updated the changelog and cc'ed stable.
Please note that I have not added a fixes tag because this has always
been broken for Tegra210.
drivers/clk/tegra/clk-tegra210.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index e1ba62d2b1a0..ac1d27a8c650 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -3366,6 +3366,8 @@ static struct tegra_clk_init_table init_table[] __initdata = {
{ TEGRA210_CLK_I2S3_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
{ TEGRA210_CLK_I2S4_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
{ TEGRA210_CLK_VIMCLK_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
+ { TEGRA210_CLK_HDA, TEGRA210_CLK_PLL_P, 51000000, 0 },
+ { TEGRA210_CLK_HDA2CODEC_2X, TEGRA210_CLK_PLL_P, 48000000, 0 },
/* This MUST be the last entry. */
{ TEGRA210_CLK_CLK_MAX, TEGRA210_CLK_CLK_MAX, 0, 0 },
};
--
2.7.4
^ permalink raw reply related [flat|nested] 3+ messages in thread
[parent not found: <20190607002314.4AEF321019@mail.kernel.org>]
* Re: [PATCH V2] clk: tegra210: Fix default rates for HDA clocks
[not found] ` <20190607002314.4AEF321019@mail.kernel.org>
@ 2019-06-13 15:53 ` Jon Hunter
0 siblings, 0 replies; 3+ messages in thread
From: Jon Hunter @ 2019-06-13 15:53 UTC (permalink / raw)
To: Sasha Levin, Peter De Schrijver; +Cc: linux-clk, linux-tegra, stable
On 07/06/2019 01:23, Sasha Levin wrote:
> Hi,
>
> [This is an automated email]
>
> This commit has been processed because it contains a -stable tag.
> The stable tag indicates that it's relevant for the following trees: all
>
> The bot has tested the following trees: v5.1.7, v5.0.21, v4.19.48, v4.14.123, v4.9.180, v4.4.180.
>
> v5.1.7: Build OK!
> v5.0.21: Build OK!
> v4.19.48: Failed to apply! Possible dependencies:
> 845d782d9144 ("clk: tegra: Fix maximum audio sync clock for Tegra124/210")
>
> v4.14.123: Failed to apply! Possible dependencies:
> 26f8590c4a1f ("clk: tegra: Make vic03 a child of pll_c3")
> 845d782d9144 ("clk: tegra: Fix maximum audio sync clock for Tegra124/210")
> c485ad63abb4 ("clk: tegra: Specify VDE clock rate")
>
> v4.9.180: Failed to apply! Possible dependencies:
> 24c3ebef1ab6 ("clk: tegra: Add aclk")
> 26f8590c4a1f ("clk: tegra: Make vic03 a child of pll_c3")
> 319af7975c9f ("clk: tegra: Define Tegra210 DMIC sync clocks")
> 34ac2c278b30 ("clk: tegra: Fix ISP clock modelling")
> 3843832fc8ca ("clk: tegra: Handle UTMIPLL IDDQ")
> 845d782d9144 ("clk: tegra: Fix maximum audio sync clock for Tegra124/210")
> 8dce89a1c2cf ("clk: tegra: Don't warn for PLL defaults unnecessarily")
> 9326947f2215 ("clk: tegra: Fix pll_a1 iddq register, add pll_a1")
> bfa34832df1f ("clk: tegra: Add CEC clock")
> c485ad63abb4 ("clk: tegra: Specify VDE clock rate")
> e745f992cf4b ("clk: tegra: Rework pll_u")
>
> v4.4.180: Failed to apply! Possible dependencies:
> 26f8590c4a1f ("clk: tegra: Make vic03 a child of pll_c3")
> 385f9adf625f ("clk: tegra: Constify pdiv-to-hw mappings")
> 407254da291c ("clk: tegra: pll: Add logic for out-of-table rates for T210")
> 6583a6309e83 ("clk: tegra: pll: Add tegra_pll_wait_for_lock to clk header")
> 845d782d9144 ("clk: tegra: Fix maximum audio sync clock for Tegra124/210")
> 86c679a52294 ("clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate")
> 8d99704fde54 ("clk: tegra: Format tables consistently")
> c485ad63abb4 ("clk: tegra: Specify VDE clock rate")
> c4947e364b50 ("clk: tegra: Fix 26 MHz oscillator frequency")
> d907f4b4a178 ("clk: tegra: pll: Add logic for handling SDM data")
> dd322f047d22 ("clk: tegra: pll: Add specialized logic for Tegra210")
> e52d7c04bb39 ("clk: tegra: Miscellaneous coding style cleanups")
> e745f992cf4b ("clk: tegra: Rework pll_u")
>
>
> How should we proceed with this patch?
I think that applying to 5.0 and 5.1 is fine for now.
Thanks
Jon
--
nvpublic
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH V2] clk: tegra210: Fix default rates for HDA clocks
2019-06-05 14:01 [PATCH V2] clk: tegra210: Fix default rates for HDA clocks Jon Hunter
[not found] ` <20190607002314.4AEF321019@mail.kernel.org>
@ 2019-06-14 17:43 ` Stephen Boyd
1 sibling, 0 replies; 3+ messages in thread
From: Stephen Boyd @ 2019-06-14 17:43 UTC (permalink / raw)
To: Jon Hunter, Michael Turquette, Peter De Schrijver, Thierry Reding
Cc: linux-clk, linux-tegra, linux-kernel, Sameer Pujar, Jon Hunter, stable
Quoting Jon Hunter (2019-06-05 07:01:39)
> Currently the default clock rates for the HDA and HDA2CODEC_2X clocks
> are both 19.2MHz. However, the default rates for these clocks should
> actually be 51MHz and 48MHz, respectively. The current clock settings
> results in a distorted output during audio playback. Correct the default
> clock rates for these clocks by specifying them in the clock init table
> for Tegra210.
>
> Cc: stable@vger.kernel.org
> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
> Acked-by: Thierry Reding <treding@nvidia.com>
> ---
Applied to clk-fixes
^ permalink raw reply [flat|nested] 3+ messages in thread
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2019-06-05 14:01 [PATCH V2] clk: tegra210: Fix default rates for HDA clocks Jon Hunter
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2019-06-13 15:53 ` Jon Hunter
2019-06-14 17:43 ` Stephen Boyd
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