* [PATCH] clk: sprd: add missing kfree
@ 2019-09-05 10:30 Chunyan Zhang
2019-09-12 5:47 ` Chunyan Zhang
2019-09-18 5:01 ` Stephen Boyd
0 siblings, 2 replies; 3+ messages in thread
From: Chunyan Zhang @ 2019-09-05 10:30 UTC (permalink / raw)
To: Stephen Boyd; +Cc: linux-clk, linux-kernel, Chunyan Zhang
From: Chunyan Zhang <chunyan.zhang@unisoc.com>
The number of config registers for different pll clocks probably are not
same, so we have to use malloc, and should free the memory before return.
Fixes: 3e37b005580b ("clk: sprd: add adjustable pll support")
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
Signed-off-by: Chunyan Zhang <zhang.lyra@gmail.com>
---
drivers/clk/sprd/pll.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/sprd/pll.c b/drivers/clk/sprd/pll.c
index 36b4402bf09e..640270f51aa5 100644
--- a/drivers/clk/sprd/pll.c
+++ b/drivers/clk/sprd/pll.c
@@ -136,6 +136,7 @@ static unsigned long _sprd_pll_recalc_rate(const struct sprd_pll *pll,
k2 + refin * nint * CLK_PLL_1M;
}
+ kfree(cfg);
return rate;
}
@@ -222,6 +223,7 @@ static int _sprd_pll_set_rate(const struct sprd_pll *pll,
if (!ret)
udelay(pll->udelay);
+ kfree(cfg);
return ret;
}
--
2.20.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] clk: sprd: add missing kfree
2019-09-05 10:30 [PATCH] clk: sprd: add missing kfree Chunyan Zhang
@ 2019-09-12 5:47 ` Chunyan Zhang
2019-09-18 5:01 ` Stephen Boyd
1 sibling, 0 replies; 3+ messages in thread
From: Chunyan Zhang @ 2019-09-12 5:47 UTC (permalink / raw)
To: Stephen Boyd; +Cc: linux-clk, Linux Kernel Mailing List
gentle ping
On Thu, 5 Sep 2019 at 18:30, Chunyan Zhang <zhang.lyra@gmail.com> wrote:
>
> From: Chunyan Zhang <chunyan.zhang@unisoc.com>
>
> The number of config registers for different pll clocks probably are not
> same, so we have to use malloc, and should free the memory before return.
>
> Fixes: 3e37b005580b ("clk: sprd: add adjustable pll support")
> Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
> Signed-off-by: Chunyan Zhang <zhang.lyra@gmail.com>
> ---
> drivers/clk/sprd/pll.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/clk/sprd/pll.c b/drivers/clk/sprd/pll.c
> index 36b4402bf09e..640270f51aa5 100644
> --- a/drivers/clk/sprd/pll.c
> +++ b/drivers/clk/sprd/pll.c
> @@ -136,6 +136,7 @@ static unsigned long _sprd_pll_recalc_rate(const struct sprd_pll *pll,
> k2 + refin * nint * CLK_PLL_1M;
> }
>
> + kfree(cfg);
> return rate;
> }
>
> @@ -222,6 +223,7 @@ static int _sprd_pll_set_rate(const struct sprd_pll *pll,
> if (!ret)
> udelay(pll->udelay);
>
> + kfree(cfg);
> return ret;
> }
>
> --
> 2.20.1
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] clk: sprd: add missing kfree
2019-09-05 10:30 [PATCH] clk: sprd: add missing kfree Chunyan Zhang
2019-09-12 5:47 ` Chunyan Zhang
@ 2019-09-18 5:01 ` Stephen Boyd
1 sibling, 0 replies; 3+ messages in thread
From: Stephen Boyd @ 2019-09-18 5:01 UTC (permalink / raw)
To: Chunyan Zhang; +Cc: linux-clk, linux-kernel, Chunyan Zhang
Quoting Chunyan Zhang (2019-09-05 03:30:09)
> From: Chunyan Zhang <chunyan.zhang@unisoc.com>
>
> The number of config registers for different pll clocks probably are not
> same, so we have to use malloc, and should free the memory before return.
>
> Fixes: 3e37b005580b ("clk: sprd: add adjustable pll support")
> Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
> Signed-off-by: Chunyan Zhang <zhang.lyra@gmail.com>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2019-09-18 5:01 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2019-09-05 10:30 [PATCH] clk: sprd: add missing kfree Chunyan Zhang
2019-09-12 5:47 ` Chunyan Zhang
2019-09-18 5:01 ` Stephen Boyd
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