Re: [PATCH v2] dt-bindings: clk: Make example a bit clearer

["Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>]

Hello,

On Wed, Sep 11, 2019 at 09:06:47AM -0700, Stephen Boyd wrote:
> > diff --git a/Documentation/devicetree/bindings/clock/clock-bindings.txt b/Documentation/devicetree/bindings/clock/clock-bindings.txt
> > index b646bbcf7f92..1d4942380918 100644
> > --- a/Documentation/devicetree/bindings/clock/clock-bindings.txt
> > +++ b/Documentation/devicetree/bindings/clock/clock-bindings.txt
> > @@ -150,16 +150,18 @@ set to 0, or can be omitted if it is not followed by any non-zero entry.
> >          compatible = "fsl,imx-uart";
> >          reg = <0xa000 0x1000>;
> >          ...
> > -        clocks = <&osc 0>, <&pll 1>;
> > -        clock-names = "baud", "register";
> > +        clocks = ...
> > +        clock-names = ...
> 
> I don't see the need for this change.

<&pll 1> is mentioned below. But it is not this instance that is
relevant. So I suggested to get rid of it to not be a source of
confusion. (But I guess you understood that.)

> >          assigned-clocks = <&clkcon 0>, <&pll 2>;
> > -        assigned-clock-parents = <&pll 2>;
> > +        assigned-clock-parents = <&pll 1>;
> >          assigned-clock-rates = <0>, <460800>;
> >      };
> >  
> > -In this example the <&pll 2> clock is set as parent of clock <&clkcon 0> and
> > -the <&pll 2> clock is assigned a frequency value of 460800 Hz.
> > +In this example the <&pll 1> clock is set as parent of clock <&clkcon 0> and
> > +the <&pll 2> clock is assigned a frequency value of 460800 Hz.  A parent
> > +setting for <&pll 2> is omitted (end of list) and rate setting for <&clkcon 0>
> > +is skipped because set to <0>.
> 
> Maybe you can comment that the "clocks" and "clock-names" properties
> don't matter for assigned clk rates and parents.

Sure, a long text can explain this, but a maximal simple example is
very beneficial, too.

Best regards
Uwe

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Pengutronix e.K.                           | Uwe Kleine-König            |
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