Re: [PATCH v1] clk: qcom: Skip halt checks on gcc_pcie_0_pipe_clk for 8998

[Stephen Boyd <sboyd@kernel.org>]

Quoting Manu Gautam (2019-10-09 01:31:09)
> On 3/30/2019 4:02 AM, Stephen Boyd wrote:
> > Quoting Marc Gonzalez (2019-03-28 09:26:59)
> >> On 25/03/2019 14:49, Marc Gonzalez wrote:
> >>
> >>>               .enable_mask = BIT(0),
> >> Actually, 5f2420ed2189 is not the only similar instance.
> >>
> >> $ git log --oneline -G BRANCH_HALT_SKIP drivers/clk/qcom | grep -v controller
> >> 924a86bf9793 clk: qcom: Skip halt checks on gcc_pcie_0_pipe_clk for 8998
> >> 5f2420ed2189 clk: qcom: Skip halt checks on gcc_usb3_phy_pipe_clk for 8998
> >> 2abf856202fd clk: qcom: gcc-msm8998: Disable halt check of UFS clocks
> >> 5f75b78d3d67 clk: qcom: gcc-msm8996: Disable halt check on UFS tx clock
> >> 12d807cd34b8 clk: qcom: gcc-msm8996: Disable halt check on UFS clocks
> >> 096abdc296f1 clk: msm8996-gcc: Mark halt check as no-op for USB/PCIE pipe_clk
> >> 7d99ced8f4c6 clk: qcom: Add support for BRANCH_HALT_SKIP flag for branch clocks
> >>
> > I keep asking Qualcomm engineers everytime this comes up why they can't
> > fix their phy initialization sequence.
> >
> > Too bad they don't care anymore!
> 
> 
> I have followed this up with QMP PHY hardware designers and they have
> confirmed that QMP PHY must have pipe clock enabled at the beginning
> of initialization sequence i.e. before bringing it out of reset and starting it.

Awesome, thanks for following up.

> 
> Otherwise there is possibility of incorrect locking of pipe_interface/
> retime buffers in PHY.
> Hence, for both USB and PCIe we have to continue to use HALT_SKIP flag.

Does anything go wrong if we just leave these clks enabled forever out
of boot? I'm inclined to rip the clks out and just slam the branch
enable bit on all the time in gcc driver probe and return NULL to the
callers of clk_get() for these clks. I don't see how this would be a
problem because when the upstream phy is disabled this clk is disabled
and so we aren't wasting power. It should also save us time and memory
because now we don't have to call into the clk framework to turn it on
and sequence that just right in the phy driver.