* [PATCH 2/3] clk: imx: imx8mn: mark sys_pll1/2 as fixed clock
2019-10-09 9:58 [PATCH 1/3] clk: imx: imx8mm: mark sys_pll1/2 as fixed clock Peng Fan
@ 2019-10-09 9:58 ` Peng Fan
2019-10-09 9:58 ` [PATCH 3/3] clk: imx: imx8mq: mark sys1/2_pll " Peng Fan
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Peng Fan @ 2019-10-09 9:58 UTC (permalink / raw)
To: mturquette, sboyd, shawnguo, s.hauer, festevam
Cc: kernel, dl-linux-imx, Anson Huang, Jacky Bai, Abel Vesa,
linux-clk, linux-arm-kernel, linux-kernel, Leonard Crestez,
Peng Fan
From: Peng Fan <peng.fan@nxp.com>
According Architecture definition guide, SYS_PLL1 is fixed at
800MHz, SYS_PLL2 is fixed at 1000MHz, so let's use imx_clk_fixed
to register the clocks and drop code that could change the rate.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/clk/imx/clk-imx8mn.c | 14 ++++----------
1 file changed, 4 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index 7a5590b967d5..28467db10c69 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -47,8 +47,6 @@ static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_se
static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
static const char * const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", };
static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
-static const char * const sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
-static const char * const sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
static const char * const imx8mn_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m",
@@ -336,8 +334,6 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
clks[IMX8MN_GPU_PLL_REF_SEL] = imx_clk_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
clks[IMX8MN_VPU_PLL_REF_SEL] = imx_clk_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
clks[IMX8MN_ARM_PLL_REF_SEL] = imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- clks[IMX8MN_SYS_PLL1_REF_SEL] = imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- clks[IMX8MN_SYS_PLL2_REF_SEL] = imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
clks[IMX8MN_SYS_PLL3_REF_SEL] = imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
clks[IMX8MN_AUDIO_PLL1] = imx_clk_pll14xx("audio_pll1", "audio_pll1_ref_sel", base, &imx_1443x_pll);
@@ -347,8 +343,8 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
clks[IMX8MN_GPU_PLL] = imx_clk_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx_1416x_pll);
clks[IMX8MN_VPU_PLL] = imx_clk_pll14xx("vpu_pll", "vpu_pll_ref_sel", base + 0x74, &imx_1416x_pll);
clks[IMX8MN_ARM_PLL] = imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx_1416x_pll);
- clks[IMX8MN_SYS_PLL1] = imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel", base + 0x94, &imx_1416x_pll);
- clks[IMX8MN_SYS_PLL2] = imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel", base + 0x104, &imx_1416x_pll);
+ clks[IMX8MN_SYS_PLL1] = imx_clk_fixed("sys_pll1", 800000000);
+ clks[IMX8MN_SYS_PLL2] = imx_clk_fixed("sys_pll2", 1000000000);
clks[IMX8MN_SYS_PLL3] = imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx_1416x_pll);
/* PLL bypass out */
@@ -359,8 +355,6 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
clks[IMX8MN_GPU_PLL_BYPASS] = imx_clk_mux_flags("gpu_pll_bypass", base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
clks[IMX8MN_VPU_PLL_BYPASS] = imx_clk_mux_flags("vpu_pll_bypass", base + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
clks[IMX8MN_ARM_PLL_BYPASS] = imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 28, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT);
- clks[IMX8MN_SYS_PLL1_BYPASS] = imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 28, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT);
- clks[IMX8MN_SYS_PLL2_BYPASS] = imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 28, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT);
clks[IMX8MN_SYS_PLL3_BYPASS] = imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 28, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT);
/* PLL out gate */
@@ -371,8 +365,8 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
clks[IMX8MN_GPU_PLL_OUT] = imx_clk_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x64, 11);
clks[IMX8MN_VPU_PLL_OUT] = imx_clk_gate("vpu_pll_out", "vpu_pll_bypass", base + 0x74, 11);
clks[IMX8MN_ARM_PLL_OUT] = imx_clk_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 11);
- clks[IMX8MN_SYS_PLL1_OUT] = imx_clk_gate("sys_pll1_out", "sys_pll1_bypass", base + 0x94, 11);
- clks[IMX8MN_SYS_PLL2_OUT] = imx_clk_gate("sys_pll2_out", "sys_pll2_bypass", base + 0x104, 11);
+ clks[IMX8MN_SYS_PLL1_OUT] = imx_clk_gate("sys_pll1_out", "sys_pll1", base + 0x94, 11);
+ clks[IMX8MN_SYS_PLL2_OUT] = imx_clk_gate("sys_pll2_out", "sys_pll2", base + 0x104, 11);
clks[IMX8MN_SYS_PLL3_OUT] = imx_clk_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11);
/* SYS PLL fixed output */
--
2.16.4
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 3/3] clk: imx: imx8mq: mark sys1/2_pll as fixed clock
2019-10-09 9:58 [PATCH 1/3] clk: imx: imx8mm: mark sys_pll1/2 as fixed clock Peng Fan
2019-10-09 9:58 ` [PATCH 2/3] clk: imx: imx8mn: " Peng Fan
@ 2019-10-09 9:58 ` Peng Fan
2019-10-20 14:24 ` [PATCH 1/3] clk: imx: imx8mm: mark sys_pll1/2 " Abel Vesa
2019-10-25 6:08 ` Shawn Guo
3 siblings, 0 replies; 7+ messages in thread
From: Peng Fan @ 2019-10-09 9:58 UTC (permalink / raw)
To: mturquette, sboyd, shawnguo, s.hauer, festevam
Cc: kernel, dl-linux-imx, Anson Huang, Jacky Bai, Abel Vesa,
linux-clk, linux-arm-kernel, linux-kernel, Leonard Crestez,
Peng Fan
From: Peng Fan <peng.fan@nxp.com>
According Architecture definition guide, SYS1_PLL is fixed at
800MHz, SYS2_PLL is fixed at 1000MHz, so let's use imx_clk_fixed
to register the clocks and drop code that could change the rate.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/clk/imx/clk-imx8mq.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
index 41fc9c63356e..403f6ba4c638 100644
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -34,8 +34,6 @@ static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_
static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", };
static const char * const video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", };
-static const char * const sys1_pll_out_sels[] = {"sys1_pll1_ref_sel", };
-static const char * const sys2_pll_out_sels[] = {"sys1_pll1_ref_sel", "sys2_pll1_ref_sel", };
static const char * const sys3_pll_out_sels[] = {"sys3_pll1_ref_sel", "sys2_pll1_ref_sel", };
static const char * const dram_pll_out_sels[] = {"dram_pll1_ref_sel", };
@@ -307,8 +305,6 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
clks[IMX8MQ_AUDIO_PLL1_REF_SEL] = imx_clk_mux("audio_pll1_ref_sel", base + 0x0, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
clks[IMX8MQ_AUDIO_PLL2_REF_SEL] = imx_clk_mux("audio_pll2_ref_sel", base + 0x8, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
clks[IMX8MQ_VIDEO_PLL1_REF_SEL] = imx_clk_mux("video_pll1_ref_sel", base + 0x10, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- clks[IMX8MQ_SYS1_PLL1_REF_SEL] = imx_clk_mux("sys1_pll1_ref_sel", base + 0x30, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- clks[IMX8MQ_SYS2_PLL1_REF_SEL] = imx_clk_mux("sys2_pll1_ref_sel", base + 0x3c, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
clks[IMX8MQ_SYS3_PLL1_REF_SEL] = imx_clk_mux("sys3_pll1_ref_sel", base + 0x48, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
clks[IMX8MQ_DRAM_PLL1_REF_SEL] = imx_clk_mux("dram_pll1_ref_sel", base + 0x60, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
@@ -342,8 +338,8 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
clks[IMX8MQ_AUDIO_PLL2_OUT] = imx_clk_gate("audio_pll2_out", "audio_pll2_bypass", base + 0x8, 21);
clks[IMX8MQ_VIDEO_PLL1_OUT] = imx_clk_gate("video_pll1_out", "video_pll1_bypass", base + 0x10, 21);
- clks[IMX8MQ_SYS1_PLL_OUT] = imx_clk_sccg_pll("sys1_pll_out", sys1_pll_out_sels, ARRAY_SIZE(sys1_pll_out_sels), 0, 0, 0, base + 0x30, CLK_IS_CRITICAL);
- clks[IMX8MQ_SYS2_PLL_OUT] = imx_clk_sccg_pll("sys2_pll_out", sys2_pll_out_sels, ARRAY_SIZE(sys2_pll_out_sels), 0, 0, 1, base + 0x3c, CLK_IS_CRITICAL);
+ clks[IMX8MQ_SYS1_PLL_OUT] = imx_clk_fixed("sys1_pll_out", 800000000);
+ clks[IMX8MQ_SYS2_PLL_OUT] = imx_clk_fixed("sys2_pll_out", 1000000000);
clks[IMX8MQ_SYS3_PLL_OUT] = imx_clk_sccg_pll("sys3_pll_out", sys3_pll_out_sels, ARRAY_SIZE(sys3_pll_out_sels), 0, 0, 1, base + 0x48, CLK_IS_CRITICAL);
clks[IMX8MQ_DRAM_PLL_OUT] = imx_clk_sccg_pll("dram_pll_out", dram_pll_out_sels, ARRAY_SIZE(dram_pll_out_sels), 0, 0, 0, base + 0x60, CLK_IS_CRITICAL);
/* SYS PLL fixed output */
--
2.16.4
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH 1/3] clk: imx: imx8mm: mark sys_pll1/2 as fixed clock
2019-10-09 9:58 [PATCH 1/3] clk: imx: imx8mm: mark sys_pll1/2 as fixed clock Peng Fan
2019-10-09 9:58 ` [PATCH 2/3] clk: imx: imx8mn: " Peng Fan
2019-10-09 9:58 ` [PATCH 3/3] clk: imx: imx8mq: mark sys1/2_pll " Peng Fan
@ 2019-10-20 14:24 ` Abel Vesa
2019-10-25 6:08 ` Shawn Guo
3 siblings, 0 replies; 7+ messages in thread
From: Abel Vesa @ 2019-10-20 14:24 UTC (permalink / raw)
To: Peng Fan
Cc: mturquette, sboyd, shawnguo, s.hauer, festevam, kernel,
dl-linux-imx, Anson Huang, Jacky Bai, linux-clk,
linux-arm-kernel, linux-kernel, Leonard Crestez
On 19-10-09 09:58:14, Peng Fan wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> According Architecture definition guide, SYS_PLL1 is fixed at
> 800MHz, SYS_PLL2 is fixed at 1000MHz, so let's use imx_clk_fixed
> to register the clocks and drop code that could change the rate.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
For the entire series:
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
> ---
> drivers/clk/imx/clk-imx8mm.c | 14 ++++----------
> 1 file changed, 4 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
> index 04876ec66127..ae7321ab7837 100644
> --- a/drivers/clk/imx/clk-imx8mm.c
> +++ b/drivers/clk/imx/clk-imx8mm.c
> @@ -34,8 +34,6 @@ static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
> static const char *gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
> static const char *vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", };
> static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
> -static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
> -static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
> static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
>
> /* CCM ROOT */
> @@ -325,8 +323,6 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
> clks[IMX8MM_GPU_PLL_REF_SEL] = imx_clk_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
> clks[IMX8MM_VPU_PLL_REF_SEL] = imx_clk_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
> clks[IMX8MM_ARM_PLL_REF_SEL] = imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
> - clks[IMX8MM_SYS_PLL1_REF_SEL] = imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
> - clks[IMX8MM_SYS_PLL2_REF_SEL] = imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
> clks[IMX8MM_SYS_PLL3_REF_SEL] = imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
>
> clks[IMX8MM_AUDIO_PLL1] = imx_clk_pll14xx("audio_pll1", "audio_pll1_ref_sel", base, &imx_1443x_pll);
> @@ -336,8 +332,8 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
> clks[IMX8MM_GPU_PLL] = imx_clk_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx_1416x_pll);
> clks[IMX8MM_VPU_PLL] = imx_clk_pll14xx("vpu_pll", "vpu_pll_ref_sel", base + 0x74, &imx_1416x_pll);
> clks[IMX8MM_ARM_PLL] = imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx_1416x_pll);
> - clks[IMX8MM_SYS_PLL1] = imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel", base + 0x94, &imx_1416x_pll);
> - clks[IMX8MM_SYS_PLL2] = imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel", base + 0x104, &imx_1416x_pll);
> + clks[IMX8MM_SYS_PLL1] = imx_clk_fixed("sys_pll1", 800000000);
> + clks[IMX8MM_SYS_PLL2] = imx_clk_fixed("sys_pll2", 1000000000);
> clks[IMX8MM_SYS_PLL3] = imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx_1416x_pll);
>
> /* PLL bypass out */
> @@ -348,8 +344,6 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
> clks[IMX8MM_GPU_PLL_BYPASS] = imx_clk_mux_flags("gpu_pll_bypass", base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
> clks[IMX8MM_VPU_PLL_BYPASS] = imx_clk_mux_flags("vpu_pll_bypass", base + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
> clks[IMX8MM_ARM_PLL_BYPASS] = imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 28, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT);
> - clks[IMX8MM_SYS_PLL1_BYPASS] = imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 28, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT);
> - clks[IMX8MM_SYS_PLL2_BYPASS] = imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 28, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT);
> clks[IMX8MM_SYS_PLL3_BYPASS] = imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 28, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT);
>
> /* PLL out gate */
> @@ -360,8 +354,8 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
> clks[IMX8MM_GPU_PLL_OUT] = imx_clk_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x64, 11);
> clks[IMX8MM_VPU_PLL_OUT] = imx_clk_gate("vpu_pll_out", "vpu_pll_bypass", base + 0x74, 11);
> clks[IMX8MM_ARM_PLL_OUT] = imx_clk_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 11);
> - clks[IMX8MM_SYS_PLL1_OUT] = imx_clk_gate("sys_pll1_out", "sys_pll1_bypass", base + 0x94, 11);
> - clks[IMX8MM_SYS_PLL2_OUT] = imx_clk_gate("sys_pll2_out", "sys_pll2_bypass", base + 0x104, 11);
> + clks[IMX8MM_SYS_PLL1_OUT] = imx_clk_gate("sys_pll1_out", "sys_pll1", base + 0x94, 11);
> + clks[IMX8MM_SYS_PLL2_OUT] = imx_clk_gate("sys_pll2_out", "sys_pll2", base + 0x104, 11);
> clks[IMX8MM_SYS_PLL3_OUT] = imx_clk_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11);
>
> /* SYS PLL fixed output */
> --
> 2.16.4
>
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH 1/3] clk: imx: imx8mm: mark sys_pll1/2 as fixed clock
2019-10-09 9:58 [PATCH 1/3] clk: imx: imx8mm: mark sys_pll1/2 as fixed clock Peng Fan
` (2 preceding siblings ...)
2019-10-20 14:24 ` [PATCH 1/3] clk: imx: imx8mm: mark sys_pll1/2 " Abel Vesa
@ 2019-10-25 6:08 ` Shawn Guo
2019-10-25 6:14 ` Peng Fan
3 siblings, 1 reply; 7+ messages in thread
From: Shawn Guo @ 2019-10-25 6:08 UTC (permalink / raw)
To: Peng Fan
Cc: mturquette, sboyd, s.hauer, festevam, kernel, dl-linux-imx,
Anson Huang, Jacky Bai, Abel Vesa, linux-clk, linux-arm-kernel,
linux-kernel, Leonard Crestez
On Wed, Oct 09, 2019 at 09:58:14AM +0000, Peng Fan wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> According Architecture definition guide, SYS_PLL1 is fixed at
> 800MHz, SYS_PLL2 is fixed at 1000MHz, so let's use imx_clk_fixed
> to register the clocks and drop code that could change the rate.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Applied all, thanks.
^ permalink raw reply [flat|nested] 7+ messages in thread* RE: [PATCH 1/3] clk: imx: imx8mm: mark sys_pll1/2 as fixed clock
2019-10-25 6:08 ` Shawn Guo
@ 2019-10-25 6:14 ` Peng Fan
2019-10-25 9:08 ` Shawn Guo
0 siblings, 1 reply; 7+ messages in thread
From: Peng Fan @ 2019-10-25 6:14 UTC (permalink / raw)
To: Shawn Guo
Cc: mturquette, sboyd, s.hauer, festevam, kernel, dl-linux-imx,
Anson Huang, Jacky Bai, Abel Vesa, linux-clk, linux-arm-kernel,
linux-kernel, Leonard Crestez
Hi Shawn,
> Subject: Re: [PATCH 1/3] clk: imx: imx8mm: mark sys_pll1/2 as fixed clock
>
> On Wed, Oct 09, 2019 at 09:58:14AM +0000, Peng Fan wrote:
> > From: Peng Fan <peng.fan@nxp.com>
> >
> > According Architecture definition guide, SYS_PLL1 is fixed at 800MHz,
> > SYS_PLL2 is fixed at 1000MHz, so let's use imx_clk_fixed to register
> > the clocks and drop code that could change the rate.
> >
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
>
> Applied all, thanks.
I have a v2 https://patchwork.kernel.org/cover/11208131/ patch
based on Lenoard's v3
https://patchwork.kernel.org/patch/11193189/ to avoid conflicts
when you apply Lenoard's v3 patch.
It is fine you take my v1, but you will have conflicts if you take
Leonard's v3 after apply my v1.
Regards,
Peng.
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/3] clk: imx: imx8mm: mark sys_pll1/2 as fixed clock
2019-10-25 6:14 ` Peng Fan
@ 2019-10-25 9:08 ` Shawn Guo
0 siblings, 0 replies; 7+ messages in thread
From: Shawn Guo @ 2019-10-25 9:08 UTC (permalink / raw)
To: Peng Fan
Cc: mturquette, sboyd, s.hauer, festevam, kernel, dl-linux-imx,
Anson Huang, Jacky Bai, Abel Vesa, linux-clk, linux-arm-kernel,
linux-kernel, Leonard Crestez
On Fri, Oct 25, 2019 at 06:14:21AM +0000, Peng Fan wrote:
> Hi Shawn,
>
> > Subject: Re: [PATCH 1/3] clk: imx: imx8mm: mark sys_pll1/2 as fixed clock
> >
> > On Wed, Oct 09, 2019 at 09:58:14AM +0000, Peng Fan wrote:
> > > From: Peng Fan <peng.fan@nxp.com>
> > >
> > > According Architecture definition guide, SYS_PLL1 is fixed at 800MHz,
> > > SYS_PLL2 is fixed at 1000MHz, so let's use imx_clk_fixed to register
> > > the clocks and drop code that could change the rate.
> > >
> > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> >
> > Applied all, thanks.
>
> I have a v2 https://patchwork.kernel.org/cover/11208131/ patch
> based on Lenoard's v3
> https://patchwork.kernel.org/patch/11193189/ to avoid conflicts
> when you apply Lenoard's v3 patch.
Okay, I replaced it with your v2 series. Thanks!
Shawn
^ permalink raw reply [flat|nested] 7+ messages in thread