* [PATCH 0/2] Unbreak parent selection on MMP2 timer mux
@ 2019-12-18 19:04 Lubomir Rintel
2019-12-18 19:04 ` [PATCH 1/2] ARM: mmp: do not divide the clock rate Lubomir Rintel
2019-12-18 19:04 ` [PATCH 2/2] clk: mmp2: Fix the order of timer mux parents Lubomir Rintel
0 siblings, 2 replies; 4+ messages in thread
From: Lubomir Rintel @ 2019-12-18 19:04 UTC (permalink / raw)
To: Olof Johansson
Cc: Arnd Bergmann, Michael Turquette, Stephen Boyd, soc,
linux-arm-kernel, linux-clk, linux-kernel
Hi,
Patches chained to this message fix timer mux parent determination on
MMP2.
They need to go together -- I'm hoping that they'll get acks from CLK
maintainers and make it in via the SoC tree.
Thanks,
Lubo
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 1/2] ARM: mmp: do not divide the clock rate
2019-12-18 19:04 [PATCH 0/2] Unbreak parent selection on MMP2 timer mux Lubomir Rintel
@ 2019-12-18 19:04 ` Lubomir Rintel
2019-12-18 19:04 ` [PATCH 2/2] clk: mmp2: Fix the order of timer mux parents Lubomir Rintel
1 sibling, 0 replies; 4+ messages in thread
From: Lubomir Rintel @ 2019-12-18 19:04 UTC (permalink / raw)
To: Olof Johansson
Cc: Arnd Bergmann, Michael Turquette, Stephen Boyd, soc,
linux-arm-kernel, linux-clk, linux-kernel, Lubomir Rintel
This was done because the clock driver returned the wrong rate, which is
fixed in "clk: mmp2: Fix the order of timer mux parents" patch.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
---
arch/arm/mach-mmp/time.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c
index 110dcb3314d13..c65cfc1ad99b4 100644
--- a/arch/arm/mach-mmp/time.c
+++ b/arch/arm/mach-mmp/time.c
@@ -207,7 +207,7 @@ static int __init mmp_dt_init_timer(struct device_node *np)
ret = clk_prepare_enable(clk);
if (ret)
return ret;
- rate = clk_get_rate(clk) / 2;
+ rate = clk_get_rate(clk);
} else if (cpu_is_pj4()) {
rate = 6500000;
} else {
--
2.23.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/2] clk: mmp2: Fix the order of timer mux parents
2019-12-18 19:04 [PATCH 0/2] Unbreak parent selection on MMP2 timer mux Lubomir Rintel
2019-12-18 19:04 ` [PATCH 1/2] ARM: mmp: do not divide the clock rate Lubomir Rintel
@ 2019-12-18 19:04 ` Lubomir Rintel
2019-12-19 5:14 ` Stephen Boyd
1 sibling, 1 reply; 4+ messages in thread
From: Lubomir Rintel @ 2019-12-18 19:04 UTC (permalink / raw)
To: Olof Johansson
Cc: Arnd Bergmann, Michael Turquette, Stephen Boyd, soc,
linux-arm-kernel, linux-clk, linux-kernel, Lubomir Rintel
Determined empirically, no documentation is available.
The OLPC XO-1.75 laptop used parent 1, that one being VCTCXO/4 (65MHz), but
thought it's a VCTCXO/2 (130MHz). The mmp2 timer driver, not knowing
what is going on, ended up just dividing the rate as of
commit f36797ee4380 ("ARM: mmp/mmp2: dt: enable the clock")'
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
---
drivers/clk/mmp/clk-of-mmp2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/mmp/clk-of-mmp2.c b/drivers/clk/mmp/clk-of-mmp2.c
index e7e264f26a50d..24af9241bfa06 100644
--- a/drivers/clk/mmp/clk-of-mmp2.c
+++ b/drivers/clk/mmp/clk-of-mmp2.c
@@ -154,7 +154,7 @@ static DEFINE_SPINLOCK(ssp3_lock);
static const char *ssp_parent_names[] = {"vctcxo_4", "vctcxo_2", "vctcxo", "pll1_16"};
static DEFINE_SPINLOCK(timer_lock);
-static const char *timer_parent_names[] = {"clk32", "vctcxo_2", "vctcxo_4", "vctcxo"};
+static const char *timer_parent_names[] = {"clk32", "vctcxo_4", "vctcxo_2", "vctcxo"};
static DEFINE_SPINLOCK(reset_lock);
--
2.23.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 2/2] clk: mmp2: Fix the order of timer mux parents
2019-12-18 19:04 ` [PATCH 2/2] clk: mmp2: Fix the order of timer mux parents Lubomir Rintel
@ 2019-12-19 5:14 ` Stephen Boyd
0 siblings, 0 replies; 4+ messages in thread
From: Stephen Boyd @ 2019-12-19 5:14 UTC (permalink / raw)
To: Lubomir Rintel, Olof Johansson
Cc: Arnd Bergmann, Michael Turquette, soc, linux-arm-kernel,
linux-clk, linux-kernel, Lubomir Rintel
Quoting Lubomir Rintel (2019-12-18 11:04:54)
> Determined empirically, no documentation is available.
>
> The OLPC XO-1.75 laptop used parent 1, that one being VCTCXO/4 (65MHz), but
> thought it's a VCTCXO/2 (130MHz). The mmp2 timer driver, not knowing
> what is going on, ended up just dividing the rate as of
> commit f36797ee4380 ("ARM: mmp/mmp2: dt: enable the clock")'
>
> Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
> ---
Any Fixes: tag?
Acked-by: Stephen Boyd <sboyd@kernel.org>
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2019-12-19 5:14 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2019-12-18 19:04 [PATCH 0/2] Unbreak parent selection on MMP2 timer mux Lubomir Rintel
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2019-12-18 19:04 ` [PATCH 2/2] clk: mmp2: Fix the order of timer mux parents Lubomir Rintel
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