* [PATCH v2 0/2] clk: qcom: gcc-msm8996: Fix CLKREF parenting @ 2020-01-06 8:05 Bjorn Andersson 2020-01-06 8:05 ` [PATCH v2 1/2] clk: qcom: gcc-msm8996: Fix parent for CLKREF clocks Bjorn Andersson 2020-01-06 8:05 ` [PATCH v2 2/2] arm64: dts: qcom: msm8996: Define parent clocks for gcc Bjorn Andersson 0 siblings, 2 replies; 5+ messages in thread From: Bjorn Andersson @ 2020-01-06 8:05 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel We've always seen intermittent resets of msm8996 during boot, seemingly related to PCIe somehow. The likely cause of these errors are the fact that the CLKREF of all PHYs are parented by LN_BB, which while being on during boot is disabled by the UFS host driver if it fails to find its PHY. As such, depending on the timeing (and success) of the UFS initialization, PCIe might loose its clocking. These two patches ensures that LN_BB, connected to the CXO2 pad on the SoC, is described as parent for all the CLKREF clocks. So that they all vote for this clock appropriately. Bjorn Andersson (2): clk: qcom: gcc-msm8996: Fix parent for CLKREF clocks arm64: dts: qcom: msm8996: Define parent clocks for gcc .../devicetree/bindings/clock/qcom,gcc.yaml | 10 ++++++ arch/arm64/boot/dts/qcom/msm8996.dtsi | 3 ++ drivers/clk/qcom/gcc-msm8996.c | 35 +++++++++++++++---- 3 files changed, 41 insertions(+), 7 deletions(-) -- 2.24.0 ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2 1/2] clk: qcom: gcc-msm8996: Fix parent for CLKREF clocks 2020-01-06 8:05 [PATCH v2 0/2] clk: qcom: gcc-msm8996: Fix CLKREF parenting Bjorn Andersson @ 2020-01-06 8:05 ` Bjorn Andersson 2020-01-06 16:55 ` Stephen Boyd 2020-01-06 8:05 ` [PATCH v2 2/2] arm64: dts: qcom: msm8996: Define parent clocks for gcc Bjorn Andersson 1 sibling, 1 reply; 5+ messages in thread From: Bjorn Andersson @ 2020-01-06 8:05 UTC (permalink / raw) To: Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland Cc: Andy Gross, linux-arm-msm, linux-clk, devicetree, linux-kernel The CLKREF clocks are all fed by the clock signal on the CXO2 pad on the SoC. Update the definition of these clocks to allow this to be wired up to the appropriate clock source. Retain "xo" as the global named parent to make the change a nop in the event that DT doesn't carry the necessary clocks definition. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> --- Changes since v1: - Rewrote DT binding part after the binding changed structure .../devicetree/bindings/clock/qcom,gcc.yaml | 10 ++++++ drivers/clk/qcom/gcc-msm8996.c | 35 +++++++++++++++---- 2 files changed, 38 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml index f2b5cd6fe0fe..8535ed93766b 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml @@ -47,6 +47,11 @@ properties: - description: Board XO source - description: Board active XO source - description: Sleep clock source + #qcom,gcc-msm8996 + - items: + - description: XO source + - description: Second XO source + - description: Sleep clock source #qcom,gcc-msm8998 - items: - description: Board XO source @@ -65,6 +70,11 @@ properties: - const: bi_tcxo - const: bi_tcxo_ao - const: sleep_clk + #qcom,gcc-msm8996 + - items: + - const: cxo + - const: cxo2 + - const: sleep_clk #qcom,gcc-msm8998 - items: - const: xo diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c index d004cdaa0e39..3c3a7ff04562 100644 --- a/drivers/clk/qcom/gcc-msm8996.c +++ b/drivers/clk/qcom/gcc-msm8996.c @@ -3046,7 +3046,10 @@ static struct clk_branch gcc_usb3_clkref_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb3_clkref_clk", - .parent_names = (const char *[]){ "xo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "cxo2", + .name = "xo", + }, .num_parents = 1, .ops = &clk_branch2_ops, }, @@ -3060,7 +3063,10 @@ static struct clk_branch gcc_hdmi_clkref_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_hdmi_clkref_clk", - .parent_names = (const char *[]){ "xo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "cxo2", + .name = "xo", + }, .num_parents = 1, .ops = &clk_branch2_ops, }, @@ -3074,7 +3080,10 @@ static struct clk_branch gcc_edp_clkref_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_edp_clkref_clk", - .parent_names = (const char *[]){ "xo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "cxo2", + .name = "xo", + }, .num_parents = 1, .ops = &clk_branch2_ops, }, @@ -3088,7 +3097,10 @@ static struct clk_branch gcc_ufs_clkref_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_clkref_clk", - .parent_names = (const char *[]){ "xo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "cxo2", + .name = "xo", + }, .num_parents = 1, .ops = &clk_branch2_ops, }, @@ -3102,7 +3114,10 @@ static struct clk_branch gcc_pcie_clkref_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_clkref_clk", - .parent_names = (const char *[]){ "xo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "cxo2", + .name = "xo", + }, .num_parents = 1, .ops = &clk_branch2_ops, }, @@ -3116,7 +3131,10 @@ static struct clk_branch gcc_rx2_usb2_clkref_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_rx2_usb2_clkref_clk", - .parent_names = (const char *[]){ "xo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "cxo2", + .name = "xo", + }, .num_parents = 1, .ops = &clk_branch2_ops, }, @@ -3130,7 +3148,10 @@ static struct clk_branch gcc_rx1_usb2_clkref_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_rx1_usb2_clkref_clk", - .parent_names = (const char *[]){ "xo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "cxo2", + .name = "xo", + }, .num_parents = 1, .ops = &clk_branch2_ops, }, -- 2.24.0 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v2 1/2] clk: qcom: gcc-msm8996: Fix parent for CLKREF clocks 2020-01-06 8:05 ` [PATCH v2 1/2] clk: qcom: gcc-msm8996: Fix parent for CLKREF clocks Bjorn Andersson @ 2020-01-06 16:55 ` Stephen Boyd 0 siblings, 0 replies; 5+ messages in thread From: Stephen Boyd @ 2020-01-06 16:55 UTC (permalink / raw) To: Bjorn Andersson, Mark Rutland, Michael Turquette, Rob Herring Cc: Andy Gross, linux-arm-msm, linux-clk, devicetree, linux-kernel Quoting Bjorn Andersson (2020-01-06 00:05:45) > The CLKREF clocks are all fed by the clock signal on the CXO2 pad on the > SoC. Update the definition of these clocks to allow this to be wired up > to the appropriate clock source. > > Retain "xo" as the global named parent to make the change a nop in the > event that DT doesn't carry the necessary clocks definition. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > --- Applied to clk-next ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2 2/2] arm64: dts: qcom: msm8996: Define parent clocks for gcc 2020-01-06 8:05 [PATCH v2 0/2] clk: qcom: gcc-msm8996: Fix CLKREF parenting Bjorn Andersson 2020-01-06 8:05 ` [PATCH v2 1/2] clk: qcom: gcc-msm8996: Fix parent for CLKREF clocks Bjorn Andersson @ 2020-01-06 8:05 ` Bjorn Andersson 2020-03-06 4:37 ` Vinod Koul 1 sibling, 1 reply; 5+ messages in thread From: Bjorn Andersson @ 2020-01-06 8:05 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson Cc: Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland, linux-arm-msm, linux-clk, devicetree, linux-kernel The CLKREF clocks in GCC are parented by RPM_SMD_LN_BB_CLK, through the CXO2 pad. Wire this up so that this is properly enabled when need by the various PHYs. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> --- Changes since v1: - Rebased patch arch/arm64/boot/dts/qcom/msm8996.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 023dafc6cfd4..b22a1b9cb9ce 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -443,6 +443,9 @@ gcc: clock-controller@300000 { #reset-cells = <1>; #power-domain-cells = <1>; reg = <0x00300000 0x90000>; + + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>; + clock-names = "cxo2"; }; tsens0: thermal-sensor@4a9000 { -- 2.24.0 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v2 2/2] arm64: dts: qcom: msm8996: Define parent clocks for gcc 2020-01-06 8:05 ` [PATCH v2 2/2] arm64: dts: qcom: msm8996: Define parent clocks for gcc Bjorn Andersson @ 2020-03-06 4:37 ` Vinod Koul 0 siblings, 0 replies; 5+ messages in thread From: Vinod Koul @ 2020-03-06 4:37 UTC (permalink / raw) To: Bjorn Andersson Cc: Andy Gross, Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland, linux-arm-msm, linux-clk, devicetree, linux-kernel On 06-01-20, 00:05, Bjorn Andersson wrote: > The CLKREF clocks in GCC are parented by RPM_SMD_LN_BB_CLK, through the > CXO2 pad. Wire this up so that this is properly enabled when need by the > various PHYs. Reviewed-by: Vinod Koul <vkoul@kernel.org> -- ~Vinod ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-03-06 4:37 UTC | newest] Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-01-06 8:05 [PATCH v2 0/2] clk: qcom: gcc-msm8996: Fix CLKREF parenting Bjorn Andersson 2020-01-06 8:05 ` [PATCH v2 1/2] clk: qcom: gcc-msm8996: Fix parent for CLKREF clocks Bjorn Andersson 2020-01-06 16:55 ` Stephen Boyd 2020-01-06 8:05 ` [PATCH v2 2/2] arm64: dts: qcom: msm8996: Define parent clocks for gcc Bjorn Andersson 2020-03-06 4:37 ` Vinod Koul
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