From: Thierry Reding <thierry.reding@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>
Cc: Jon Hunter <jonathanh@nvidia.com>,
Dmitry Osipenko <digetx@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Joseph Lo <josephl@nvidia.com>,
devicetree@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 1/8] clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210
Date: Tue, 10 Mar 2020 16:19:56 +0100 [thread overview]
Message-ID: <20200310152003.2945170-2-thierry.reding@gmail.com> (raw)
In-Reply-To: <20200310152003.2945170-1-thierry.reding@gmail.com>
From: Joseph Lo <josephl@nvidia.com>
Introduce the low jitter path of PLLP and PLLMB which can be used as EMC
clock source.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
drivers/clk/tegra/clk-tegra210.c | 11 +++++++++++
include/dt-bindings/clock/tegra210-car.h | 4 ++--
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 45d54ead30bc..f99647b4a71f 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -3161,6 +3161,17 @@ static void __init tegra210_pll_init(void __iomem *clk_base,
clk_register_clkdev(clk, "pll_m_ud", NULL);
clks[TEGRA210_CLK_PLL_M_UD] = clk;
+ /* PLLMB_UD */
+ clk = clk_register_fixed_factor(NULL, "pll_mb_ud", "pll_mb",
+ CLK_SET_RATE_PARENT, 1, 1);
+ clk_register_clkdev(clk, "pll_mb_ud", NULL);
+ clks[TEGRA210_CLK_PLL_MB_UD] = clk;
+
+ /* PLLP_UD */
+ clk = clk_register_fixed_factor(NULL, "pll_p_ud", "pll_p",
+ 0, 1, 1);
+ clks[TEGRA210_CLK_PLL_P_UD] = clk;
+
/* PLLU_VCO */
if (!tegra210_init_pllu()) {
clk = clk_register_fixed_rate(NULL, "pll_u_vco", "pll_ref", 0,
diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h
index 7a8f10b9a66d..5c93b01156d4 100644
--- a/include/dt-bindings/clock/tegra210-car.h
+++ b/include/dt-bindings/clock/tegra210-car.h
@@ -351,8 +351,8 @@
#define TEGRA210_CLK_PLL_P_OUT_XUSB 317
#define TEGRA210_CLK_XUSB_SSP_SRC 318
#define TEGRA210_CLK_PLL_RE_OUT1 319
-/* 320 */
-/* 321 */
+#define TEGRA210_CLK_PLL_MB_UD 320
+#define TEGRA210_CLK_PLL_P_UD 321
#define TEGRA210_CLK_ISP 322
#define TEGRA210_CLK_PLL_A_OUT_ADSP 323
#define TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP 324
--
2.24.1
next prev parent reply other threads:[~2020-03-10 15:20 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-10 15:19 [PATCH v5 0/8] Add EMC scaling support for Tegra210 Thierry Reding
2020-03-10 15:19 ` Thierry Reding [this message]
2020-03-10 16:19 ` [PATCH v5 1/8] clk: tegra: Add PLLP_UD and PLLMB_UD " Dmitry Osipenko
2020-03-10 17:05 ` Thierry Reding
2020-03-10 17:50 ` Dmitry Osipenko
2020-03-10 15:19 ` [PATCH v5 2/8] clk: tegra: Export functions for EMC clock scaling Thierry Reding
2020-03-10 16:13 ` Dmitry Osipenko
2020-03-10 16:16 ` Dmitry Osipenko
2020-03-10 17:08 ` Thierry Reding
2020-03-10 17:06 ` Thierry Reding
2020-03-10 15:19 ` [PATCH v5 3/8] clk: tegra: Implement Tegra210 EMC clock Thierry Reding
2020-03-10 16:26 ` Dmitry Osipenko
2020-03-10 17:10 ` Thierry Reding
2020-03-10 16:29 ` Dmitry Osipenko
2020-03-23 11:06 ` Thierry Reding
2020-03-10 16:55 ` Dmitry Osipenko
2020-03-23 11:05 ` Thierry Reding
2020-03-23 13:14 ` Dmitry Osipenko
2020-03-10 17:03 ` Dmitry Osipenko
2020-03-23 11:02 ` Thierry Reding
2020-03-10 17:44 ` Dmitry Osipenko
2020-03-23 11:00 ` Thierry Reding
2020-03-23 13:21 ` Dmitry Osipenko
2020-03-10 15:19 ` [PATCH v5 4/8] dt-bindings: memory: tegra: Add external memory controller binding for Tegra210 Thierry Reding
2020-03-10 16:35 ` Dmitry Osipenko
2020-03-10 17:12 ` Thierry Reding
2020-03-10 18:38 ` Rob Herring
2020-03-23 10:35 ` Thierry Reding
2020-03-10 15:20 ` [PATCH v5 6/8] memory: tegra: Add EMC scaling sequence code " Thierry Reding
2020-03-10 15:20 ` [PATCH v5 7/8] arm64: tegra: Add external memory controller node " Thierry Reding
2020-03-10 15:20 ` [PATCH v5 8/8] clk: tegra: Remove the old emc_mux clock " Thierry Reding
[not found] ` <20200310152003.2945170-6-thierry.reding@gmail.com>
2020-03-10 16:43 ` [PATCH v5 5/8] memory: tegra: Add EMC scaling support code " Dmitry Osipenko
2020-03-10 17:13 ` Thierry Reding
2020-03-11 0:25 ` Dmitry Osipenko
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