From: Thierry Reding <thierry.reding@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>
Cc: Jon Hunter <jonathanh@nvidia.com>,
Dmitry Osipenko <digetx@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Joseph Lo <josephl@nvidia.com>,
devicetree@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 2/8] clk: tegra: Export functions for EMC clock scaling
Date: Tue, 10 Mar 2020 16:19:57 +0100 [thread overview]
Message-ID: <20200310152003.2945170-3-thierry.reding@gmail.com> (raw)
In-Reply-To: <20200310152003.2945170-1-thierry.reding@gmail.com>
From: Joseph Lo <josephl@nvidia.com>
Export functions to allow accessing the CAR register required by EMC
clock scaling. These functions will be used to access the CAR register
as part of the scaling sequence.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v5:
- remove tegra210_clk_emc_update_setting() which is no longer needed
drivers/clk/tegra/clk-tegra210.c | 26 ++++++++++++++++++++++++++
include/linux/clk/tegra.h | 3 +++
2 files changed, 29 insertions(+)
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index f99647b4a71f..0a5be781da60 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -37,6 +37,7 @@
#define CLK_SOURCE_LA 0x1f8
#define CLK_SOURCE_SDMMC2 0x154
#define CLK_SOURCE_SDMMC4 0x164
+#define CLK_SOURCE_EMC_DLL 0x664
#define PLLC_BASE 0x80
#define PLLC_OUT 0x84
@@ -227,6 +228,10 @@
#define RST_DFLL_DVCO 0x2f4
#define DVFS_DFLL_RESET_SHIFT 0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_X_SET 0x284
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_X_CLR 0x288
+#define CLK_OUT_ENB_X_CLK_ENB_EMC_DLL BIT(14)
+
#define CLK_RST_CONTROLLER_RST_DEV_Y_SET 0x2a8
#define CLK_RST_CONTROLLER_RST_DEV_Y_CLR 0x2ac
#define CPU_SOFTRST_CTRL 0x380
@@ -555,6 +560,27 @@ void tegra210_set_sata_pll_seq_sw(bool state)
}
EXPORT_SYMBOL_GPL(tegra210_set_sata_pll_seq_sw);
+void tegra210_clk_emc_dll_enable(bool flag)
+{
+ u32 offset = flag ? CLK_RST_CONTROLLER_CLK_OUT_ENB_X_SET :
+ CLK_RST_CONTROLLER_CLK_OUT_ENB_X_CLR;
+
+ writel_relaxed(CLK_OUT_ENB_X_CLK_ENB_EMC_DLL, clk_base + offset);
+}
+EXPORT_SYMBOL_GPL(tegra210_clk_emc_dll_enable);
+
+void tegra210_clk_emc_dll_update_setting(u32 emc_dll_src_value)
+{
+ writel_relaxed(emc_dll_src_value, clk_base + CLK_SOURCE_EMC_DLL);
+}
+EXPORT_SYMBOL_GPL(tegra210_clk_emc_dll_update_setting);
+
+void tegra210_clk_emc_update_setting(u32 emc_src_value)
+{
+ writel_relaxed(emc_src_value, clk_base + CLK_SOURCE_EMC);
+}
+EXPORT_SYMBOL_GPL(tegra210_clk_emc_update_setting);
+
static void tegra210_generic_mbist_war(struct tegra210_domain_mbist_war *mbist)
{
u32 val;
diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h
index 2b1b35240074..5b0bdb413460 100644
--- a/include/linux/clk/tegra.h
+++ b/include/linux/clk/tegra.h
@@ -131,6 +131,9 @@ extern void tegra210_set_sata_pll_seq_sw(bool state);
extern void tegra210_put_utmipll_in_iddq(void);
extern void tegra210_put_utmipll_out_iddq(void);
extern int tegra210_clk_handle_mbist_war(unsigned int id);
+extern void tegra210_clk_emc_dll_enable(bool flag);
+extern void tegra210_clk_emc_dll_update_setting(u32 emc_dll_src_value);
+extern void tegra210_clk_emc_update_setting(u32 emc_src_value);
struct clk;
--
2.24.1
next prev parent reply other threads:[~2020-03-10 15:20 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-10 15:19 [PATCH v5 0/8] Add EMC scaling support for Tegra210 Thierry Reding
2020-03-10 15:19 ` [PATCH v5 1/8] clk: tegra: Add PLLP_UD and PLLMB_UD " Thierry Reding
2020-03-10 16:19 ` Dmitry Osipenko
2020-03-10 17:05 ` Thierry Reding
2020-03-10 17:50 ` Dmitry Osipenko
2020-03-10 15:19 ` Thierry Reding [this message]
2020-03-10 16:13 ` [PATCH v5 2/8] clk: tegra: Export functions for EMC clock scaling Dmitry Osipenko
2020-03-10 16:16 ` Dmitry Osipenko
2020-03-10 17:08 ` Thierry Reding
2020-03-10 17:06 ` Thierry Reding
2020-03-10 15:19 ` [PATCH v5 3/8] clk: tegra: Implement Tegra210 EMC clock Thierry Reding
2020-03-10 16:26 ` Dmitry Osipenko
2020-03-10 17:10 ` Thierry Reding
2020-03-10 16:29 ` Dmitry Osipenko
2020-03-23 11:06 ` Thierry Reding
2020-03-10 16:55 ` Dmitry Osipenko
2020-03-23 11:05 ` Thierry Reding
2020-03-23 13:14 ` Dmitry Osipenko
2020-03-10 17:03 ` Dmitry Osipenko
2020-03-23 11:02 ` Thierry Reding
2020-03-10 17:44 ` Dmitry Osipenko
2020-03-23 11:00 ` Thierry Reding
2020-03-23 13:21 ` Dmitry Osipenko
2020-03-10 15:19 ` [PATCH v5 4/8] dt-bindings: memory: tegra: Add external memory controller binding for Tegra210 Thierry Reding
2020-03-10 16:35 ` Dmitry Osipenko
2020-03-10 17:12 ` Thierry Reding
2020-03-10 18:38 ` Rob Herring
2020-03-23 10:35 ` Thierry Reding
2020-03-10 15:20 ` [PATCH v5 6/8] memory: tegra: Add EMC scaling sequence code " Thierry Reding
2020-03-10 15:20 ` [PATCH v5 7/8] arm64: tegra: Add external memory controller node " Thierry Reding
2020-03-10 15:20 ` [PATCH v5 8/8] clk: tegra: Remove the old emc_mux clock " Thierry Reding
[not found] ` <20200310152003.2945170-6-thierry.reding@gmail.com>
2020-03-10 16:43 ` [PATCH v5 5/8] memory: tegra: Add EMC scaling support code " Dmitry Osipenko
2020-03-10 17:13 ` Thierry Reding
2020-03-11 0:25 ` Dmitry Osipenko
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