* [PATCH 0/3] CLK: HSDK: CGU: updates for HSDK clock management
@ 2020-03-11 13:41 Eugeniy Paltsev
2020-03-11 13:41 ` [PATCH 1/3] CLK: HSDK: CGU: check if PLL is bypassed first Eugeniy Paltsev
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Eugeniy Paltsev @ 2020-03-11 13:41 UTC (permalink / raw)
To: linux-clk
Cc: linux-kernel, linux-snps-arc, Michael Turquette, Stephen Boyd,
Alexey Brodkin, Eugeniy Paltsev
Bunch of updates for HSDK clock generation unit (CGU) driver.
Eugeniy Paltsev (3):
CLK: HSDK: CGU: check if PLL is bypassed first
CLK: HSDK: CGU: support PLL bypassing
CLK: HSDK: CGU: add support for 148.5MHz clock
drivers/clk/clk-hsdk-pll.c | 70 +++++++++++++++++++++-----------------
1 file changed, 39 insertions(+), 31 deletions(-)
--
2.21.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/3] CLK: HSDK: CGU: check if PLL is bypassed first
2020-03-11 13:41 [PATCH 0/3] CLK: HSDK: CGU: updates for HSDK clock management Eugeniy Paltsev
@ 2020-03-11 13:41 ` Eugeniy Paltsev
2020-05-29 4:07 ` Stephen Boyd
2020-03-11 13:41 ` [PATCH 2/3] CLK: HSDK: CGU: support PLL bypassing Eugeniy Paltsev
2020-03-11 13:41 ` [PATCH 3/3] CLK: HSDK: CGU: add support for 148.5MHz clock Eugeniy Paltsev
2 siblings, 1 reply; 7+ messages in thread
From: Eugeniy Paltsev @ 2020-03-11 13:41 UTC (permalink / raw)
To: linux-clk
Cc: linux-kernel, linux-snps-arc, Michael Turquette, Stephen Boyd,
Alexey Brodkin, Eugeniy Paltsev
If PLL is bypassed the EN (enable) bit has no effect on
output clock.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
---
drivers/clk/clk-hsdk-pll.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/clk-hsdk-pll.c b/drivers/clk/clk-hsdk-pll.c
index 97d1e8c35b71..b47a559f3528 100644
--- a/drivers/clk/clk-hsdk-pll.c
+++ b/drivers/clk/clk-hsdk-pll.c
@@ -172,14 +172,14 @@ static unsigned long hsdk_pll_recalc_rate(struct clk_hw *hw,
dev_dbg(clk->dev, "current configuration: %#x\n", val);
- /* Check if PLL is disabled */
- if (val & CGU_PLL_CTRL_PD)
- return 0;
-
/* Check if PLL is bypassed */
if (val & CGU_PLL_CTRL_BYPASS)
return parent_rate;
+ /* Check if PLL is disabled */
+ if (val & CGU_PLL_CTRL_PD)
+ return 0;
+
/* input divider = reg.idiv + 1 */
idiv = 1 + ((val & CGU_PLL_CTRL_IDIV_MASK) >> CGU_PLL_CTRL_IDIV_SHIFT);
/* fb divider = 2*(reg.fbdiv + 1) */
--
2.21.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/3] CLK: HSDK: CGU: support PLL bypassing
2020-03-11 13:41 [PATCH 0/3] CLK: HSDK: CGU: updates for HSDK clock management Eugeniy Paltsev
2020-03-11 13:41 ` [PATCH 1/3] CLK: HSDK: CGU: check if PLL is bypassed first Eugeniy Paltsev
@ 2020-03-11 13:41 ` Eugeniy Paltsev
2020-05-29 4:07 ` Stephen Boyd
2020-03-11 13:41 ` [PATCH 3/3] CLK: HSDK: CGU: add support for 148.5MHz clock Eugeniy Paltsev
2 siblings, 1 reply; 7+ messages in thread
From: Eugeniy Paltsev @ 2020-03-11 13:41 UTC (permalink / raw)
To: linux-clk
Cc: linux-kernel, linux-snps-arc, Michael Turquette, Stephen Boyd,
Alexey Brodkin, Eugeniy Paltsev
Support setting PLL to bypass mode to support output frequency
equal to input one.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
---
drivers/clk/clk-hsdk-pll.c | 61 +++++++++++++++++++++-----------------
1 file changed, 34 insertions(+), 27 deletions(-)
diff --git a/drivers/clk/clk-hsdk-pll.c b/drivers/clk/clk-hsdk-pll.c
index b47a559f3528..0ea7af57a5b1 100644
--- a/drivers/clk/clk-hsdk-pll.c
+++ b/drivers/clk/clk-hsdk-pll.c
@@ -53,35 +53,37 @@ struct hsdk_pll_cfg {
u32 fbdiv;
u32 odiv;
u32 band;
+ u32 bypass;
};
static const struct hsdk_pll_cfg asdt_pll_cfg[] = {
- { 100000000, 0, 11, 3, 0 },
- { 133000000, 0, 15, 3, 0 },
- { 200000000, 1, 47, 3, 0 },
- { 233000000, 1, 27, 2, 0 },
- { 300000000, 1, 35, 2, 0 },
- { 333000000, 1, 39, 2, 0 },
- { 400000000, 1, 47, 2, 0 },
- { 500000000, 0, 14, 1, 0 },
- { 600000000, 0, 17, 1, 0 },
- { 700000000, 0, 20, 1, 0 },
- { 800000000, 0, 23, 1, 0 },
- { 900000000, 1, 26, 0, 0 },
- { 1000000000, 1, 29, 0, 0 },
- { 1100000000, 1, 32, 0, 0 },
- { 1200000000, 1, 35, 0, 0 },
- { 1300000000, 1, 38, 0, 0 },
- { 1400000000, 1, 41, 0, 0 },
- { 1500000000, 1, 44, 0, 0 },
- { 1600000000, 1, 47, 0, 0 },
+ { 100000000, 0, 11, 3, 0, 0 },
+ { 133000000, 0, 15, 3, 0, 0 },
+ { 200000000, 1, 47, 3, 0, 0 },
+ { 233000000, 1, 27, 2, 0, 0 },
+ { 300000000, 1, 35, 2, 0, 0 },
+ { 333000000, 1, 39, 2, 0, 0 },
+ { 400000000, 1, 47, 2, 0, 0 },
+ { 500000000, 0, 14, 1, 0, 0 },
+ { 600000000, 0, 17, 1, 0, 0 },
+ { 700000000, 0, 20, 1, 0, 0 },
+ { 800000000, 0, 23, 1, 0, 0 },
+ { 900000000, 1, 26, 0, 0, 0 },
+ { 1000000000, 1, 29, 0, 0, 0 },
+ { 1100000000, 1, 32, 0, 0, 0 },
+ { 1200000000, 1, 35, 0, 0, 0 },
+ { 1300000000, 1, 38, 0, 0, 0 },
+ { 1400000000, 1, 41, 0, 0, 0 },
+ { 1500000000, 1, 44, 0, 0, 0 },
+ { 1600000000, 1, 47, 0, 0, 0 },
{}
};
static const struct hsdk_pll_cfg hdmi_pll_cfg[] = {
- { 297000000, 0, 21, 2, 0 },
- { 540000000, 0, 19, 1, 0 },
- { 594000000, 0, 21, 1, 0 },
+ { 27000000, 0, 0, 0, 0, 1 },
+ { 297000000, 0, 21, 2, 0, 0 },
+ { 540000000, 0, 19, 1, 0, 0 },
+ { 594000000, 0, 21, 1, 0, 0 },
{}
};
@@ -134,11 +136,16 @@ static inline void hsdk_pll_set_cfg(struct hsdk_pll_clk *clk,
{
u32 val = 0;
- /* Powerdown and Bypass bits should be cleared */
- val |= cfg->idiv << CGU_PLL_CTRL_IDIV_SHIFT;
- val |= cfg->fbdiv << CGU_PLL_CTRL_FBDIV_SHIFT;
- val |= cfg->odiv << CGU_PLL_CTRL_ODIV_SHIFT;
- val |= cfg->band << CGU_PLL_CTRL_BAND_SHIFT;
+ if (cfg->bypass) {
+ val = hsdk_pll_read(clk, CGU_PLL_CTRL);
+ val |= CGU_PLL_CTRL_BYPASS;
+ } else {
+ /* Powerdown and Bypass bits should be cleared */
+ val |= cfg->idiv << CGU_PLL_CTRL_IDIV_SHIFT;
+ val |= cfg->fbdiv << CGU_PLL_CTRL_FBDIV_SHIFT;
+ val |= cfg->odiv << CGU_PLL_CTRL_ODIV_SHIFT;
+ val |= cfg->band << CGU_PLL_CTRL_BAND_SHIFT;
+ }
dev_dbg(clk->dev, "write configuration: %#x\n", val);
--
2.21.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 3/3] CLK: HSDK: CGU: add support for 148.5MHz clock
2020-03-11 13:41 [PATCH 0/3] CLK: HSDK: CGU: updates for HSDK clock management Eugeniy Paltsev
2020-03-11 13:41 ` [PATCH 1/3] CLK: HSDK: CGU: check if PLL is bypassed first Eugeniy Paltsev
2020-03-11 13:41 ` [PATCH 2/3] CLK: HSDK: CGU: support PLL bypassing Eugeniy Paltsev
@ 2020-03-11 13:41 ` Eugeniy Paltsev
2020-05-29 4:07 ` Stephen Boyd
2 siblings, 1 reply; 7+ messages in thread
From: Eugeniy Paltsev @ 2020-03-11 13:41 UTC (permalink / raw)
To: linux-clk
Cc: linux-kernel, linux-snps-arc, Michael Turquette, Stephen Boyd,
Alexey Brodkin, Eugeniy Paltsev
Add support for 148.5MHz clock for HDMI PLL
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
---
drivers/clk/clk-hsdk-pll.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/clk-hsdk-pll.c b/drivers/clk/clk-hsdk-pll.c
index 0ea7af57a5b1..b4f8852201cb 100644
--- a/drivers/clk/clk-hsdk-pll.c
+++ b/drivers/clk/clk-hsdk-pll.c
@@ -81,6 +81,7 @@ static const struct hsdk_pll_cfg asdt_pll_cfg[] = {
static const struct hsdk_pll_cfg hdmi_pll_cfg[] = {
{ 27000000, 0, 0, 0, 0, 1 },
+ { 148500000, 0, 21, 3, 0, 0 },
{ 297000000, 0, 21, 2, 0, 0 },
{ 540000000, 0, 19, 1, 0, 0 },
{ 594000000, 0, 21, 1, 0, 0 },
--
2.21.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 1/3] CLK: HSDK: CGU: check if PLL is bypassed first
2020-03-11 13:41 ` [PATCH 1/3] CLK: HSDK: CGU: check if PLL is bypassed first Eugeniy Paltsev
@ 2020-05-29 4:07 ` Stephen Boyd
0 siblings, 0 replies; 7+ messages in thread
From: Stephen Boyd @ 2020-05-29 4:07 UTC (permalink / raw)
To: Eugeniy Paltsev, linux-clk
Cc: linux-kernel, linux-snps-arc, Michael Turquette, Alexey Brodkin,
Eugeniy Paltsev
Quoting Eugeniy Paltsev (2020-03-11 06:41:13)
> If PLL is bypassed the EN (enable) bit has no effect on
> output clock.
>
> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/3] CLK: HSDK: CGU: support PLL bypassing
2020-03-11 13:41 ` [PATCH 2/3] CLK: HSDK: CGU: support PLL bypassing Eugeniy Paltsev
@ 2020-05-29 4:07 ` Stephen Boyd
0 siblings, 0 replies; 7+ messages in thread
From: Stephen Boyd @ 2020-05-29 4:07 UTC (permalink / raw)
To: Eugeniy Paltsev, linux-clk
Cc: linux-kernel, linux-snps-arc, Michael Turquette, Alexey Brodkin,
Eugeniy Paltsev
Quoting Eugeniy Paltsev (2020-03-11 06:41:14)
> Support setting PLL to bypass mode to support output frequency
> equal to input one.
>
> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 3/3] CLK: HSDK: CGU: add support for 148.5MHz clock
2020-03-11 13:41 ` [PATCH 3/3] CLK: HSDK: CGU: add support for 148.5MHz clock Eugeniy Paltsev
@ 2020-05-29 4:07 ` Stephen Boyd
0 siblings, 0 replies; 7+ messages in thread
From: Stephen Boyd @ 2020-05-29 4:07 UTC (permalink / raw)
To: Eugeniy Paltsev, linux-clk
Cc: linux-kernel, linux-snps-arc, Michael Turquette, Alexey Brodkin,
Eugeniy Paltsev
Quoting Eugeniy Paltsev (2020-03-11 06:41:15)
> Add support for 148.5MHz clock for HDMI PLL
>
> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2020-05-29 4:07 UTC | newest]
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2020-03-11 13:41 [PATCH 0/3] CLK: HSDK: CGU: updates for HSDK clock management Eugeniy Paltsev
2020-03-11 13:41 ` [PATCH 1/3] CLK: HSDK: CGU: check if PLL is bypassed first Eugeniy Paltsev
2020-05-29 4:07 ` Stephen Boyd
2020-03-11 13:41 ` [PATCH 2/3] CLK: HSDK: CGU: support PLL bypassing Eugeniy Paltsev
2020-05-29 4:07 ` Stephen Boyd
2020-03-11 13:41 ` [PATCH 3/3] CLK: HSDK: CGU: add support for 148.5MHz clock Eugeniy Paltsev
2020-05-29 4:07 ` Stephen Boyd
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