From: Lars Povlsen <lars.povlsen@microchip.com>
To: SoC Team <soc@kernel.org>, Arnd Bergmann <arnd@arndb.de>,
Stephen Boyd <sboyd@kernel.org>,
Linus Walleij <linus.walleij@linaro.org>
Cc: Lars Povlsen <lars.povlsen@microchip.com>,
Steen Hegelund <Steen.Hegelund@microchip.com>,
Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>,
Olof Johansson <olof@lixom.net>,
"Michael Turquette" <mturquette@baylibre.com>,
<devicetree@vger.kernel.org>, <linux-clk@vger.kernel.org>,
<linux-gpio@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
Alexandre Belloni <alexandre.belloni@bootlin.com>
Subject: [PATCH 06/14] arm64: dts: sparx5: Add basic cpu support
Date: Wed, 13 May 2020 14:55:24 +0200 [thread overview]
Message-ID: <20200513125532.24585-7-lars.povlsen@microchip.com> (raw)
In-Reply-To: <20200513125532.24585-1-lars.povlsen@microchip.com>
This adds the basic DT structure for the Microchip Sparx5 SoC, and the
reference boards, pcb125, pcb134 and pcb135. The two latter have a
NAND vs a eMMC centric variant (as a mount option),
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
---
MAINTAINERS | 1 +
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/microchip/Makefile | 4 +
arch/arm64/boot/dts/microchip/sparx5.dtsi | 135 ++++++++++++++++++
.../boot/dts/microchip/sparx5_pcb125.dts | 17 +++
.../boot/dts/microchip/sparx5_pcb134.dts | 17 +++
.../dts/microchip/sparx5_pcb134_board.dtsi | 15 ++
.../boot/dts/microchip/sparx5_pcb134_emmc.dts | 17 +++
.../boot/dts/microchip/sparx5_pcb135.dts | 17 +++
.../dts/microchip/sparx5_pcb135_board.dtsi | 15 ++
.../boot/dts/microchip/sparx5_pcb135_emmc.dts | 17 +++
.../boot/dts/microchip/sparx5_pcb_common.dtsi | 15 ++
12 files changed, 271 insertions(+)
create mode 100644 arch/arm64/boot/dts/microchip/Makefile
create mode 100644 arch/arm64/boot/dts/microchip/sparx5.dtsi
create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb134.dts
create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts
create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb135.dts
create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts
create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi
diff --git a/MAINTAINERS b/MAINTAINERS
index 1b5a18d3dbb9f..5aa28d6e39d4f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2084,6 +2084,7 @@ M: Lars Povlsen <lars.povlsen@microchip.com>
M: Steen Hegelund <Steen.Hegelund@microchip.com>
M: Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+F: arch/arm64/boot/dts/microchip/
N: sparx5
S: Supported
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index f19b762c008d8..9680a7f20c307 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -17,6 +17,7 @@ subdir-y += intel
subdir-y += lg
subdir-y += marvell
subdir-y += mediatek
+subdir-y += microchip
subdir-y += nvidia
subdir-y += qcom
subdir-y += realtek
diff --git a/arch/arm64/boot/dts/microchip/Makefile b/arch/arm64/boot/dts/microchip/Makefile
new file mode 100644
index 0000000000000..c6e0313eea0f9
--- /dev/null
+++ b/arch/arm64/boot/dts/microchip/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb125.dtb
+dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb134.dtb sparx5_pcb134_emmc.dtb
+dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb135.dtb sparx5_pcb135_emmc.dtb
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi
new file mode 100644
index 0000000000000..3136b4369f507
--- /dev/null
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "microchip,sparx5";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+ };
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x0>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x0000fff8>;
+ next-level-cache = <&L2_0>;
+ };
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x1>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x0000fff8>;
+ next-level-cache = <&L2_0>;
+ };
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts =
+ <GIC_PPI 13
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ clocks: clocks {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+ ahb_clk: ahb-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <250000000>;
+ };
+ sys_clk: sys-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <625000000>;
+ };
+ };
+
+ axi: axi@600000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+
+ gic: interrupt-controller@600300000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-controller;
+ reg = <0x6 0x00300000 0x20000>, /* GICD */
+ <0x6 0x00340000 0x1000000>; /* GICR */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ uart0: serial@600100000 {
+ compatible = "ns16550a";
+ reg = <0x6 0x00100000 0x20>;
+ clocks = <&ahb_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ status = "disabled";
+ };
+
+ uart1: serial@600102000 {
+ compatible = "ns16550a";
+ reg = <0x6 0x00102000 0x20>;
+ clocks = <&ahb_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+
+ status = "disabled";
+ };
+
+ timer1: timer@600105000 {
+ compatible = "snps,dw-apb-timer";
+ reg = <0x6 0x00105000 0x1000>;
+ clocks = <&ahb_clk>;
+ clock-names = "timer";
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ };
+};
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
new file mode 100644
index 0000000000000..d7f985f7ee020
--- /dev/null
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ */
+
+/dts-v1/;
+#include "sparx5_pcb_common.dtsi"
+
+/ {
+ model = "Sparx5 PCB125 Reference Board";
+ compatible = "microchip,sparx5-pcb125", "microchip,sparx5";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x00000000 0x10000000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts
new file mode 100644
index 0000000000000..feee4e99ff57c
--- /dev/null
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ */
+
+/dts-v1/;
+#include "sparx5_pcb134_board.dtsi"
+
+/ {
+ model = "Sparx5 PCB134 Reference Board (NAND)";
+ compatible = "microchip,sparx5-pcb134", "microchip,sparx5";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x00000000 0x10000000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
new file mode 100644
index 0000000000000..9b2aec400101b
--- /dev/null
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ */
+
+/dts-v1/;
+#include "sparx5_pcb_common.dtsi"
+
+/{
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
+ priority = <200>;
+ };
+};
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts
new file mode 100644
index 0000000000000..10081a66961bb
--- /dev/null
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ */
+
+/dts-v1/;
+#include "sparx5_pcb134_board.dtsi"
+
+/ {
+ model = "Sparx5 PCB134 Reference Board (eMMC enabled)";
+ compatible = "microchip,sparx5-pcb134", "microchip,sparx5";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x00000000 0x10000000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts
new file mode 100644
index 0000000000000..20e409a9be196
--- /dev/null
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ */
+
+/dts-v1/;
+#include "sparx5_pcb135_board.dtsi"
+
+/ {
+ model = "Sparx5 PCB135 Reference Board (NAND)";
+ compatible = "microchip,sparx5-pcb135", "microchip,sparx5";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x00000000 0x10000000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
new file mode 100644
index 0000000000000..9b2aec400101b
--- /dev/null
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ */
+
+/dts-v1/;
+#include "sparx5_pcb_common.dtsi"
+
+/{
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
+ priority = <200>;
+ };
+};
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts
new file mode 100644
index 0000000000000..741f0e12260e5
--- /dev/null
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ */
+
+/dts-v1/;
+#include "sparx5_pcb135_board.dtsi"
+
+/ {
+ model = "Sparx5 PCB135 Reference Board (eMMC enabled)";
+ compatible = "microchip,sparx5-pcb135", "microchip,sparx5";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x00000000 0x10000000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi
new file mode 100644
index 0000000000000..1f99d0db1284f
--- /dev/null
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ */
+
+/dts-v1/;
+#include "sparx5.dtsi"
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
--
2.26.2
next prev parent reply other threads:[~2020-05-13 12:57 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-13 12:55 [PATCH 00/14] Adding support for Microchip Sparx5 SoC Lars Povlsen
2020-05-13 12:55 ` [PATCH 01/14] pinctrl: ocelot: Should register GPIO's even if not irq controller Lars Povlsen
2020-05-18 7:29 ` Linus Walleij
2020-05-13 12:55 ` [PATCH 02/14] pinctrl: ocelot: Remove instance number from pin functions Lars Povlsen
2020-05-18 7:31 ` Linus Walleij
2020-05-13 12:55 ` [PATCH 03/14] pinctrl: ocelot: Fix GPIO interrupt decoding on Jaguar2 Lars Povlsen
2020-05-18 7:31 ` Linus Walleij
2020-05-13 12:55 ` [PATCH 04/14] arm64: sparx5: Add support for Microchip 2xA53 SoC Lars Povlsen
2020-05-13 12:55 ` [PATCH 05/14] dt-bindings: arm: sparx5: Add documentation for Microchip Sparx5 SoC Lars Povlsen
2020-05-28 2:11 ` Rob Herring
2020-06-02 9:10 ` Lars Povlsen
2020-05-13 12:55 ` Lars Povlsen [this message]
2020-05-13 15:39 ` [PATCH 06/14] arm64: dts: sparx5: Add basic cpu support Marc Zyngier
2020-05-15 15:09 ` Lars Povlsen
2020-05-15 15:30 ` Robin Murphy
2020-05-18 7:43 ` Lars Povlsen
2020-05-13 12:55 ` [PATCH 07/14] dt-bindings: pinctrl: ocelot: Add Sparx5 SoC support Lars Povlsen
2020-05-18 7:33 ` Linus Walleij
2020-05-13 12:55 ` [PATCH 08/14] arm64: dts: sparx5: Add pinctrl support Lars Povlsen
2020-05-13 12:55 ` [PATCH 09/14] pinctrl: ocelot: Add Sparx5 SoC support Lars Povlsen
2020-05-14 18:09 ` kbuild test robot
2020-05-15 15:52 ` Lars Povlsen
2020-05-13 12:55 ` [PATCH 10/14] dt-bindings: clock: sparx5: Add Sparx5 SoC DPLL clock Lars Povlsen
2020-05-28 2:18 ` Rob Herring
2020-06-02 8:39 ` Lars Povlsen
[not found] ` <159054759981.88029.2630901114208720574@swboyd.mtv.corp.google.com>
2020-05-29 14:04 ` Lars Povlsen
2020-05-13 12:55 ` [PATCH 11/14] dt-bindings: clock: sparx5: Add bindings include file Lars Povlsen
2020-05-13 12:55 ` [PATCH 12/14] clk: sparx5: Add Sparx5 SoC DPLL clock driver Lars Povlsen
[not found] ` <159054818459.88029.10644772284176356883@swboyd.mtv.corp.google.com>
2020-05-27 14:29 ` Lars Povlsen
2020-05-13 12:55 ` [PATCH 13/14] arm64: dts: sparx5: Add Sparx5 SoC DPLL clock Lars Povlsen
2020-05-13 12:55 ` [PATCH 14/14] arm64: dts: sparx5: Add i2c devices, i2c muxes Lars Povlsen
2020-05-21 10:16 ` [PATCH 00/14] Adding support for Microchip Sparx5 SoC Arnd Bergmann
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