From: Rob Herring <robh@kernel.org>
To: Lars Povlsen <lars.povlsen@microchip.com>
Cc: SoC Team <soc@kernel.org>, Arnd Bergmann <arnd@arndb.de>,
Stephen Boyd <sboyd@kernel.org>,
Linus Walleij <linus.walleij@linaro.org>,
Steen Hegelund <Steen.Hegelund@microchip.com>,
Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>,
Olof Johansson <olof@lixom.net>,
Michael Turquette <mturquette@baylibre.com>,
devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Alexandre Belloni <alexandre.belloni@bootlin.com>
Subject: Re: [PATCH 05/14] dt-bindings: arm: sparx5: Add documentation for Microchip Sparx5 SoC
Date: Wed, 27 May 2020 20:11:37 -0600 [thread overview]
Message-ID: <20200528021137.GA3214411@bogus> (raw)
In-Reply-To: <20200513125532.24585-6-lars.povlsen@microchip.com>
On Wed, May 13, 2020 at 02:55:23PM +0200, Lars Povlsen wrote:
> This adds the main Sparx5 SoC DT documentation file, with information
> abut the supported board types.
>
> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
> ---
> .../bindings/arm/microchip,sparx5.yaml | 87 +++++++++++++++++++
> 1 file changed, 87 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/microchip,sparx5.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/microchip,sparx5.yaml b/Documentation/devicetree/bindings/arm/microchip,sparx5.yaml
> new file mode 100644
> index 0000000000000..83b36d1217988
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/microchip,sparx5.yaml
> @@ -0,0 +1,87 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/microchip,sparx5.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Microchip Sparx5 Boards Device Tree Bindings
> +
> +maintainers:
> + - Lars Povlsen <lars.povlsen@microchip.com>
> +
> +description: |+
> + The Microchip Sparx5 SoC is a ARMv8-based used in a family of
> + gigabit TSN-capable gigabit switches.
> +
> + The SparX-5 Ethernet switch family provides a rich set of switching
> + features such as advanced TCAM-based VLAN and QoS processing
> + enabling delivery of differentiated services, and security through
> + TCAM-based frame processing using versatile content aware processor
> + (VCAP)
> +
> +properties:
> + $nodename:
> + const: '/'
> + compatible:
> + oneOf:
> + - description: The Sparx5 pcb125 board is a modular board,
> + which has both spi-nor and eMMC storage. The modular design
> + allows for connection of different network ports.
> + items:
> + - const: microchip,sparx5-pcb125
> + - const: microchip,sparx5
> +
> + - description: The Sparx5 pcb134 is a pizzabox form factor
> + gigabit switch with 20 SFP ports. It features spi-nor and
> + either spi-nand or eMMC storage (mount option).
> + items:
> + - const: microchip,sparx5-pcb134
> + - const: microchip,sparx5
> +
> + - description: The Sparx5 pcb135 is a pizzabox form factor
> + gigabit switch with 48+4 Cu ports. It features spi-nor and
> + either spi-nand or eMMC storage (mount option).
> + items:
> + - const: microchip,sparx5-pcb135
> + - const: microchip,sparx5
> +
> + axi@600000000:
> + type: object
> + description: the root node in the Sparx5 platforms must contain
> + an axi bus child node. They are always at physical address
> + 0x600000000 in all the Sparx5 variants.
> + properties:
> + compatible:
> + items:
> + - const: simple-bus
> + reg:
> + maxItems: 1
simple-bus doesn't have 'reg'. If there's bus registers, then it's not
simple.
> +
> + required:
> + - compatible
> + - reg
> +
> +patternProperties:
> + "^syscon@[0-9a-f]+$":
This should be under a bus node.
> + description: All Sparx5 boards must provide a system controller,
> + typically under the axi bus node. It contain reset registers and
> + other system control.
> + type: object
> + properties:
> + compatible:
> + items:
> + - const: microchip,sparx5-cpu-syscon
> + - const: syscon
This probably should be in its own document. If really this simple,
there's already syscon.yaml you can add to.
> + reg:
> + maxItems: 1
> +
> + required:
> + - compatible
> + - reg
> +
> +required:
> + - compatible
> + - axi@600000000
> + - syscon@600000000
> +
> +...
> --
> 2.26.2
next prev parent reply other threads:[~2020-05-28 2:11 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-13 12:55 [PATCH 00/14] Adding support for Microchip Sparx5 SoC Lars Povlsen
2020-05-13 12:55 ` [PATCH 01/14] pinctrl: ocelot: Should register GPIO's even if not irq controller Lars Povlsen
2020-05-18 7:29 ` Linus Walleij
2020-05-13 12:55 ` [PATCH 02/14] pinctrl: ocelot: Remove instance number from pin functions Lars Povlsen
2020-05-18 7:31 ` Linus Walleij
2020-05-13 12:55 ` [PATCH 03/14] pinctrl: ocelot: Fix GPIO interrupt decoding on Jaguar2 Lars Povlsen
2020-05-18 7:31 ` Linus Walleij
2020-05-13 12:55 ` [PATCH 04/14] arm64: sparx5: Add support for Microchip 2xA53 SoC Lars Povlsen
2020-05-13 12:55 ` [PATCH 05/14] dt-bindings: arm: sparx5: Add documentation for Microchip Sparx5 SoC Lars Povlsen
2020-05-28 2:11 ` Rob Herring [this message]
2020-06-02 9:10 ` Lars Povlsen
2020-05-13 12:55 ` [PATCH 06/14] arm64: dts: sparx5: Add basic cpu support Lars Povlsen
2020-05-13 15:39 ` Marc Zyngier
2020-05-15 15:09 ` Lars Povlsen
2020-05-15 15:30 ` Robin Murphy
2020-05-18 7:43 ` Lars Povlsen
2020-05-13 12:55 ` [PATCH 07/14] dt-bindings: pinctrl: ocelot: Add Sparx5 SoC support Lars Povlsen
2020-05-18 7:33 ` Linus Walleij
2020-05-13 12:55 ` [PATCH 08/14] arm64: dts: sparx5: Add pinctrl support Lars Povlsen
2020-05-13 12:55 ` [PATCH 09/14] pinctrl: ocelot: Add Sparx5 SoC support Lars Povlsen
2020-05-14 18:09 ` kbuild test robot
2020-05-15 15:52 ` Lars Povlsen
2020-05-13 12:55 ` [PATCH 10/14] dt-bindings: clock: sparx5: Add Sparx5 SoC DPLL clock Lars Povlsen
2020-05-28 2:18 ` Rob Herring
2020-06-02 8:39 ` Lars Povlsen
[not found] ` <159054759981.88029.2630901114208720574@swboyd.mtv.corp.google.com>
2020-05-29 14:04 ` Lars Povlsen
2020-05-13 12:55 ` [PATCH 11/14] dt-bindings: clock: sparx5: Add bindings include file Lars Povlsen
2020-05-13 12:55 ` [PATCH 12/14] clk: sparx5: Add Sparx5 SoC DPLL clock driver Lars Povlsen
[not found] ` <159054818459.88029.10644772284176356883@swboyd.mtv.corp.google.com>
2020-05-27 14:29 ` Lars Povlsen
2020-05-13 12:55 ` [PATCH 13/14] arm64: dts: sparx5: Add Sparx5 SoC DPLL clock Lars Povlsen
2020-05-13 12:55 ` [PATCH 14/14] arm64: dts: sparx5: Add i2c devices, i2c muxes Lars Povlsen
2020-05-21 10:16 ` [PATCH 00/14] Adding support for Microchip Sparx5 SoC Arnd Bergmann
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200528021137.GA3214411@bogus \
--to=robh@kernel.org \
--cc=Steen.Hegelund@microchip.com \
--cc=UNGLinuxDriver@microchip.com \
--cc=alexandre.belloni@bootlin.com \
--cc=arnd@arndb.de \
--cc=devicetree@vger.kernel.org \
--cc=lars.povlsen@microchip.com \
--cc=linus.walleij@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-gpio@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mturquette@baylibre.com \
--cc=olof@lixom.net \
--cc=sboyd@kernel.org \
--cc=soc@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).