* [PATCH 1/2] clk: sprd: mark the local clock symbols static
@ 2020-05-19 3:00 Chunyan Zhang
2020-05-19 3:00 ` [PATCH 2/2] clk: sprd: return correct type of value for _sprd_pll_recalc_rate Chunyan Zhang
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Chunyan Zhang @ 2020-05-19 3:00 UTC (permalink / raw)
To: Stephen Boyd, Michael Turquette
Cc: linux-clk, linux-kernel, Orson Zhai, Baolin Wang, Chunyan Zhang,
Chunyan Zhang
From: Chunyan Zhang <chunyan.zhang@unisoc.com>
There's a few pll gate clocks which were not marked with static, and
those clock are used only in the current file, so add static key word
for them.
Fixes: 0e4b8a2349f3 ("clk: sprd: add clocks support for SC9863A")
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
---
drivers/clk/sprd/sc9863a-clk.c | 32 ++++++++++++++++----------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/clk/sprd/sc9863a-clk.c b/drivers/clk/sprd/sc9863a-clk.c
index 9568ec956ee4..ad2e0f9f8563 100644
--- a/drivers/clk/sprd/sc9863a-clk.c
+++ b/drivers/clk/sprd/sc9863a-clk.c
@@ -23,22 +23,22 @@
#include "pll.h"
/* mpll*_gate clocks control cpu cores, they were enabled by default */
-SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll0_gate, "mpll0-gate", "ext-26m", 0x94,
- 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240);
-SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll0_gate, "dpll0-gate", "ext-26m", 0x98,
- 0x1000, BIT(0), 0, 0, 240);
-SPRD_PLL_SC_GATE_CLK_FW_NAME(lpll_gate, "lpll-gate", "ext-26m", 0x9c,
- 0x1000, BIT(0), 0, 0, 240);
-SPRD_PLL_SC_GATE_CLK_FW_NAME(gpll_gate, "gpll-gate", "ext-26m", 0xa8,
- 0x1000, BIT(0), 0, 0, 240);
-SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll1_gate, "dpll1-gate", "ext-26m", 0x1dc,
- 0x1000, BIT(0), 0, 0, 240);
-SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll1_gate, "mpll1-gate", "ext-26m", 0x1e0,
- 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240);
-SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll2_gate, "mpll2-gate", "ext-26m", 0x1e4,
- 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240);
-SPRD_PLL_SC_GATE_CLK_FW_NAME(isppll_gate, "isppll-gate", "ext-26m", 0x1e8,
- 0x1000, BIT(0), 0, 0, 240);
+static SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll0_gate, "mpll0-gate", "ext-26m", 0x94,
+ 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240);
+static SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll0_gate, "dpll0-gate", "ext-26m", 0x98,
+ 0x1000, BIT(0), 0, 0, 240);
+static SPRD_PLL_SC_GATE_CLK_FW_NAME(lpll_gate, "lpll-gate", "ext-26m", 0x9c,
+ 0x1000, BIT(0), 0, 0, 240);
+static SPRD_PLL_SC_GATE_CLK_FW_NAME(gpll_gate, "gpll-gate", "ext-26m", 0xa8,
+ 0x1000, BIT(0), 0, 0, 240);
+static SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll1_gate, "dpll1-gate", "ext-26m", 0x1dc,
+ 0x1000, BIT(0), 0, 0, 240);
+static SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll1_gate, "mpll1-gate", "ext-26m", 0x1e0,
+ 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240);
+static SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll2_gate, "mpll2-gate", "ext-26m", 0x1e4,
+ 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240);
+static SPRD_PLL_SC_GATE_CLK_FW_NAME(isppll_gate, "isppll-gate", "ext-26m",
+ 0x1e8, 0x1000, BIT(0), 0, 0, 240);
static struct sprd_clk_common *sc9863a_pmu_gate_clks[] = {
/* address base is 0x402b0000 */
--
2.20.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 2/2] clk: sprd: return correct type of value for _sprd_pll_recalc_rate
2020-05-19 3:00 [PATCH 1/2] clk: sprd: mark the local clock symbols static Chunyan Zhang
@ 2020-05-19 3:00 ` Chunyan Zhang
2020-05-19 13:13 ` Baolin Wang
2020-05-27 3:14 ` Stephen Boyd
2020-05-19 13:12 ` [PATCH 1/2] clk: sprd: mark the local clock symbols static Baolin Wang
2020-05-27 3:14 ` Stephen Boyd
2 siblings, 2 replies; 6+ messages in thread
From: Chunyan Zhang @ 2020-05-19 3:00 UTC (permalink / raw)
To: Stephen Boyd, Michael Turquette
Cc: linux-clk, linux-kernel, Orson Zhai, Baolin Wang, Chunyan Zhang,
Chunyan Zhang
From: Chunyan Zhang <chunyan.zhang@unisoc.com>
The function _sprd_pll_recalc_rate() defines return value to unsigned
long, but it would return a negative value when malloc fail, changing
to return its parent_rate makes more sense, since if the callback
.recalc_rate() is not set, the framework returns the parent_rate as
well.
Fixes: 3e37b005580b ("clk: sprd: add adjustable pll support")
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
---
drivers/clk/sprd/pll.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sprd/pll.c b/drivers/clk/sprd/pll.c
index 15791484388f..13a322b2535a 100644
--- a/drivers/clk/sprd/pll.c
+++ b/drivers/clk/sprd/pll.c
@@ -106,7 +106,7 @@ static unsigned long _sprd_pll_recalc_rate(const struct sprd_pll *pll,
cfg = kcalloc(regs_num, sizeof(*cfg), GFP_KERNEL);
if (!cfg)
- return -ENOMEM;
+ return parent_rate;
for (i = 0; i < regs_num; i++)
cfg[i] = sprd_pll_read(pll, i);
--
2.20.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH 2/2] clk: sprd: return correct type of value for _sprd_pll_recalc_rate
2020-05-19 3:00 ` [PATCH 2/2] clk: sprd: return correct type of value for _sprd_pll_recalc_rate Chunyan Zhang
@ 2020-05-19 13:13 ` Baolin Wang
2020-05-27 3:14 ` Stephen Boyd
1 sibling, 0 replies; 6+ messages in thread
From: Baolin Wang @ 2020-05-19 13:13 UTC (permalink / raw)
To: Chunyan Zhang
Cc: Stephen Boyd, Michael Turquette, linux-clk, LKML, Orson Zhai,
Chunyan Zhang
On Tue, May 19, 2020 at 11:00 AM Chunyan Zhang <zhang.lyra@gmail.com> wrote:
>
> From: Chunyan Zhang <chunyan.zhang@unisoc.com>
>
> The function _sprd_pll_recalc_rate() defines return value to unsigned
> long, but it would return a negative value when malloc fail, changing
> to return its parent_rate makes more sense, since if the callback
> .recalc_rate() is not set, the framework returns the parent_rate as
> well.
>
> Fixes: 3e37b005580b ("clk: sprd: add adjustable pll support")
> Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
Looks good to me.
Reviewed-by: Baolin Wang <baolin.wang7@gmail.com>
--
Baolin Wang
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH 2/2] clk: sprd: return correct type of value for _sprd_pll_recalc_rate
2020-05-19 3:00 ` [PATCH 2/2] clk: sprd: return correct type of value for _sprd_pll_recalc_rate Chunyan Zhang
2020-05-19 13:13 ` Baolin Wang
@ 2020-05-27 3:14 ` Stephen Boyd
1 sibling, 0 replies; 6+ messages in thread
From: Stephen Boyd @ 2020-05-27 3:14 UTC (permalink / raw)
To: Chunyan Zhang, Michael Turquette
Cc: linux-clk, linux-kernel, Orson Zhai, Baolin Wang, Chunyan Zhang,
Chunyan Zhang
Quoting Chunyan Zhang (2020-05-18 20:00:36)
> From: Chunyan Zhang <chunyan.zhang@unisoc.com>
>
> The function _sprd_pll_recalc_rate() defines return value to unsigned
> long, but it would return a negative value when malloc fail, changing
> to return its parent_rate makes more sense, since if the callback
> .recalc_rate() is not set, the framework returns the parent_rate as
> well.
>
> Fixes: 3e37b005580b ("clk: sprd: add adjustable pll support")
> Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] clk: sprd: mark the local clock symbols static
2020-05-19 3:00 [PATCH 1/2] clk: sprd: mark the local clock symbols static Chunyan Zhang
2020-05-19 3:00 ` [PATCH 2/2] clk: sprd: return correct type of value for _sprd_pll_recalc_rate Chunyan Zhang
@ 2020-05-19 13:12 ` Baolin Wang
2020-05-27 3:14 ` Stephen Boyd
2 siblings, 0 replies; 6+ messages in thread
From: Baolin Wang @ 2020-05-19 13:12 UTC (permalink / raw)
To: Chunyan Zhang
Cc: Stephen Boyd, Michael Turquette, linux-clk, LKML, Orson Zhai,
Chunyan Zhang
On Tue, May 19, 2020 at 11:00 AM Chunyan Zhang <zhang.lyra@gmail.com> wrote:
>
> From: Chunyan Zhang <chunyan.zhang@unisoc.com>
>
> There's a few pll gate clocks which were not marked with static, and
> those clock are used only in the current file, so add static key word
> for them.
>
> Fixes: 0e4b8a2349f3 ("clk: sprd: add clocks support for SC9863A")
> Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
Reviewed-by: Baolin Wang <baolin.wang7@gmail.com>
> ---
> drivers/clk/sprd/sc9863a-clk.c | 32 ++++++++++++++++----------------
> 1 file changed, 16 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/clk/sprd/sc9863a-clk.c b/drivers/clk/sprd/sc9863a-clk.c
> index 9568ec956ee4..ad2e0f9f8563 100644
> --- a/drivers/clk/sprd/sc9863a-clk.c
> +++ b/drivers/clk/sprd/sc9863a-clk.c
> @@ -23,22 +23,22 @@
> #include "pll.h"
>
> /* mpll*_gate clocks control cpu cores, they were enabled by default */
> -SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll0_gate, "mpll0-gate", "ext-26m", 0x94,
> - 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240);
> -SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll0_gate, "dpll0-gate", "ext-26m", 0x98,
> - 0x1000, BIT(0), 0, 0, 240);
> -SPRD_PLL_SC_GATE_CLK_FW_NAME(lpll_gate, "lpll-gate", "ext-26m", 0x9c,
> - 0x1000, BIT(0), 0, 0, 240);
> -SPRD_PLL_SC_GATE_CLK_FW_NAME(gpll_gate, "gpll-gate", "ext-26m", 0xa8,
> - 0x1000, BIT(0), 0, 0, 240);
> -SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll1_gate, "dpll1-gate", "ext-26m", 0x1dc,
> - 0x1000, BIT(0), 0, 0, 240);
> -SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll1_gate, "mpll1-gate", "ext-26m", 0x1e0,
> - 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240);
> -SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll2_gate, "mpll2-gate", "ext-26m", 0x1e4,
> - 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240);
> -SPRD_PLL_SC_GATE_CLK_FW_NAME(isppll_gate, "isppll-gate", "ext-26m", 0x1e8,
> - 0x1000, BIT(0), 0, 0, 240);
> +static SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll0_gate, "mpll0-gate", "ext-26m", 0x94,
> + 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240);
> +static SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll0_gate, "dpll0-gate", "ext-26m", 0x98,
> + 0x1000, BIT(0), 0, 0, 240);
> +static SPRD_PLL_SC_GATE_CLK_FW_NAME(lpll_gate, "lpll-gate", "ext-26m", 0x9c,
> + 0x1000, BIT(0), 0, 0, 240);
> +static SPRD_PLL_SC_GATE_CLK_FW_NAME(gpll_gate, "gpll-gate", "ext-26m", 0xa8,
> + 0x1000, BIT(0), 0, 0, 240);
> +static SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll1_gate, "dpll1-gate", "ext-26m", 0x1dc,
> + 0x1000, BIT(0), 0, 0, 240);
> +static SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll1_gate, "mpll1-gate", "ext-26m", 0x1e0,
> + 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240);
> +static SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll2_gate, "mpll2-gate", "ext-26m", 0x1e4,
> + 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240);
> +static SPRD_PLL_SC_GATE_CLK_FW_NAME(isppll_gate, "isppll-gate", "ext-26m",
> + 0x1e8, 0x1000, BIT(0), 0, 0, 240);
>
> static struct sprd_clk_common *sc9863a_pmu_gate_clks[] = {
> /* address base is 0x402b0000 */
> --
> 2.20.1
>
--
Baolin Wang
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH 1/2] clk: sprd: mark the local clock symbols static
2020-05-19 3:00 [PATCH 1/2] clk: sprd: mark the local clock symbols static Chunyan Zhang
2020-05-19 3:00 ` [PATCH 2/2] clk: sprd: return correct type of value for _sprd_pll_recalc_rate Chunyan Zhang
2020-05-19 13:12 ` [PATCH 1/2] clk: sprd: mark the local clock symbols static Baolin Wang
@ 2020-05-27 3:14 ` Stephen Boyd
2 siblings, 0 replies; 6+ messages in thread
From: Stephen Boyd @ 2020-05-27 3:14 UTC (permalink / raw)
To: Chunyan Zhang, Michael Turquette
Cc: linux-clk, linux-kernel, Orson Zhai, Baolin Wang, Chunyan Zhang,
Chunyan Zhang
Quoting Chunyan Zhang (2020-05-18 20:00:35)
> From: Chunyan Zhang <chunyan.zhang@unisoc.com>
>
> There's a few pll gate clocks which were not marked with static, and
> those clock are used only in the current file, so add static key word
> for them.
>
> Fixes: 0e4b8a2349f3 ("clk: sprd: add clocks support for SC9863A")
> Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-05-27 3:14 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2020-05-19 3:00 [PATCH 1/2] clk: sprd: mark the local clock symbols static Chunyan Zhang
2020-05-19 3:00 ` [PATCH 2/2] clk: sprd: return correct type of value for _sprd_pll_recalc_rate Chunyan Zhang
2020-05-19 13:13 ` Baolin Wang
2020-05-27 3:14 ` Stephen Boyd
2020-05-19 13:12 ` [PATCH 1/2] clk: sprd: mark the local clock symbols static Baolin Wang
2020-05-27 3:14 ` Stephen Boyd
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