[PATCH 0/5] Add clock drivers for SM8350

[PATCH 0/5] Add clock drivers for SM8350

[Vinod Koul]

This add rpmhcc and gcc clock controller drivers for the controllers found
in SM8350 SoC

Vinod Koul (3):
  dt-bindings: clock: Add RPMHCC bindings for SM8350
  clk: qcom: rpmh: add support for SM8350 rpmh clocks
  dt-bindings: clock: Add SM8350 GCC clock bindings

Vivek Aknurwar (2):
  clk: qcom: clk-alpha-pll: Add support for Lucid 5LPE PLL
  clk: qcom: gcc: Add clock driver for SM8350

 .../bindings/clock/qcom,gcc-sm8350.yaml       |   68 +
 .../bindings/clock/qcom,rpmhcc.yaml           |    1 +
 drivers/clk/qcom/Kconfig                      |    9 +
 drivers/clk/qcom/Makefile                     |    1 +
 drivers/clk/qcom/clk-alpha-pll.c              |  223 +
 drivers/clk/qcom/clk-alpha-pll.h              |    4 +
 drivers/clk/qcom/clk-rpmh.c                   |   34 +
 drivers/clk/qcom/gcc-sm8350.c                 | 3959 +++++++++++++++++
 include/dt-bindings/clock/qcom,gcc-sm8350.h   |  261 ++
 include/dt-bindings/clock/qcom,rpmh.h         |    8 +
 10 files changed, 4568 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml
 create mode 100644 drivers/clk/qcom/gcc-sm8350.c
 create mode 100644 include/dt-bindings/clock/qcom,gcc-sm8350.h

-- 
2.26.2

[PATCH 1/5] dt-bindings: clock: Add RPMHCC bindings for SM8350

[Vinod Koul]

Add bindings and update documentation for clock rpmh driver on SM8350.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
 Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
index a46a3a799a70..3037eb98c810 100644
--- a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
@@ -21,6 +21,7 @@ properties:
       - qcom,sdm845-rpmh-clk
       - qcom,sm8150-rpmh-clk
       - qcom,sm8250-rpmh-clk
+      - qcom,sm8350-rpmh-clk
 
   clocks:
     maxItems: 1
-- 
2.26.2

[PATCH 2/5] clk: qcom: rpmh: add support for SM8350 rpmh clocks

[Vinod Koul]

This adds the RPMH clocks present in SM8350 SoC

Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
 drivers/clk/qcom/clk-rpmh.c           | 34 +++++++++++++++++++++++++++
 include/dt-bindings/clock/qcom,rpmh.h |  8 +++++++
 2 files changed, 42 insertions(+)

diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
index e2c669b08aff..64cab4403a17 100644
--- a/drivers/clk/qcom/clk-rpmh.c
+++ b/drivers/clk/qcom/clk-rpmh.c
@@ -432,6 +432,39 @@ static const struct clk_rpmh_desc clk_rpmh_sm8250 = {
 	.num_clks = ARRAY_SIZE(sm8250_rpmh_clocks),
 };
 
+DEFINE_CLK_RPMH_VRM(sm8350, div_clk1, div_clk1_ao, "divclka1", 2);
+DEFINE_CLK_RPMH_VRM(sm8350, rf_clk4, rf_clk4_ao, "rfclka4", 1);
+DEFINE_CLK_RPMH_VRM(sm8350, rf_clk5, rf_clk5_ao, "rfclka5", 1);
+DEFINE_CLK_RPMH_BCM(sm8350, pka, "PKA0");
+DEFINE_CLK_RPMH_BCM(sm8350, hwkm, "HK0");
+
+static struct clk_hw *sm8350_rpmh_clocks[] = {
+	[RPMH_CXO_CLK]		= &sdm845_bi_tcxo.hw,
+	[RPMH_CXO_CLK_A]	= &sdm845_bi_tcxo_ao.hw,
+	[RPMH_DIV_CLK1]		= &sm8350_div_clk1.hw,
+	[RPMH_DIV_CLK1_A]	= &sm8350_div_clk1_ao.hw,
+	[RPMH_LN_BB_CLK1]	= &sm8250_ln_bb_clk1.hw,
+	[RPMH_LN_BB_CLK1_A]	= &sm8250_ln_bb_clk1_ao.hw,
+	[RPMH_LN_BB_CLK2]	= &sdm845_ln_bb_clk2.hw,
+	[RPMH_LN_BB_CLK2_A]	= &sdm845_ln_bb_clk2_ao.hw,
+	[RPMH_RF_CLK1]		= &sdm845_rf_clk1.hw,
+	[RPMH_RF_CLK1_A]	= &sdm845_rf_clk1_ao.hw,
+	[RPMH_RF_CLK3]		= &sdm845_rf_clk3.hw,
+	[RPMH_RF_CLK3_A]	= &sdm845_rf_clk3_ao.hw,
+	[RPMH_RF_CLK4]		= &sm8350_rf_clk4.hw,
+	[RPMH_RF_CLK4_A]	= &sm8350_rf_clk4_ao.hw,
+	[RPMH_RF_CLK5]		= &sm8350_rf_clk5.hw,
+	[RPMH_RF_CLK5_A]	= &sm8350_rf_clk5_ao.hw,
+	[RPMH_IPA_CLK]		= &sdm845_ipa.hw,
+	[RPMH_PKA_CLK]		= &sm8350_pka.hw,
+	[RPMH_HWKM_CLK]		= &sm8350_hwkm.hw,
+};
+
+static const struct clk_rpmh_desc clk_rpmh_sm8350 = {
+	.clks = sm8350_rpmh_clocks,
+	.num_clks = ARRAY_SIZE(sm8350_rpmh_clocks),
+};
+
 static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
 					 void *data)
 {
@@ -519,6 +552,7 @@ static const struct of_device_id clk_rpmh_match_table[] = {
 	{ .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845},
 	{ .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150},
 	{ .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250},
+	{ .compatible = "qcom,sm8350-rpmh-clk", .data = &clk_rpmh_sm8350},
 	{ }
 };
 MODULE_DEVICE_TABLE(of, clk_rpmh_match_table);
diff --git a/include/dt-bindings/clock/qcom,rpmh.h b/include/dt-bindings/clock/qcom,rpmh.h
index 2e6c54e65455..6dbe5d398bf0 100644
--- a/include/dt-bindings/clock/qcom,rpmh.h
+++ b/include/dt-bindings/clock/qcom,rpmh.h
@@ -21,5 +21,13 @@
 #define RPMH_IPA_CLK				12
 #define RPMH_LN_BB_CLK1				13
 #define RPMH_LN_BB_CLK1_A			14
+#define RPMH_DIV_CLK1				15
+#define RPMH_DIV_CLK1_A				16
+#define RPMH_RF_CLK4				17
+#define RPMH_RF_CLK4_A				18
+#define RPMH_RF_CLK5				19
+#define RPMH_RF_CLK5_A				20
+#define RPMH_PKA_CLK				21
+#define RPMH_HWKM_CLK				22
 
 #endif
-- 
2.26.2

[PATCH 3/5] dt-bindings: clock: Add SM8350 GCC clock bindings

[Vinod Koul]

Add device tree bindings for global clock controller on SM8350 SoCs.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
 .../bindings/clock/qcom,gcc-sm8350.yaml       |  68 +++++
 include/dt-bindings/clock/qcom,gcc-sm8350.h   | 261 ++++++++++++++++++
 2 files changed, 329 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml
 create mode 100644 include/dt-bindings/clock/qcom,gcc-sm8350.h

diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml
new file mode 100644
index 000000000000..2b0939f81162
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8350.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller Binding for SM8350
+
+maintainers:
+  - Vinod Koul <vkoul@kernel.org>
+
+description: |
+  Qualcomm global clock control module which supports the clocks, resets and
+  power domains on SM8350.
+
+  See also:
+  - dt-bindings/clock/qcom,gcc-sm8350.h
+
+properties:
+  compatible:
+    const: qcom,gcc-sm8350
+
+  clocks:
+    items:
+      - description: Board XO source
+      - description: Sleep clock source
+
+  clock-names:
+    items:
+      - const: bi_tcxo
+      - const: sleep_clk
+
+  '#clock-cells':
+    const: 1
+
+  '#reset-cells':
+    const: 1
+
+  '#power-domain-cells':
+    const: 1
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - clocks
+  - clock-names
+  - reg
+  - '#clock-cells'
+  - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    clock-controller@100000 {
+      compatible = "qcom,gcc-sm8350";
+      reg = <0x00100000 0x1f0000>;
+      clocks = <&rpmhcc RPMH_CXO_CLK>,
+               <&sleep_clk>;
+      clock-names = "bi_tcxo", "sleep_clk";
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+    };
+
+...
diff --git a/include/dt-bindings/clock/qcom,gcc-sm8350.h b/include/dt-bindings/clock/qcom,gcc-sm8350.h
new file mode 100644
index 000000000000..2462f64f6e75
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-sm8350.h
@@ -0,0 +1,261 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2020, Linaro Limited
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8350_H
+#define _DT_BINDINGS_CLK_QCOM_GCC_SM8350_H
+
+/* GCC HW clocks */
+#define CORE_BI_PLL_TEST_SE					0
+#define PCIE_0_PIPE_CLK						1
+#define PCIE_1_PIPE_CLK						2
+#define UFS_CARD_RX_SYMBOL_0_CLK				3
+#define UFS_CARD_RX_SYMBOL_1_CLK				4
+#define UFS_CARD_TX_SYMBOL_0_CLK				5
+#define UFS_PHY_RX_SYMBOL_0_CLK					6
+#define UFS_PHY_RX_SYMBOL_1_CLK					7
+#define UFS_PHY_TX_SYMBOL_0_CLK					8
+#define USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK			9
+#define USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK			10
+
+/* GCC clocks */
+#define GCC_AGGRE_NOC_PCIE_0_AXI_CLK				11
+#define GCC_AGGRE_NOC_PCIE_1_AXI_CLK				12
+#define GCC_AGGRE_NOC_PCIE_TBU_CLK				13
+#define GCC_AGGRE_UFS_CARD_AXI_CLK				14
+#define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK			15
+#define GCC_AGGRE_UFS_PHY_AXI_CLK				16
+#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK			17
+#define GCC_AGGRE_USB3_PRIM_AXI_CLK				18
+#define GCC_AGGRE_USB3_SEC_AXI_CLK				19
+#define GCC_BOOT_ROM_AHB_CLK					20
+#define GCC_CAMERA_AHB_CLK					21
+#define GCC_CAMERA_HF_AXI_CLK					22
+#define GCC_CAMERA_SF_AXI_CLK					23
+#define GCC_CAMERA_XO_CLK					24
+#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK				25
+#define GCC_CFG_NOC_USB3_SEC_AXI_CLK				26
+#define GCC_DDRSS_GPU_AXI_CLK					27
+#define GCC_DDRSS_PCIE_SF_TBU_CLK				28
+#define GCC_DISP_AHB_CLK					29
+#define GCC_DISP_HF_AXI_CLK					30
+#define GCC_DISP_SF_AXI_CLK					31
+#define GCC_DISP_XO_CLK						32
+#define GCC_GP1_CLK						33
+#define GCC_GP1_CLK_SRC						34
+#define GCC_GP2_CLK						35
+#define GCC_GP2_CLK_SRC						36
+#define GCC_GP3_CLK						37
+#define GCC_GP3_CLK_SRC						38
+#define GCC_GPLL0						39
+#define GCC_GPLL0_OUT_EVEN					40
+#define GCC_GPLL4						41
+#define GCC_GPLL9						42
+#define GCC_GPU_CFG_AHB_CLK					43
+#define GCC_GPU_GPLL0_CLK_SRC					44
+#define GCC_GPU_GPLL0_DIV_CLK_SRC				45
+#define GCC_GPU_IREF_EN						46
+#define GCC_GPU_MEMNOC_GFX_CLK					47
+#define GCC_GPU_SNOC_DVM_GFX_CLK				48
+#define GCC_PCIE0_PHY_RCHNG_CLK					49
+#define GCC_PCIE1_PHY_RCHNG_CLK					50
+#define GCC_PCIE_0_AUX_CLK					51
+#define GCC_PCIE_0_AUX_CLK_SRC					52
+#define GCC_PCIE_0_CFG_AHB_CLK					53
+#define GCC_PCIE_0_CLKREF_EN					54
+#define GCC_PCIE_0_MSTR_AXI_CLK					55
+#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC				56
+#define GCC_PCIE_0_PIPE_CLK					57
+#define GCC_PCIE_0_PIPE_CLK_SRC					58
+#define GCC_PCIE_0_SLV_AXI_CLK					59
+#define GCC_PCIE_0_SLV_Q2A_AXI_CLK				60
+#define GCC_PCIE_1_AUX_CLK					61
+#define GCC_PCIE_1_AUX_CLK_SRC					62
+#define GCC_PCIE_1_CFG_AHB_CLK					63
+#define GCC_PCIE_1_CLKREF_EN					64
+#define GCC_PCIE_1_MSTR_AXI_CLK					65
+#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC				66
+#define GCC_PCIE_1_PIPE_CLK					67
+#define GCC_PCIE_1_PIPE_CLK_SRC					68
+#define GCC_PCIE_1_SLV_AXI_CLK					69
+#define GCC_PCIE_1_SLV_Q2A_AXI_CLK				70
+#define GCC_PDM2_CLK						71
+#define GCC_PDM2_CLK_SRC					72
+#define GCC_PDM_AHB_CLK						73
+#define GCC_PDM_XO4_CLK						74
+#define GCC_QMIP_CAMERA_NRT_AHB_CLK				75
+#define GCC_QMIP_CAMERA_RT_AHB_CLK				76
+#define GCC_QMIP_DISP_AHB_CLK					77
+#define GCC_QMIP_VIDEO_CVP_AHB_CLK				78
+#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK				79
+#define GCC_QUPV3_WRAP0_CORE_2X_CLK				80
+#define GCC_QUPV3_WRAP0_CORE_CLK				81
+#define GCC_QUPV3_WRAP0_S0_CLK					82
+#define GCC_QUPV3_WRAP0_S0_CLK_SRC				83
+#define GCC_QUPV3_WRAP0_S1_CLK					84
+#define GCC_QUPV3_WRAP0_S1_CLK_SRC				85
+#define GCC_QUPV3_WRAP0_S2_CLK					86
+#define GCC_QUPV3_WRAP0_S2_CLK_SRC				87
+#define GCC_QUPV3_WRAP0_S3_CLK					88
+#define GCC_QUPV3_WRAP0_S3_CLK_SRC				89
+#define GCC_QUPV3_WRAP0_S4_CLK					90
+#define GCC_QUPV3_WRAP0_S4_CLK_SRC				91
+#define GCC_QUPV3_WRAP0_S5_CLK					92
+#define GCC_QUPV3_WRAP0_S5_CLK_SRC				93
+#define GCC_QUPV3_WRAP0_S6_CLK					94
+#define GCC_QUPV3_WRAP0_S6_CLK_SRC				95
+#define GCC_QUPV3_WRAP0_S7_CLK					96
+#define GCC_QUPV3_WRAP0_S7_CLK_SRC				97
+#define GCC_QUPV3_WRAP1_CORE_2X_CLK				98
+#define GCC_QUPV3_WRAP1_CORE_CLK				99
+#define GCC_QUPV3_WRAP1_S0_CLK					100
+#define GCC_QUPV3_WRAP1_S0_CLK_SRC				101
+#define GCC_QUPV3_WRAP1_S1_CLK					102
+#define GCC_QUPV3_WRAP1_S1_CLK_SRC				103
+#define GCC_QUPV3_WRAP1_S2_CLK					104
+#define GCC_QUPV3_WRAP1_S2_CLK_SRC				105
+#define GCC_QUPV3_WRAP1_S3_CLK					106
+#define GCC_QUPV3_WRAP1_S3_CLK_SRC				107
+#define GCC_QUPV3_WRAP1_S4_CLK					108
+#define GCC_QUPV3_WRAP1_S4_CLK_SRC				109
+#define GCC_QUPV3_WRAP1_S5_CLK					110
+#define GCC_QUPV3_WRAP1_S5_CLK_SRC				111
+#define GCC_QUPV3_WRAP2_CORE_2X_CLK				112
+#define GCC_QUPV3_WRAP2_CORE_CLK				113
+#define GCC_QUPV3_WRAP2_S0_CLK					114
+#define GCC_QUPV3_WRAP2_S0_CLK_SRC				115
+#define GCC_QUPV3_WRAP2_S1_CLK					116
+#define GCC_QUPV3_WRAP2_S1_CLK_SRC				117
+#define GCC_QUPV3_WRAP2_S2_CLK					118
+#define GCC_QUPV3_WRAP2_S2_CLK_SRC				119
+#define GCC_QUPV3_WRAP2_S3_CLK					120
+#define GCC_QUPV3_WRAP2_S3_CLK_SRC				121
+#define GCC_QUPV3_WRAP2_S4_CLK					122
+#define GCC_QUPV3_WRAP2_S4_CLK_SRC				123
+#define GCC_QUPV3_WRAP2_S5_CLK					124
+#define GCC_QUPV3_WRAP2_S5_CLK_SRC				125
+#define GCC_QUPV3_WRAP_0_M_AHB_CLK				126
+#define GCC_QUPV3_WRAP_0_S_AHB_CLK				127
+#define GCC_QUPV3_WRAP_1_M_AHB_CLK				128
+#define GCC_QUPV3_WRAP_1_S_AHB_CLK				129
+#define GCC_QUPV3_WRAP_2_M_AHB_CLK				130
+#define GCC_QUPV3_WRAP_2_S_AHB_CLK				131
+#define GCC_SDCC2_AHB_CLK					132
+#define GCC_SDCC2_APPS_CLK					133
+#define GCC_SDCC2_APPS_CLK_SRC					134
+#define GCC_SDCC4_AHB_CLK					135
+#define GCC_SDCC4_APPS_CLK					136
+#define GCC_SDCC4_APPS_CLK_SRC					137
+#define GCC_THROTTLE_PCIE_AHB_CLK				138
+#define GCC_UFS_1_CLKREF_EN					139
+#define GCC_UFS_CARD_AHB_CLK					140
+#define GCC_UFS_CARD_AXI_CLK					141
+#define GCC_UFS_CARD_AXI_CLK_SRC				142
+#define GCC_UFS_CARD_AXI_HW_CTL_CLK				143
+#define GCC_UFS_CARD_ICE_CORE_CLK				144
+#define GCC_UFS_CARD_ICE_CORE_CLK_SRC				145
+#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK			146
+#define GCC_UFS_CARD_PHY_AUX_CLK				147
+#define GCC_UFS_CARD_PHY_AUX_CLK_SRC				148
+#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK				149
+#define GCC_UFS_CARD_RX_SYMBOL_0_CLK				150
+#define GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC			151
+#define GCC_UFS_CARD_RX_SYMBOL_1_CLK				152
+#define GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC			153
+#define GCC_UFS_CARD_TX_SYMBOL_0_CLK				154
+#define GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC			155
+#define GCC_UFS_CARD_UNIPRO_CORE_CLK				156
+#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC			157
+#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK			158
+#define GCC_UFS_PHY_AHB_CLK					159
+#define GCC_UFS_PHY_AXI_CLK					160
+#define GCC_UFS_PHY_AXI_CLK_SRC					161
+#define GCC_UFS_PHY_AXI_HW_CTL_CLK				162
+#define GCC_UFS_PHY_ICE_CORE_CLK				163
+#define GCC_UFS_PHY_ICE_CORE_CLK_SRC				164
+#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK				165
+#define GCC_UFS_PHY_PHY_AUX_CLK					166
+#define GCC_UFS_PHY_PHY_AUX_CLK_SRC				167
+#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK				168
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK				169
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC				170
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK				171
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC				172
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK				173
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC				174
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK				175
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				176
+#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK			177
+#define GCC_USB30_PRIM_MASTER_CLK				178
+#define GCC_USB30_PRIM_MASTER_CLK__FORCE_MEM_CORE_ON		179
+#define GCC_USB30_PRIM_MASTER_CLK_SRC				180
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK				181
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			182
+#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC		183
+#define GCC_USB30_PRIM_SLEEP_CLK				184
+#define GCC_USB30_SEC_MASTER_CLK				185
+#define GCC_USB30_SEC_MASTER_CLK__FORCE_MEM_CORE_ON		186
+#define GCC_USB30_SEC_MASTER_CLK_SRC				187
+#define GCC_USB30_SEC_MOCK_UTMI_CLK				188
+#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC				189
+#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC			190
+#define GCC_USB30_SEC_SLEEP_CLK					191
+#define GCC_USB3_PRIM_PHY_AUX_CLK				192
+#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				193
+#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				194
+#define GCC_USB3_PRIM_PHY_PIPE_CLK				195
+#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC				196
+#define GCC_USB3_SEC_CLKREF_EN					197
+#define GCC_USB3_SEC_PHY_AUX_CLK				198
+#define GCC_USB3_SEC_PHY_AUX_CLK_SRC				199
+#define GCC_USB3_SEC_PHY_COM_AUX_CLK				200
+#define GCC_USB3_SEC_PHY_PIPE_CLK				201
+#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC				202
+#define GCC_VIDEO_AHB_CLK					203
+#define GCC_VIDEO_AXI0_CLK					204
+#define GCC_VIDEO_AXI1_CLK					205
+#define GCC_VIDEO_XO_CLK					206
+
+/* GCC resets */
+#define GCC_CAMERA_BCR						0
+#define GCC_DISPLAY_BCR						1
+#define GCC_GPU_BCR						2
+#define GCC_MMSS_BCR						3
+#define GCC_PCIE_0_BCR						4
+#define GCC_PCIE_0_LINK_DOWN_BCR				5
+#define GCC_PCIE_0_NOCSR_COM_PHY_BCR				6
+#define GCC_PCIE_0_PHY_BCR					7
+#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR			8
+#define GCC_PCIE_1_BCR						9
+#define GCC_PCIE_1_LINK_DOWN_BCR				10
+#define GCC_PCIE_1_NOCSR_COM_PHY_BCR				11
+#define GCC_PCIE_1_PHY_BCR					12
+#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR			13
+#define GCC_PCIE_PHY_CFG_AHB_BCR				14
+#define GCC_PCIE_PHY_COM_BCR					15
+#define GCC_PDM_BCR						16
+#define GCC_QUPV3_WRAPPER_0_BCR					17
+#define GCC_QUPV3_WRAPPER_1_BCR					18
+#define GCC_QUPV3_WRAPPER_2_BCR					19
+#define GCC_QUSB2PHY_PRIM_BCR					20
+#define GCC_QUSB2PHY_SEC_BCR					21
+#define GCC_SDCC2_BCR						22
+#define GCC_SDCC4_BCR						23
+#define GCC_UFS_CARD_BCR					24
+#define GCC_UFS_PHY_BCR						25
+#define GCC_USB30_PRIM_BCR					26
+#define GCC_USB30_SEC_BCR					27
+#define GCC_USB3_DP_PHY_PRIM_BCR				28
+#define GCC_USB3_DP_PHY_SEC_BCR					29
+#define GCC_USB3_PHY_PRIM_BCR					30
+#define GCC_USB3_PHY_SEC_BCR					31
+#define GCC_USB3PHY_PHY_PRIM_BCR				32
+#define GCC_USB3PHY_PHY_SEC_BCR					33
+#define GCC_USB_PHY_CFG_AHB2PHY_BCR				34
+#define GCC_VIDEO_AXI0_CLK_ARES					35
+#define GCC_VIDEO_AXI1_CLK_ARES					36
+#define GCC_VIDEO_BCR						37
+
+#endif
-- 
2.26.2

[PATCH 4/5] clk: qcom: clk-alpha-pll: Add support for Lucid 5LPE PLL

[Vinod Koul]

From: Vivek Aknurwar <viveka@codeaurora.org>

Lucid 5LPE is a slightly different Lucid PLL with different offsets and
porgramming sequence so add support for these

Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org>
Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org>
[vkoul: rebase and tidy up for upstream]
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
 drivers/clk/qcom/clk-alpha-pll.c | 223 +++++++++++++++++++++++++++++++
 drivers/clk/qcom/clk-alpha-pll.h |   4 +
 2 files changed, 227 insertions(+)

diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 564431130a76..31d86e5e55b7 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -146,6 +146,12 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
 /* LUCID PLL specific settings and offsets */
 #define LUCID_PCAL_DONE		BIT(27)
 
+/* LUCID 5LPE PLL specific settings and offsets */
+#define LUCID_5LPE_PCAL_DONE		BIT(11)
+#define LUCID_5LPE_ENABLE_VOTE_RUN	BIT(21)
+#define LUCID_5LPE_PLL_LATCH_INPUT	BIT(14)
+#define LUCID_5LPE_ALPHA_PLL_ACK_LATCH	BIT(13)
+
 #define pll_alpha_width(p)					\
 		((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ?	\
 				 ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
@@ -1561,3 +1567,220 @@ const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = {
 	.set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
 };
 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops);
+
+static int alpha_pll_lucid_5lpe_enable(struct clk_hw *hw)
+{
+	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+	u32 val;
+	int ret;
+
+	ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
+	if (ret)
+		return ret;
+
+	/* If in FSM mode, just vote for it */
+	if (val & LUCID_5LPE_ENABLE_VOTE_RUN) {
+		ret = clk_enable_regmap(hw);
+		if (ret)
+			return ret;
+		return wait_for_pll_enable_lock(pll);
+	}
+
+	/* Check if PLL is already enabled */
+	ret = trion_pll_is_enabled(pll, pll->clkr.regmap);
+	if (ret < 0)
+		return ret;
+
+	ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
+	if (ret)
+		return ret;
+
+	/* Set operation mode to RUN */
+	regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN);
+
+	ret = wait_for_pll_enable_lock(pll);
+	if (ret)
+		return ret;
+
+	/* Enable the PLL outputs */
+	ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK);
+	if (ret)
+		return ret;
+
+	/* Enable the global PLL outputs */
+	ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
+	if (ret)
+		return ret;
+
+	/* Ensure that the write above goes through before returning. */
+	mb();
+	return ret;
+}
+
+static void alpha_pll_lucid_5lpe_disable(struct clk_hw *hw)
+{
+	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+	u32 val;
+	int ret;
+
+	ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
+	if (ret)
+		return;
+
+	/* If in FSM mode, just unvote it */
+	if (val & LUCID_5LPE_ENABLE_VOTE_RUN) {
+		clk_disable_regmap(hw);
+		return;
+	}
+
+	/* Disable the global PLL output */
+	ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
+	if (ret)
+		return;
+
+	/* Disable the PLL outputs */
+	ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
+	if (ret)
+		return;
+
+	/* Place the PLL mode in STANDBY */
+	regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_STANDBY);
+}
+
+/*
+ * The Lucid 5LPE PLL requires a power-on self-calibration which happens
+ * when the PLL comes out of reset. Calibrate in case it is not completed.
+ */
+static int alpha_pll_lucid_5lpe_prepare(struct clk_hw *hw)
+{
+	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+	struct clk_hw *p;
+	u32 regval;
+	int ret;
+
+	/* Return early if calibration is not needed. */
+	regmap_read(pll->clkr.regmap, PLL_MODE(pll), &regval);
+	if (regval & LUCID_5LPE_PCAL_DONE)
+		return 0;
+
+	p = clk_hw_get_parent(hw);
+	if (!p)
+		return -EINVAL;
+
+	ret = alpha_pll_lucid_5lpe_enable(hw);
+	if (ret)
+		return ret;
+
+	alpha_pll_lucid_5lpe_disable(hw);
+
+	return 0;
+}
+
+static int alpha_pll_lucid_5lpe_set_rate(struct clk_hw *hw, unsigned long rate,
+					 unsigned long prate)
+{
+	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+	unsigned long rrate;
+	u32 regval, l;
+	u64 a;
+	int ret;
+
+	rrate = alpha_pll_round_rate(rate, prate, &l, &a, ALPHA_REG_16BIT_WIDTH);
+
+	/*
+	 * Due to a limited number of bits for fractional rate programming, the
+	 * rounded up rate could be marginally higher than the requested rate.
+	 */
+	if (rrate > (rate + PLL_RATE_MARGIN) || rrate < rate) {
+		pr_err("Call set rate on the PLL with rounded rates!\n");
+		return -EINVAL;
+	}
+
+	regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
+	regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
+
+	/* Latch the PLL input */
+	ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
+				 LUCID_5LPE_PLL_LATCH_INPUT, LUCID_5LPE_PLL_LATCH_INPUT);
+	if (ret)
+		return ret;
+
+	/* Wait for 2 reference cycles before checking the ACK bit. */
+	udelay(1);
+	regmap_read(pll->clkr.regmap, PLL_MODE(pll), &regval);
+	if (!(regval & LUCID_5LPE_ALPHA_PLL_ACK_LATCH)) {
+		pr_err("Lucid 5LPE PLL latch failed. Output may be unstable!\n");
+		return -EINVAL;
+	}
+
+	/* Return the latch input to 0 */
+	ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), LUCID_5LPE_PLL_LATCH_INPUT, 0);
+	if (ret)
+		return ret;
+
+	if (clk_hw_is_enabled(hw)) {
+		ret = wait_for_pll_enable_lock(pll);
+		if (ret)
+			return ret;
+	}
+
+	/* Wait for PLL output to stabilize */
+	udelay(100);
+	return 0;
+}
+
+static int clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
+					       unsigned long parent_rate)
+{
+	struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
+	int i, val = 0, div, ret;
+
+	/*
+	 * If the PLL is in FSM mode, then treat set_rate callback as a
+	 * no-operation.
+	 */
+	ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
+	if (ret)
+		return ret;
+
+	if (val & LUCID_5LPE_ENABLE_VOTE_RUN)
+		return 0;
+
+	if (!pll->post_div_table) {
+		pr_err("Missing the post_div_table for the PLL\n");
+		return -EINVAL;
+	}
+
+	div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
+	for (i = 0; i < pll->num_post_div; i++) {
+		if (pll->post_div_table[i].div == div) {
+			val = pll->post_div_table[i].val;
+			break;
+		}
+	}
+
+	return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
+				(BIT(pll->width) - 1) << pll->post_div_shift,
+				val << pll->post_div_shift);
+}
+
+const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = {
+	.prepare = alpha_pll_lucid_5lpe_prepare,
+	.enable = alpha_pll_lucid_5lpe_enable,
+	.disable = alpha_pll_lucid_5lpe_disable,
+	.set_rate = alpha_pll_lucid_5lpe_set_rate,
+};
+EXPORT_SYMBOL(clk_alpha_pll_lucid_5lpe_ops);
+
+const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = {
+	.enable = alpha_pll_lucid_5lpe_enable,
+	.disable = alpha_pll_lucid_5lpe_disable,
+};
+EXPORT_SYMBOL(clk_alpha_pll_fixed_lucid_5lpe_ops);
+
+const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = {
+	.recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
+	.round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
+	.set_rate = clk_lucid_5lpe_pll_postdiv_set_rate,
+};
+EXPORT_SYMBOL(clk_alpha_pll_postdiv_lucid_5lpe_ops);
diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
index d3201b87c0cd..d983b1aab8c8 100644
--- a/drivers/clk/qcom/clk-alpha-pll.h
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -142,6 +142,10 @@ extern const struct clk_ops clk_alpha_pll_lucid_ops;
 #define clk_alpha_pll_fixed_lucid_ops clk_alpha_pll_fixed_trion_ops
 extern const struct clk_ops clk_alpha_pll_postdiv_lucid_ops;
 
+extern const struct clk_ops clk_alpha_pll_lucid_5lpe_ops;
+extern const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops;
+extern const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops;
+
 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
 			     const struct alpha_pll_config *config);
 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
-- 
2.26.2

Re: [PATCH 2/5] clk: qcom: rpmh: add support for SM8350 rpmh clocks

[Bjorn Andersson]

On Thu 03 Dec 01:02 CST 2020, Vinod Koul wrote:

> This adds the RPMH clocks present in SM8350 SoC
> 
> Signed-off-by: Vinod Koul <vkoul@kernel.org>

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Regards,
Bjorn

> ---
>  drivers/clk/qcom/clk-rpmh.c           | 34 +++++++++++++++++++++++++++
>  include/dt-bindings/clock/qcom,rpmh.h |  8 +++++++
>  2 files changed, 42 insertions(+)
> 
> diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
> index e2c669b08aff..64cab4403a17 100644
> --- a/drivers/clk/qcom/clk-rpmh.c
> +++ b/drivers/clk/qcom/clk-rpmh.c
> @@ -432,6 +432,39 @@ static const struct clk_rpmh_desc clk_rpmh_sm8250 = {
>  	.num_clks = ARRAY_SIZE(sm8250_rpmh_clocks),
>  };
>  
> +DEFINE_CLK_RPMH_VRM(sm8350, div_clk1, div_clk1_ao, "divclka1", 2);
> +DEFINE_CLK_RPMH_VRM(sm8350, rf_clk4, rf_clk4_ao, "rfclka4", 1);
> +DEFINE_CLK_RPMH_VRM(sm8350, rf_clk5, rf_clk5_ao, "rfclka5", 1);
> +DEFINE_CLK_RPMH_BCM(sm8350, pka, "PKA0");
> +DEFINE_CLK_RPMH_BCM(sm8350, hwkm, "HK0");
> +
> +static struct clk_hw *sm8350_rpmh_clocks[] = {
> +	[RPMH_CXO_CLK]		= &sdm845_bi_tcxo.hw,
> +	[RPMH_CXO_CLK_A]	= &sdm845_bi_tcxo_ao.hw,
> +	[RPMH_DIV_CLK1]		= &sm8350_div_clk1.hw,
> +	[RPMH_DIV_CLK1_A]	= &sm8350_div_clk1_ao.hw,
> +	[RPMH_LN_BB_CLK1]	= &sm8250_ln_bb_clk1.hw,
> +	[RPMH_LN_BB_CLK1_A]	= &sm8250_ln_bb_clk1_ao.hw,
> +	[RPMH_LN_BB_CLK2]	= &sdm845_ln_bb_clk2.hw,
> +	[RPMH_LN_BB_CLK2_A]	= &sdm845_ln_bb_clk2_ao.hw,
> +	[RPMH_RF_CLK1]		= &sdm845_rf_clk1.hw,
> +	[RPMH_RF_CLK1_A]	= &sdm845_rf_clk1_ao.hw,
> +	[RPMH_RF_CLK3]		= &sdm845_rf_clk3.hw,
> +	[RPMH_RF_CLK3_A]	= &sdm845_rf_clk3_ao.hw,
> +	[RPMH_RF_CLK4]		= &sm8350_rf_clk4.hw,
> +	[RPMH_RF_CLK4_A]	= &sm8350_rf_clk4_ao.hw,
> +	[RPMH_RF_CLK5]		= &sm8350_rf_clk5.hw,
> +	[RPMH_RF_CLK5_A]	= &sm8350_rf_clk5_ao.hw,
> +	[RPMH_IPA_CLK]		= &sdm845_ipa.hw,
> +	[RPMH_PKA_CLK]		= &sm8350_pka.hw,
> +	[RPMH_HWKM_CLK]		= &sm8350_hwkm.hw,
> +};
> +
> +static const struct clk_rpmh_desc clk_rpmh_sm8350 = {
> +	.clks = sm8350_rpmh_clocks,
> +	.num_clks = ARRAY_SIZE(sm8350_rpmh_clocks),
> +};
> +
>  static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
>  					 void *data)
>  {
> @@ -519,6 +552,7 @@ static const struct of_device_id clk_rpmh_match_table[] = {
>  	{ .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845},
>  	{ .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150},
>  	{ .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250},
> +	{ .compatible = "qcom,sm8350-rpmh-clk", .data = &clk_rpmh_sm8350},
>  	{ }
>  };
>  MODULE_DEVICE_TABLE(of, clk_rpmh_match_table);
> diff --git a/include/dt-bindings/clock/qcom,rpmh.h b/include/dt-bindings/clock/qcom,rpmh.h
> index 2e6c54e65455..6dbe5d398bf0 100644
> --- a/include/dt-bindings/clock/qcom,rpmh.h
> +++ b/include/dt-bindings/clock/qcom,rpmh.h
> @@ -21,5 +21,13 @@
>  #define RPMH_IPA_CLK				12
>  #define RPMH_LN_BB_CLK1				13
>  #define RPMH_LN_BB_CLK1_A			14
> +#define RPMH_DIV_CLK1				15
> +#define RPMH_DIV_CLK1_A				16
> +#define RPMH_RF_CLK4				17
> +#define RPMH_RF_CLK4_A				18
> +#define RPMH_RF_CLK5				19
> +#define RPMH_RF_CLK5_A				20
> +#define RPMH_PKA_CLK				21
> +#define RPMH_HWKM_CLK				22
>  
>  #endif
> -- 
> 2.26.2
> 

Re: [PATCH 1/5] dt-bindings: clock: Add RPMHCC bindings for SM8350

[Bjorn Andersson]

On Thu 03 Dec 01:02 CST 2020, Vinod Koul wrote:

> Add bindings and update documentation for clock rpmh driver on SM8350.
> 
> Signed-off-by: Vinod Koul <vkoul@kernel.org>

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>

> ---
>  Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
> index a46a3a799a70..3037eb98c810 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
> @@ -21,6 +21,7 @@ properties:
>        - qcom,sdm845-rpmh-clk
>        - qcom,sm8150-rpmh-clk
>        - qcom,sm8250-rpmh-clk
> +      - qcom,sm8350-rpmh-clk
>  
>    clocks:
>      maxItems: 1
> -- 
> 2.26.2
> 

Re: [PATCH 5/5] clk: qcom: gcc: Add clock driver for SM8350

[Bjorn Andersson]

On Thu 03 Dec 01:02 CST 2020, Vinod Koul wrote:
> diff --git a/drivers/clk/qcom/gcc-sm8350.c b/drivers/clk/qcom/gcc-sm8350.c
[..]
> +static int gcc_sm8350_probe(struct platform_device *pdev)
> +{
> +	struct regmap *regmap;
> +	int ret;
> +
> +	regmap = qcom_cc_map(pdev, &gcc_sm8350_desc);
> +	if (IS_ERR(regmap)) {
> +		dev_err(&pdev->dev, "Failed to map gcc registers\n");
> +		return PTR_ERR(regmap);
> +	}
> +
> +	ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks));
> +	if (ret)
> +		return ret;
> +
> +	/* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
> +	regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14));
> +
> +	/*
> +	 * Enable clocks required by the i2c-connected pm8008 regulators. Don't
> +	 * register them with the clock framework so that client requests are
> +	 * short-circuited before grabbing the enable/prepare locks. This
> +	 * prevents deadlocks between the clk/regulator frameworks.
> +	 *
> +	 *	gcc_qupv3_wrap_1_m_ahb_clk
> +	 *	gcc_qupv3_wrap_1_s_ahb_clk
> +	 *	gcc_qupv3_wrap1_s5_clk
> +	 */

Isn't this a workaround inherited from the downstream control of
regulators from within the clock core? Does this still apply upstream?

Regards,
Bjorn

> +	regmap_update_bits(regmap, 0x52008, BIT(20), BIT(20));
> +	regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
> +	regmap_update_bits(regmap, 0x52008, BIT(27), BIT(27));
> +
> +	return qcom_cc_really_probe(pdev, &gcc_sm8350_desc, regmap);
> +}
> +
> +static struct platform_driver gcc_sm8350_driver = {
> +	.probe = gcc_sm8350_probe,
> +	.driver = {
> +		.name = "sm8350-gcc",
> +		.of_match_table = gcc_sm8350_match_table,
> +	},
> +};
> +
> +static int __init gcc_sm8350_init(void)
> +{
> +	return platform_driver_register(&gcc_sm8350_driver);
> +}
> +subsys_initcall(gcc_sm8350_init);
> +
> +static void __exit gcc_sm8350_exit(void)
> +{
> +	platform_driver_unregister(&gcc_sm8350_driver);
> +}
> +module_exit(gcc_sm8350_exit);
> +
> +MODULE_DESCRIPTION("QTI GCC SM8350 Driver");
> +MODULE_LICENSE("GPL v2");
> -- 
> 2.26.2
> 

Re: [PATCH 5/5] clk: qcom: gcc: Add clock driver for SM8350

[Vinod Koul]

Hi Bjorn,

On 03-12-20, 18:06, Bjorn Andersson wrote:
> On Thu 03 Dec 01:02 CST 2020, Vinod Koul wrote:
> > diff --git a/drivers/clk/qcom/gcc-sm8350.c b/drivers/clk/qcom/gcc-sm8350.c
> [..]
> > +static int gcc_sm8350_probe(struct platform_device *pdev)
> > +{
> > +	struct regmap *regmap;
> > +	int ret;
> > +
> > +	regmap = qcom_cc_map(pdev, &gcc_sm8350_desc);
> > +	if (IS_ERR(regmap)) {
> > +		dev_err(&pdev->dev, "Failed to map gcc registers\n");
> > +		return PTR_ERR(regmap);
> > +	}
> > +
> > +	ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks));
> > +	if (ret)
> > +		return ret;
> > +
> > +	/* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
> > +	regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14));
> > +
> > +	/*
> > +	 * Enable clocks required by the i2c-connected pm8008 regulators. Don't
> > +	 * register them with the clock framework so that client requests are
> > +	 * short-circuited before grabbing the enable/prepare locks. This
> > +	 * prevents deadlocks between the clk/regulator frameworks.
> > +	 *
> > +	 *	gcc_qupv3_wrap_1_m_ahb_clk
> > +	 *	gcc_qupv3_wrap_1_s_ahb_clk
> > +	 *	gcc_qupv3_wrap1_s5_clk
> > +	 */
> 
> Isn't this a workaround inherited from the downstream control of
> regulators from within the clock core? Does this still apply upstream?

Let me check on this bit...

Thanks
-- 
~Vinod

Re: [PATCH 5/5] clk: qcom: gcc: Add clock driver for SM8350

[Taniya Das]

Hi Vinod,

On 12/4/2020 10:05 AM, Vinod Koul wrote:
> Hi Bjorn,
> 
> On 03-12-20, 18:06, Bjorn Andersson wrote:
>> On Thu 03 Dec 01:02 CST 2020, Vinod Koul wrote:
>>> diff --git a/drivers/clk/qcom/gcc-sm8350.c b/drivers/clk/qcom/gcc-sm8350.c
>> [..]
>>> +static int gcc_sm8350_probe(struct platform_device *pdev)
>>> +{
>>> +	struct regmap *regmap;
>>> +	int ret;
>>> +
>>> +	regmap = qcom_cc_map(pdev, &gcc_sm8350_desc);
>>> +	if (IS_ERR(regmap)) {
>>> +		dev_err(&pdev->dev, "Failed to map gcc registers\n");
>>> +		return PTR_ERR(regmap);
>>> +	}
>>> +
>>> +	ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks));
>>> +	if (ret)
>>> +		return ret;
>>> +
>>> +	/* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
>>> +	regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14));
>>> +
>>> +	/*
>>> +	 * Enable clocks required by the i2c-connected pm8008 regulators. Don't
>>> +	 * register them with the clock framework so that client requests are
>>> +	 * short-circuited before grabbing the enable/prepare locks. This
>>> +	 * prevents deadlocks between the clk/regulator frameworks.
>>> +	 *
>>> +	 *	gcc_qupv3_wrap_1_m_ahb_clk
>>> +	 *	gcc_qupv3_wrap_1_s_ahb_clk
>>> +	 *	gcc_qupv3_wrap1_s5_clk
>>> +	 */
>>
>> Isn't this a workaround inherited from the downstream control of
>> regulators from within the clock core? Does this still apply upstream?
> 
> Let me check on this bit...
> 
> Thanks
> 

No it should not apply.

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation.

--

Re: [PATCH 5/5] clk: qcom: gcc: Add clock driver for SM8350

[Vinod Koul]

Hi Taniya,

On 04-12-20, 14:20, Taniya Das wrote:
> On 12/4/2020 10:05 AM, Vinod Koul wrote:
> > On 03-12-20, 18:06, Bjorn Andersson wrote:
> > > On Thu 03 Dec 01:02 CST 2020, Vinod Koul wrote:
> > > > diff --git a/drivers/clk/qcom/gcc-sm8350.c b/drivers/clk/qcom/gcc-sm8350.c
> > > [..]
> > > > +static int gcc_sm8350_probe(struct platform_device *pdev)
> > > > +{
> > > > +	struct regmap *regmap;
> > > > +	int ret;
> > > > +
> > > > +	regmap = qcom_cc_map(pdev, &gcc_sm8350_desc);
> > > > +	if (IS_ERR(regmap)) {
> > > > +		dev_err(&pdev->dev, "Failed to map gcc registers\n");
> > > > +		return PTR_ERR(regmap);
> > > > +	}
> > > > +
> > > > +	ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks));
> > > > +	if (ret)
> > > > +		return ret;
> > > > +
> > > > +	/* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
> > > > +	regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14));
> > > > +
> > > > +	/*
> > > > +	 * Enable clocks required by the i2c-connected pm8008 regulators. Don't
> > > > +	 * register them with the clock framework so that client requests are
> > > > +	 * short-circuited before grabbing the enable/prepare locks. This
> > > > +	 * prevents deadlocks between the clk/regulator frameworks.
> > > > +	 *
> > > > +	 *	gcc_qupv3_wrap_1_m_ahb_clk
> > > > +	 *	gcc_qupv3_wrap_1_s_ahb_clk
> > > > +	 *	gcc_qupv3_wrap1_s5_clk
> > > > +	 */
> > > 
> > > Isn't this a workaround inherited from the downstream control of
> > > regulators from within the clock core? Does this still apply upstream?
> > 
> > Let me check on this bit...
> > 
> > Thanks
> > 
> 
> No it should not apply.

Thanks for confirmation, removed now. Will send v2

-- 
~Vinod