From: Damien Le Moal <damien.lemoal@wdc.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
linux-riscv@lists.infradead.org, Rob Herring <robh+dt@kernel.org>,
devicetree@vger.kernel.org, Stephen Boyd <sboyd@kernel.org>,
linux-clk@vger.kernel.org,
Linus Walleij <linus.walleij@linaro.org>,
linux-gpio@vger.kernel.org,
Philipp Zabel <p.zabel@pengutronix.de>
Cc: Sean Anderson <seanga2@gmail.com>
Subject: [PATCH v8 08/22] dt-binding: clock: Document canaan,k210-clk bindings
Date: Thu, 10 Dec 2020 23:02:59 +0900 [thread overview]
Message-ID: <20201210140313.258739-9-damien.lemoal@wdc.com> (raw)
In-Reply-To: <20201210140313.258739-1-damien.lemoal@wdc.com>
Document the device tree bindings of the Canaan Kendryte K210 SoC clock
driver in Documentation/devicetree/bindings/clock/canaan,k210-clk.yaml.
The header file include/dt-bindings/clock/k210-clk.h is modified to
include the complete list of IDs for all clocks of the SoC.
Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
---
.../bindings/clock/canaan,k210-clk.yaml | 54 ++++++++++++++++++
include/dt-bindings/clock/k210-clk.h | 55 +++++++++++++++----
2 files changed, 98 insertions(+), 11 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/canaan,k210-clk.yaml
diff --git a/Documentation/devicetree/bindings/clock/canaan,k210-clk.yaml b/Documentation/devicetree/bindings/clock/canaan,k210-clk.yaml
new file mode 100644
index 000000000000..565ca468cb44
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/canaan,k210-clk.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/canaan,k210-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Canaan Kendryte K210 Clock Device Tree Bindings
+
+maintainers:
+ - Damien Le Moal <damien.lemoal@wdc.com>
+
+description: |
+ Canaan Kendryte K210 SoC clocks driver bindings. The clock
+ controller node must be defined as a child node of the K210
+ system controller node.
+
+ See also:
+ - dt-bindings/clock/k210-clk.h
+
+properties:
+ compatible:
+ const: canaan,k210-clk
+
+ clocks:
+ description:
+ Phandle of the SoC 26MHz fixed-rate oscillator clock.
+
+ '#clock-cells':
+ const: 1
+
+required:
+ - compatible
+ - '#clock-cells'
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/k210-clk.h>
+ clocks {
+ in0: oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+ };
+
+ /* ... */
+ sysclk: clock-controller {
+ #clock-cells = <1>;
+ compatible = "canaan,k210-clk";
+ clocks = <&in0>;
+ };
diff --git a/include/dt-bindings/clock/k210-clk.h b/include/dt-bindings/clock/k210-clk.h
index 5a2fd64d1a49..b2de702cbf75 100644
--- a/include/dt-bindings/clock/k210-clk.h
+++ b/include/dt-bindings/clock/k210-clk.h
@@ -3,18 +3,51 @@
* Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
* Copyright (c) 2020 Western Digital Corporation or its affiliates.
*/
-#ifndef K210_CLK_H
-#define K210_CLK_H
+#ifndef CLOCK_K210_CLK_H
+#define CLOCK_K210_CLK_H
/*
- * Arbitrary identifiers for clocks.
- * The structure is: in0 -> pll0 -> aclk -> cpu
- *
- * Since we use the hardware defaults for now, set all these to the same clock.
+ * Kendryte K210 SoC clock identifiers (arbitrary values).
*/
-#define K210_CLK_PLL0 0
-#define K210_CLK_PLL1 0
-#define K210_CLK_ACLK 0
-#define K210_CLK_CPU 0
+#define K210_CLK_CPU 0
+#define K210_CLK_SRAM0 1
+#define K210_CLK_SRAM1 2
+#define K210_CLK_AI 3
+#define K210_CLK_DMA 4
+#define K210_CLK_FFT 5
+#define K210_CLK_ROM 6
+#define K210_CLK_DVP 7
+#define K210_CLK_APB0 8
+#define K210_CLK_APB1 9
+#define K210_CLK_APB2 10
+#define K210_CLK_I2S0 11
+#define K210_CLK_I2S1 12
+#define K210_CLK_I2S2 13
+#define K210_CLK_I2S0_M 14
+#define K210_CLK_I2S1_M 15
+#define K210_CLK_I2S2_M 16
+#define K210_CLK_WDT0 17
+#define K210_CLK_WDT1 18
+#define K210_CLK_SPI0 19
+#define K210_CLK_SPI1 20
+#define K210_CLK_SPI2 21
+#define K210_CLK_I2C0 22
+#define K210_CLK_I2C1 23
+#define K210_CLK_I2C2 24
+#define K210_CLK_SPI3 25
+#define K210_CLK_TIMER0 26
+#define K210_CLK_TIMER1 27
+#define K210_CLK_TIMER2 28
+#define K210_CLK_GPIO 29
+#define K210_CLK_UART1 30
+#define K210_CLK_UART2 31
+#define K210_CLK_UART3 32
+#define K210_CLK_FPIOA 33
+#define K210_CLK_SHA 34
+#define K210_CLK_AES 35
+#define K210_CLK_OTP 36
+#define K210_CLK_RTC 37
-#endif /* K210_CLK_H */
+#define K210_NUM_CLKS 38
+
+#endif /* CLOCK_K210_CLK_H */
--
2.29.2
next prev parent reply other threads:[~2020-12-10 14:06 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-10 14:02 [PATCH v8 00/22] RISC-V Kendryte K210 support improvements Damien Le Moal
2020-12-10 14:02 ` [PATCH v8 01/22] riscv: Fix kernel time_init() Damien Le Moal
2020-12-11 2:09 ` Palmer Dabbelt
2020-12-10 14:02 ` [PATCH v8 02/22] riscv: Fix sifive serial driver Damien Le Moal
2020-12-11 2:09 ` Palmer Dabbelt
2020-12-11 4:34 ` Damien Le Moal
2020-12-10 14:02 ` [PATCH v8 03/22] riscv: Enable interrupts during syscalls with M-Mode Damien Le Moal
2020-12-11 2:09 ` Palmer Dabbelt
2020-12-10 14:02 ` [PATCH v8 04/22] riscv: Fix builtin DTB handling Damien Le Moal
2020-12-10 14:02 ` [PATCH v8 05/22] riscv: Use vendor name for K210 SoC support Damien Le Moal
2020-12-10 14:02 ` [PATCH v8 06/22] riscv: cleanup Canaan Kendryte K210 sysctl driver Damien Le Moal
2020-12-10 14:02 ` [PATCH v8 07/22] dt-bindings: Add Canaan vendor prefix Damien Le Moal
2020-12-11 3:47 ` Rob Herring
2020-12-10 14:02 ` Damien Le Moal [this message]
2020-12-11 3:48 ` [PATCH v8 08/22] dt-binding: clock: Document canaan,k210-clk bindings Rob Herring
2020-12-10 14:03 ` [PATCH v8 09/22] dt-bindings: reset: Document canaan,k210-rst bindings Damien Le Moal
2020-12-11 3:48 ` Rob Herring
2020-12-10 14:03 ` [PATCH v8 10/22] dt-bindings: pinctrl: Document canaan,k210-fpioa bindings Damien Le Moal
2020-12-11 3:51 ` Rob Herring
2020-12-10 14:03 ` [PATCH v8 11/22] dt-binding: mfd: Document canaan,k210-sysctl bindings Damien Le Moal
2020-12-11 3:54 ` Rob Herring
2020-12-10 14:03 ` [PATCH v8 12/22] riscv: Add Canaan Kendryte K210 clock driver Damien Le Moal
2020-12-10 14:03 ` [PATCH v8 13/22] riscv: Add Canaan Kendryte K210 reset controller Damien Le Moal
2020-12-10 14:03 ` [PATCH v8 14/22] riscv: Add Canaan Kendryte K210 FPIOA driver Damien Le Moal
2020-12-10 14:03 ` [PATCH v8 15/22] riscv: Update Canaan Kendryte K210 device tree Damien Le Moal
2020-12-10 14:03 ` [PATCH v8 16/22] riscv: Add SiPeed MAIX BiT board " Damien Le Moal
2020-12-10 14:03 ` [PATCH v8 17/22] riscv: Add SiPeed MAIX DOCK " Damien Le Moal
2020-12-10 14:03 ` [PATCH v8 18/22] riscv: Add SiPeed MAIX GO " Damien Le Moal
2020-12-10 14:03 ` [PATCH v8 19/22] riscv: Add SiPeed MAIXDUINO " Damien Le Moal
2020-12-10 14:03 ` [PATCH v8 20/22] riscv: Add Kendryte KD233 " Damien Le Moal
2020-12-10 14:03 ` [PATCH v8 21/22] riscv: Update Canaan Kendryte K210 defconfig Damien Le Moal
2020-12-10 14:03 ` [PATCH v8 22/22] riscv: Add Canaan Kendryte K210 SD card defconfig Damien Le Moal
2020-12-13 6:04 ` [PATCH v8 00/22] RISC-V Kendryte K210 support improvements Stephen Boyd
2020-12-13 8:06 ` Damien Le Moal
2020-12-16 1:42 ` Palmer Dabbelt
2020-12-16 2:12 ` Damien Le Moal
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