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From: Damien Le Moal <Damien.LeMoal@wdc.com>
To: "palmer@dabbelt.com" <palmer@dabbelt.com>
Cc: "linux-riscv@lists.infradead.org"
	<linux-riscv@lists.infradead.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-gpio@vger.kernel.org" <linux-gpio@vger.kernel.org>,
	"linus.walleij@linaro.org" <linus.walleij@linaro.org>,
	"sboyd@kernel.org" <sboyd@kernel.org>,
	"seanga2@gmail.com" <seanga2@gmail.com>,
	"p.zabel@pengutronix.de" <p.zabel@pengutronix.de>,
	"robh+dt@kernel.org" <robh+dt@kernel.org>,
	"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>
Subject: Re: [PATCH v8 02/22] riscv: Fix sifive serial driver
Date: Fri, 11 Dec 2020 04:34:51 +0000	[thread overview]
Message-ID: <3c3238a00beaab166a67e3baf0ad4714d3c90ef1.camel@wdc.com> (raw)
In-Reply-To: <mhng-b369aaef-f262-4ca3-bcda-5bd4ee893332@palmerdabbelt-glaptop1>

On Thu, 2020-12-10 at 18:09 -0800, Palmer Dabbelt wrote:
> On Thu, 10 Dec 2020 06:02:53 PST (-0800), Damien Le Moal wrote:
> > Setup the port uartclk in sifive_serial_probe() so that the base baud
> > rate is correctly printed during device probe instead of always showing
> > "0".  I.e. the probe message is changed from
> > 
> > 38000000.serial: ttySIF0 at MMIO 0x38000000 (irq = 1,
> > base_baud = 0) is a SiFive UART v0
> > 
> > to the correct:
> > 
> > 38000000.serial: ttySIF0 at MMIO 0x38000000 (irq = 1,
> > base_baud = 115200) is a SiFive UART v0
> > 
> > Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
> > ---
> >  drivers/tty/serial/sifive.c | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/drivers/tty/serial/sifive.c b/drivers/tty/serial/sifive.c
> > index 13eadcb8aec4..214bf3086c68 100644
> > --- a/drivers/tty/serial/sifive.c
> > +++ b/drivers/tty/serial/sifive.c
> > @@ -999,6 +999,7 @@ static int sifive_serial_probe(struct platform_device *pdev)
> >  	/* Set up clock divider */
> >  	ssp->clkin_rate = clk_get_rate(ssp->clk);
> >  	ssp->baud_rate = SIFIVE_DEFAULT_BAUD_RATE;
> > +	ssp->port.uartclk = ssp->baud_rate * 16;
> >  	__ssp_update_div(ssp);
> > 
> >  	platform_set_drvdata(pdev, ssp);
> 
> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
> 
> As an aside: is this an intrinsic property of being a serial port, or specific
> to the SiFive driver?  We seem to multiply/divide by 16 quite a bit to convert
> between baud rates and clocks, so if it's specific to SiFive then it seems
> reasonable to name that constant in this driver.  If it's a serial thing then I
> guess we should just do whatever everyone else is doing.

That port.uartclk field is not specific to the sifive driver. And setting its
value correctly lead to the correct message being printed. That message is also
generic and not special to the SiFive serial driver.

> Don't think that blocks this patch, though, as it's all over the place.

I did not dig too far in that driver, I only wanted to fix the message so that
meaningful information is printed. But yes, I also thought that a little
cleanup would be good. The DT binding doc is also incomplete as it is missing
the "sifive,fu540-c000-uart0" compatible string.


-- 
Damien Le Moal
Western Digital

  reply	other threads:[~2020-12-11  4:37 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-10 14:02 [PATCH v8 00/22] RISC-V Kendryte K210 support improvements Damien Le Moal
2020-12-10 14:02 ` [PATCH v8 01/22] riscv: Fix kernel time_init() Damien Le Moal
2020-12-11  2:09   ` Palmer Dabbelt
2020-12-10 14:02 ` [PATCH v8 02/22] riscv: Fix sifive serial driver Damien Le Moal
2020-12-11  2:09   ` Palmer Dabbelt
2020-12-11  4:34     ` Damien Le Moal [this message]
2020-12-10 14:02 ` [PATCH v8 03/22] riscv: Enable interrupts during syscalls with M-Mode Damien Le Moal
2020-12-11  2:09   ` Palmer Dabbelt
2020-12-10 14:02 ` [PATCH v8 04/22] riscv: Fix builtin DTB handling Damien Le Moal
2020-12-10 14:02 ` [PATCH v8 05/22] riscv: Use vendor name for K210 SoC support Damien Le Moal
2020-12-10 14:02 ` [PATCH v8 06/22] riscv: cleanup Canaan Kendryte K210 sysctl driver Damien Le Moal
2020-12-10 14:02 ` [PATCH v8 07/22] dt-bindings: Add Canaan vendor prefix Damien Le Moal
2020-12-11  3:47   ` Rob Herring
2020-12-10 14:02 ` [PATCH v8 08/22] dt-binding: clock: Document canaan,k210-clk bindings Damien Le Moal
2020-12-11  3:48   ` Rob Herring
2020-12-10 14:03 ` [PATCH v8 09/22] dt-bindings: reset: Document canaan,k210-rst bindings Damien Le Moal
2020-12-11  3:48   ` Rob Herring
2020-12-10 14:03 ` [PATCH v8 10/22] dt-bindings: pinctrl: Document canaan,k210-fpioa bindings Damien Le Moal
2020-12-11  3:51   ` Rob Herring
2020-12-10 14:03 ` [PATCH v8 11/22] dt-binding: mfd: Document canaan,k210-sysctl bindings Damien Le Moal
2020-12-11  3:54   ` Rob Herring
2020-12-10 14:03 ` [PATCH v8 12/22] riscv: Add Canaan Kendryte K210 clock driver Damien Le Moal
2020-12-10 14:03 ` [PATCH v8 13/22] riscv: Add Canaan Kendryte K210 reset controller Damien Le Moal
2020-12-10 14:03 ` [PATCH v8 14/22] riscv: Add Canaan Kendryte K210 FPIOA driver Damien Le Moal
2020-12-10 14:03 ` [PATCH v8 15/22] riscv: Update Canaan Kendryte K210 device tree Damien Le Moal
2020-12-10 14:03 ` [PATCH v8 16/22] riscv: Add SiPeed MAIX BiT board " Damien Le Moal
2020-12-10 14:03 ` [PATCH v8 17/22] riscv: Add SiPeed MAIX DOCK " Damien Le Moal
2020-12-10 14:03 ` [PATCH v8 18/22] riscv: Add SiPeed MAIX GO " Damien Le Moal
2020-12-10 14:03 ` [PATCH v8 19/22] riscv: Add SiPeed MAIXDUINO " Damien Le Moal
2020-12-10 14:03 ` [PATCH v8 20/22] riscv: Add Kendryte KD233 " Damien Le Moal
2020-12-10 14:03 ` [PATCH v8 21/22] riscv: Update Canaan Kendryte K210 defconfig Damien Le Moal
2020-12-10 14:03 ` [PATCH v8 22/22] riscv: Add Canaan Kendryte K210 SD card defconfig Damien Le Moal
2020-12-13  6:04 ` [PATCH v8 00/22] RISC-V Kendryte K210 support improvements Stephen Boyd
2020-12-13  8:06   ` Damien Le Moal
2020-12-16  1:42     ` Palmer Dabbelt
2020-12-16  2:12       ` Damien Le Moal

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