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From: AngeloGioacchino Del Regno  <angelogioacchino.delregno@somainline.org>
To: linux-arm-msm@vger.kernel.org
Cc: konrad.dybcio@somainline.org, marijn.suijten@somainline.org,
	martin.botka@somainline.org, phone-devel@vger.kernel.org,
	linux-kernel@vger.kernel.org, agross@kernel.org,
	bjorn.andersson@linaro.org, mturquette@baylibre.com,
	sboyd@kernel.org, robh+dt@kernel.org, linux-clk@vger.kernel.org,
	devicetree@vger.kernel.org,
	AngeloGioacchino Del Regno 
	<angelogioacchino.delregno@somainline.org>
Subject: [PATCH 9/9] clk: qcom: gpucc-msm8998: Allow fabia gpupll0 rate setting
Date: Sat,  9 Jan 2021 14:46:17 +0100	[thread overview]
Message-ID: <20210109134617.146275-10-angelogioacchino.delregno@somainline.org> (raw)
In-Reply-To: <20210109134617.146275-1-angelogioacchino.delregno@somainline.org>

The GPU PLL0 is not a fixed PLL and the rate can be set on it:
this is necessary especially on boards which bootloader is setting
a very low rate on this PLL before booting Linux, which would be
unsuitable for postdividing to reach the maximum allowed Adreno GPU
frequency of 710MHz (or, actually, even 670MHz..) on this SoC.

To allow setting rates on the GPU PLL0, also define VCO boundaries
and set the CLK_SET_RATE_PARENT flag to the GPU PLL0 postdivider.

With this change, the Adreno GPU is now able to scale through all
the available frequencies.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
---
 drivers/clk/qcom/gpucc-msm8998.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/qcom/gpucc-msm8998.c b/drivers/clk/qcom/gpucc-msm8998.c
index 1a518c4915b4..fedfffaf0a8d 100644
--- a/drivers/clk/qcom/gpucc-msm8998.c
+++ b/drivers/clk/qcom/gpucc-msm8998.c
@@ -50,6 +50,11 @@ static struct clk_branch gpucc_cxo_clk = {
 	},
 };
 
+static struct pll_vco fabia_vco[] = {
+	{ 249600000, 2000000000, 0 },
+	{ 125000000, 1000000000, 1 },
+};
+
 static const struct clk_div_table post_div_table_fabia_even[] = {
 	{ 0x0, 1 },
 	{ 0x1, 2 },
@@ -61,11 +66,13 @@ static const struct clk_div_table post_div_table_fabia_even[] = {
 static struct clk_alpha_pll gpupll0 = {
 	.offset = 0x0,
 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
+	.vco_table = fabia_vco,
+	.num_vco = ARRAY_SIZE(fabia_vco),
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "gpupll0",
 		.parent_hws = (const struct clk_hw *[]){ &gpucc_cxo_clk.clkr.hw },
 		.num_parents = 1,
-		.ops = &clk_alpha_pll_fixed_fabia_ops,
+		.ops = &clk_alpha_pll_fabia_ops,
 	},
 };
 
@@ -80,6 +87,7 @@ static struct clk_alpha_pll_postdiv gpupll0_out_even = {
 		.name = "gpupll0_out_even",
 		.parent_hws = (const struct clk_hw *[]){ &gpupll0.clkr.hw },
 		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_alpha_pll_postdiv_fabia_ops,
 	},
 };
-- 
2.29.2


      parent reply	other threads:[~2021-01-09 13:55 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-09 13:46 [PATCH 0/9] Clock fixes for MSM8998 GCC, MMCC, GPUCC AngeloGioacchino Del Regno
2021-01-09 13:46 ` [PATCH 1/9] clk: qcom: gcc-msm8998: Wire up gcc_mmss_gpll0 clock AngeloGioacchino Del Regno
2021-01-14 19:07   ` Rob Herring
2021-01-14 21:44     ` AngeloGioacchino Del Regno
2021-01-14 22:12   ` Jeffrey Hugo
2021-01-14 22:13     ` AngeloGioacchino Del Regno
2021-01-14 22:33       ` Jeffrey Hugo
2021-01-14 22:40         ` AngeloGioacchino Del Regno
2021-01-14 22:44           ` Jeffrey Hugo
2021-01-14 22:49             ` AngeloGioacchino Del Regno
2021-01-09 13:46 ` [PATCH 2/9] clk: qcom: gcc-msm8998: Add missing hmss_gpll0_clk_src clock AngeloGioacchino Del Regno
2021-01-09 13:46 ` [PATCH 3/9] clk: qcom: gcc-msm8998: Mark gpu_cfg_ahb_clk as critical AngeloGioacchino Del Regno
2021-01-09 13:46 ` [PATCH 4/9] clk: qcom: gcc-msm8998: Fix Alpha PLL type for all GPLLs AngeloGioacchino Del Regno
2021-01-09 13:46 ` [PATCH 5/9] clk: qcom: mmcc-msm8998: Set CLK_GET_RATE_NOCACHE to pixel/byte clks AngeloGioacchino Del Regno
2021-01-09 13:46 ` [PATCH 6/9] clk: qcom: mmcc-msm8998: Add hardware clockgating registers to some clks AngeloGioacchino Del Regno
2021-01-09 13:46 ` [PATCH 7/9] clk: qcom: mmcc-msm8998: Set bimc_smmu_gdsc always on AngeloGioacchino Del Regno
2021-01-09 13:46 ` [PATCH 8/9] clk: qcom: gpucc-msm8998: Add resets, cxc, fix flags on gpu_gx_gdsc AngeloGioacchino Del Regno
2021-01-09 13:46 ` AngeloGioacchino Del Regno [this message]

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