From: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
To: linux-arm-msm@vger.kernel.org
Cc: konrad.dybcio@somainline.org, marijn.suijten@somainline.org,
martin.botka@somainline.org, phone-devel@vger.kernel.org,
linux-kernel@vger.kernel.org, agross@kernel.org,
bjorn.andersson@linaro.org, mturquette@baylibre.com,
sboyd@kernel.org, robh+dt@kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@somainline.org>
Subject: [PATCH 1/9] clk: qcom: gcc-msm8998: Wire up gcc_mmss_gpll0 clock
Date: Sat, 9 Jan 2021 14:46:09 +0100 [thread overview]
Message-ID: <20210109134617.146275-2-angelogioacchino.delregno@somainline.org> (raw)
In-Reply-To: <20210109134617.146275-1-angelogioacchino.delregno@somainline.org>
This clock enables the GPLL0 output to the multimedia subsystem
clock controller.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
---
drivers/clk/qcom/gcc-msm8998.c | 17 +++++++++++++++++
include/dt-bindings/clock/qcom,gcc-msm8998.h | 1 +
2 files changed, 18 insertions(+)
diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c
index 9d7016bcd680..d51c556851ca 100644
--- a/drivers/clk/qcom/gcc-msm8998.c
+++ b/drivers/clk/qcom/gcc-msm8998.c
@@ -1341,6 +1341,22 @@ static struct clk_branch gcc_boot_rom_ahb_clk = {
},
};
+static struct clk_branch gcc_mmss_gpll0_clk = {
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mmss_gpll0_clk",
+ .parent_names = (const char *[]){
+ "gpll0_out_main",
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_branch gcc_mss_gpll0_div_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
@@ -2944,6 +2960,7 @@ static struct clk_regmap *gcc_msm8998_clocks[] = {
[GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr,
[GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
[GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,
+ [GCC_MMSS_GPLL0_CLK] = &gcc_mmss_gpll0_clk.clkr,
};
static struct gdsc *gcc_msm8998_gdscs[] = {
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8998.h b/include/dt-bindings/clock/qcom,gcc-msm8998.h
index 6a73a174f049..47ca17df780b 100644
--- a/include/dt-bindings/clock/qcom,gcc-msm8998.h
+++ b/include/dt-bindings/clock/qcom,gcc-msm8998.h
@@ -184,6 +184,7 @@
#define GCC_MSS_MNOC_BIMC_AXI_CLK 175
#define GCC_BIMC_GFX_CLK 176
#define UFS_UNIPRO_CORE_CLK_SRC 177
+#define GCC_MMSS_GPLL0_CLK 178
#define PCIE_0_GDSC 0
#define UFS_GDSC 1
--
2.29.2
next prev parent reply other threads:[~2021-01-09 13:55 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-09 13:46 [PATCH 0/9] Clock fixes for MSM8998 GCC, MMCC, GPUCC AngeloGioacchino Del Regno
2021-01-09 13:46 ` AngeloGioacchino Del Regno [this message]
2021-01-14 19:07 ` [PATCH 1/9] clk: qcom: gcc-msm8998: Wire up gcc_mmss_gpll0 clock Rob Herring
2021-01-14 21:44 ` AngeloGioacchino Del Regno
2021-01-14 22:12 ` Jeffrey Hugo
2021-01-14 22:13 ` AngeloGioacchino Del Regno
2021-01-14 22:33 ` Jeffrey Hugo
2021-01-14 22:40 ` AngeloGioacchino Del Regno
2021-01-14 22:44 ` Jeffrey Hugo
2021-01-14 22:49 ` AngeloGioacchino Del Regno
2021-01-09 13:46 ` [PATCH 2/9] clk: qcom: gcc-msm8998: Add missing hmss_gpll0_clk_src clock AngeloGioacchino Del Regno
2021-01-09 13:46 ` [PATCH 3/9] clk: qcom: gcc-msm8998: Mark gpu_cfg_ahb_clk as critical AngeloGioacchino Del Regno
2021-01-09 13:46 ` [PATCH 4/9] clk: qcom: gcc-msm8998: Fix Alpha PLL type for all GPLLs AngeloGioacchino Del Regno
2021-01-09 13:46 ` [PATCH 5/9] clk: qcom: mmcc-msm8998: Set CLK_GET_RATE_NOCACHE to pixel/byte clks AngeloGioacchino Del Regno
2021-01-09 13:46 ` [PATCH 6/9] clk: qcom: mmcc-msm8998: Add hardware clockgating registers to some clks AngeloGioacchino Del Regno
2021-01-09 13:46 ` [PATCH 7/9] clk: qcom: mmcc-msm8998: Set bimc_smmu_gdsc always on AngeloGioacchino Del Regno
2021-01-09 13:46 ` [PATCH 8/9] clk: qcom: gpucc-msm8998: Add resets, cxc, fix flags on gpu_gx_gdsc AngeloGioacchino Del Regno
2021-01-09 13:46 ` [PATCH 9/9] clk: qcom: gpucc-msm8998: Allow fabia gpupll0 rate setting AngeloGioacchino Del Regno
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210109134617.146275-2-angelogioacchino.delregno@somainline.org \
--to=angelogioacchino.delregno@somainline.org \
--cc=agross@kernel.org \
--cc=bjorn.andersson@linaro.org \
--cc=devicetree@vger.kernel.org \
--cc=konrad.dybcio@somainline.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=marijn.suijten@somainline.org \
--cc=martin.botka@somainline.org \
--cc=mturquette@baylibre.com \
--cc=phone-devel@vger.kernel.org \
--cc=robh+dt@kernel.org \
--cc=sboyd@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).