* [PATCH v2 0/2] clk: renesas: r8a779a0: Add clocks to support thermal
@ 2021-03-09 16:14 Niklas Söderlund
2021-03-09 16:14 ` [PATCH v2 1/2] clk: renesas: r8a779a0: Add CL16M clock Niklas Söderlund
2021-03-09 16:14 ` [PATCH v2 2/2] clk: renesas: r8a779a0: Add TSC clock Niklas Söderlund
0 siblings, 2 replies; 6+ messages in thread
From: Niklas Söderlund @ 2021-03-09 16:14 UTC (permalink / raw)
To: Geert Uytterhoeven, linux-clk; +Cc: linux-renesas-soc, Niklas Söderlund
Hello,
This series aims to add enough clocks to enable proper operation of the
thermal IP block for V3U. The series have been tested on target together
with other thermal enablement patches to prove operation of thermal.
Based and tested on-top of v5.12-rc2.
Niklas Söderlund (2):
clk: renesas: r8a779a0: Add CL16M clock
clk: renesas: r8a779a0: Add TSC clock
drivers/clk/renesas/r8a779a0-cpg-mssr.c | 3 +++
include/dt-bindings/clock/r8a779a0-cpg-mssr.h | 1 +
2 files changed, 4 insertions(+)
--
2.30.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 1/2] clk: renesas: r8a779a0: Add CL16M clock
2021-03-09 16:14 [PATCH v2 0/2] clk: renesas: r8a779a0: Add clocks to support thermal Niklas Söderlund
@ 2021-03-09 16:14 ` Niklas Söderlund
2021-03-09 16:31 ` Geert Uytterhoeven
2021-03-09 16:14 ` [PATCH v2 2/2] clk: renesas: r8a779a0: Add TSC clock Niklas Söderlund
1 sibling, 1 reply; 6+ messages in thread
From: Niklas Söderlund @ 2021-03-09 16:14 UTC (permalink / raw)
To: Geert Uytterhoeven, linux-clk; +Cc: linux-renesas-soc, Niklas Söderlund
Implement support for the CL16M clock on V3U.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
---
drivers/clk/renesas/r8a779a0-cpg-mssr.c | 2 ++
include/dt-bindings/clock/r8a779a0-cpg-mssr.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
index f23fe9d5e5e1c7a3..52452eff1fbed169 100644
--- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
@@ -147,6 +147,8 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
DEF_SD("sd0", R8A779A0_CLK_SD0, CLK_SDSRC, 0x870),
+ DEF_FIXED("cl16m", R8A779A0_CLK_CL16M, CLK_PLL1_DIV2, 64, 1),
+
DEF_DIV6P1("mso", R8A779A0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, 0x878),
DEF_DIV6P1("csi0", R8A779A0_CLK_CSI0, CLK_PLL5_DIV4, 0x880),
diff --git a/include/dt-bindings/clock/r8a779a0-cpg-mssr.h b/include/dt-bindings/clock/r8a779a0-cpg-mssr.h
index f1d737ca7ca1a7ca..2974dc6035f7b936 100644
--- a/include/dt-bindings/clock/r8a779a0-cpg-mssr.h
+++ b/include/dt-bindings/clock/r8a779a0-cpg-mssr.h
@@ -51,5 +51,6 @@
#define R8A779A0_CLK_CBFUSA 40
#define R8A779A0_CLK_R 41
#define R8A779A0_CLK_OSC 42
+#define R8A779A0_CLK_CL16M 43
#endif /* __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ */
--
2.30.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 2/2] clk: renesas: r8a779a0: Add TSC clock
2021-03-09 16:14 [PATCH v2 0/2] clk: renesas: r8a779a0: Add clocks to support thermal Niklas Söderlund
2021-03-09 16:14 ` [PATCH v2 1/2] clk: renesas: r8a779a0: Add CL16M clock Niklas Söderlund
@ 2021-03-09 16:14 ` Niklas Söderlund
2021-03-09 16:37 ` Geert Uytterhoeven
1 sibling, 1 reply; 6+ messages in thread
From: Niklas Söderlund @ 2021-03-09 16:14 UTC (permalink / raw)
To: Geert Uytterhoeven, linux-clk; +Cc: linux-renesas-soc, Niklas Söderlund
Implement support for the TSC clock on V3U.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
---
drivers/clk/renesas/r8a779a0-cpg-mssr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
index 52452eff1fbed169..7d8fe3644e8bd3af 100644
--- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
@@ -233,6 +233,7 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
DEF_MOD("pfc1", 916, R8A779A0_CLK_CP),
DEF_MOD("pfc2", 917, R8A779A0_CLK_CP),
DEF_MOD("pfc3", 918, R8A779A0_CLK_CP),
+ DEF_MOD("tsc", 919, R8A779A0_CLK_CL16M),
DEF_MOD("vspx0", 1028, R8A779A0_CLK_S1D1),
DEF_MOD("vspx1", 1029, R8A779A0_CLK_S1D1),
DEF_MOD("vspx2", 1030, R8A779A0_CLK_S1D1),
--
2.30.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2 1/2] clk: renesas: r8a779a0: Add CL16M clock
2021-03-09 16:14 ` [PATCH v2 1/2] clk: renesas: r8a779a0: Add CL16M clock Niklas Söderlund
@ 2021-03-09 16:31 ` Geert Uytterhoeven
2021-03-09 16:48 ` Niklas Söderlund
0 siblings, 1 reply; 6+ messages in thread
From: Geert Uytterhoeven @ 2021-03-09 16:31 UTC (permalink / raw)
To: Niklas Söderlund; +Cc: linux-clk, Linux-Renesas
Hi Niklas,
On Tue, Mar 9, 2021 at 5:14 PM Niklas Söderlund
<niklas.soderlund+renesas@ragnatech.se> wrote:
> Implement support for the CL16M clock on V3U.
>
> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Thanks for your patch!
> --- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
> @@ -147,6 +147,8 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
>
> DEF_SD("sd0", R8A779A0_CLK_SD0, CLK_SDSRC, 0x870),
>
> + DEF_FIXED("cl16m", R8A779A0_CLK_CL16M, CLK_PLL1_DIV2, 64, 1),
Is this any different from the "cl16mck" added by Wolfram, and
already present in renesas-clk?
> +
> DEF_DIV6P1("mso", R8A779A0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
> DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, 0x878),
> DEF_DIV6P1("csi0", R8A779A0_CLK_CSI0, CLK_PLL5_DIV4, 0x880),
> diff --git a/include/dt-bindings/clock/r8a779a0-cpg-mssr.h b/include/dt-bindings/clock/r8a779a0-cpg-mssr.h
> index f1d737ca7ca1a7ca..2974dc6035f7b936 100644
> --- a/include/dt-bindings/clock/r8a779a0-cpg-mssr.h
> +++ b/include/dt-bindings/clock/r8a779a0-cpg-mssr.h
> @@ -51,5 +51,6 @@
> #define R8A779A0_CLK_CBFUSA 40
> #define R8A779A0_CLK_R 41
> #define R8A779A0_CLK_OSC 42
> +#define R8A779A0_CLK_CL16M 43
We already have R8A779A0_CLK_CL16MCK?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2 2/2] clk: renesas: r8a779a0: Add TSC clock
2021-03-09 16:14 ` [PATCH v2 2/2] clk: renesas: r8a779a0: Add TSC clock Niklas Söderlund
@ 2021-03-09 16:37 ` Geert Uytterhoeven
0 siblings, 0 replies; 6+ messages in thread
From: Geert Uytterhoeven @ 2021-03-09 16:37 UTC (permalink / raw)
To: Niklas Söderlund; +Cc: linux-clk, Linux-Renesas
Hi Niklas,
On Tue, Mar 9, 2021 at 5:14 PM Niklas Söderlund
<niklas.soderlund+renesas@ragnatech.se> wrote:
> Implement support for the TSC clock on V3U.
>
> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Thanks for your patch!
> --- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
> @@ -233,6 +233,7 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
> DEF_MOD("pfc1", 916, R8A779A0_CLK_CP),
> DEF_MOD("pfc2", 917, R8A779A0_CLK_CP),
> DEF_MOD("pfc3", 918, R8A779A0_CLK_CP),
> + DEF_MOD("tsc", 919, R8A779A0_CLK_CL16M),
R8A779A0_CLK_CL16MCK?
> DEF_MOD("vspx0", 1028, R8A779A0_CLK_S1D1),
> DEF_MOD("vspx1", 1029, R8A779A0_CLK_S1D1),
> DEF_MOD("vspx2", 1030, R8A779A0_CLK_S1D1),
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2 1/2] clk: renesas: r8a779a0: Add CL16M clock
2021-03-09 16:31 ` Geert Uytterhoeven
@ 2021-03-09 16:48 ` Niklas Söderlund
0 siblings, 0 replies; 6+ messages in thread
From: Niklas Söderlund @ 2021-03-09 16:48 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: linux-clk, Linux-Renesas
Hi Geert,
Thanks for your feedback.
On 2021-03-09 17:31:09 +0100, Geert Uytterhoeven wrote:
> Hi Niklas,
>
> On Tue, Mar 9, 2021 at 5:14 PM Niklas Söderlund
> <niklas.soderlund+renesas@ragnatech.se> wrote:
> > Implement support for the CL16M clock on V3U.
> >
> > Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
>
> Thanks for your patch!
>
> > --- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
> > +++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
> > @@ -147,6 +147,8 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
> >
> > DEF_SD("sd0", R8A779A0_CLK_SD0, CLK_SDSRC, 0x870),
> >
> > + DEF_FIXED("cl16m", R8A779A0_CLK_CL16M, CLK_PLL1_DIV2, 64, 1),
>
> Is this any different from the "cl16mck" added by Wolfram, and
> already present in renesas-clk?
No they are the same and as I see Wolfram's "cl16mck" name is now in
your tree I will switch to it. Will post a v3 of 2/2 which uses it and
drop this patch.
>
> > +
> > DEF_DIV6P1("mso", R8A779A0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
> > DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, 0x878),
> > DEF_DIV6P1("csi0", R8A779A0_CLK_CSI0, CLK_PLL5_DIV4, 0x880),
> > diff --git a/include/dt-bindings/clock/r8a779a0-cpg-mssr.h b/include/dt-bindings/clock/r8a779a0-cpg-mssr.h
> > index f1d737ca7ca1a7ca..2974dc6035f7b936 100644
> > --- a/include/dt-bindings/clock/r8a779a0-cpg-mssr.h
> > +++ b/include/dt-bindings/clock/r8a779a0-cpg-mssr.h
> > @@ -51,5 +51,6 @@
> > #define R8A779A0_CLK_CBFUSA 40
> > #define R8A779A0_CLK_R 41
> > #define R8A779A0_CLK_OSC 42
> > +#define R8A779A0_CLK_CL16M 43
>
> We already have R8A779A0_CLK_CL16MCK?
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
--
Regards,
Niklas Söderlund
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-03-09 16:49 UTC | newest]
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2021-03-09 16:14 [PATCH v2 0/2] clk: renesas: r8a779a0: Add clocks to support thermal Niklas Söderlund
2021-03-09 16:14 ` [PATCH v2 1/2] clk: renesas: r8a779a0: Add CL16M clock Niklas Söderlund
2021-03-09 16:31 ` Geert Uytterhoeven
2021-03-09 16:48 ` Niklas Söderlund
2021-03-09 16:14 ` [PATCH v2 2/2] clk: renesas: r8a779a0: Add TSC clock Niklas Söderlund
2021-03-09 16:37 ` Geert Uytterhoeven
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