* [PATCH 00/18] clk: meson: move all private clk IDs to public dt-bindings headers
@ 2023-06-07 10:56 Neil Armstrong
2023-06-07 10:56 ` [PATCH 02/18] clk: meson: migrate meson-aoclk out of hw_onecell_data to drop NR_CLKS Neil Armstrong
` (16 more replies)
0 siblings, 17 replies; 35+ messages in thread
From: Neil Armstrong @ 2023-06-07 10:56 UTC (permalink / raw)
To: Jerome Brunet, Michael Turquette, Stephen Boyd, Kevin Hilman,
Martin Blumenstingl, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-amlogic, linux-clk, linux-arm-kernel, linux-kernel,
devicetree, Neil Armstrong
After some complaints in the upstreaming of the A1 clock drivers,
S4 clock driver and a tentative to use some of the private DSI
clocks in [1], it has been decided to move out all the "private"
clk IDs to public dt-bindings headers.
For that we must get rid of the "NR_CLKS" define and use
ARRAY_SIZE() to get the count of hw_clks, then we can move
the IDs and do some cleanup.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
Neil Armstrong (18):
clk: meson: migrate meson-eeclk out of hw_onecell_data to drop NR_CLKS
clk: meson: migrate meson-aoclk out of hw_onecell_data to drop NR_CLKS
clk: meson: migrate a1 clock drivers out of hw_onecell_data to drop NR_CLKS
clk: meson: migrate meson8b out of hw_onecell_data to drop NR_CLKS
clk: meson: migrate axg-audio out of hw_onecell_data to drop NR_CLKS
dt-bindings: clk: gxbb-clkc: expose all clock ids
dt-bindings: clk: axg-clkc: expose all clock ids
dt-bindings: clk: g12a-clks: expose all clock ids
dt-bindings: clk: g12a-aoclkc: expose all clock ids
dt-bindings: clk: meson8b-clkc: expose all clock ids
dt-bindings: clk: amlogic,a1-peripherals-clkc: expose all clock ids
dt-bindings: clk: amlogic,a1-pll-clkc: expose all clock ids
dt-bindings: clk: axg-audio-clkc: expose all clock ids
clk: meson: aoclk: move bindings include to main driver
clk: meson: eeclk: move bindings include to main driver
clk: meson: a1: move bindings include to main driver
clk: meson: meson8b: move bindings include to main driver
clk: meson: axg-audio: move bindings include to main driver
drivers/clk/meson/a1-peripherals.c | 345 ++---
drivers/clk/meson/a1-peripherals.h | 67 -
drivers/clk/meson/a1-pll.c | 59 +-
drivers/clk/meson/a1-pll.h | 19 -
drivers/clk/meson/axg-aoclk.c | 46 +-
drivers/clk/meson/axg-aoclk.h | 18 -
drivers/clk/meson/axg-audio.c | 858 +++++------
drivers/clk/meson/axg-audio.h | 75 -
drivers/clk/meson/axg.c | 283 ++--
drivers/clk/meson/axg.h | 63 -
drivers/clk/meson/g12a-aoclk.c | 70 +-
drivers/clk/meson/g12a-aoclk.h | 32 -
drivers/clk/meson/g12a.c | 1483 ++++++++++----------
drivers/clk/meson/g12a.h | 145 --
drivers/clk/meson/gxbb-aoclk.c | 12 +-
drivers/clk/meson/gxbb-aoclk.h | 15 -
drivers/clk/meson/gxbb.c | 844 ++++++-----
drivers/clk/meson/gxbb.h | 81 --
drivers/clk/meson/meson-aoclk.c | 22 +-
drivers/clk/meson/meson-aoclk.h | 3 +-
drivers/clk/meson/meson-eeclk.c | 22 +-
drivers/clk/meson/meson-eeclk.h | 3 +-
drivers/clk/meson/meson8b.c | 1335 +++++++++---------
drivers/clk/meson/meson8b.h | 117 --
.../clock/amlogic,a1-peripherals-clkc.h | 53 +
include/dt-bindings/clock/amlogic,a1-pll-clkc.h | 5 +
include/dt-bindings/clock/axg-audio-clkc.h | 65 +
include/dt-bindings/clock/axg-clkc.h | 48 +
include/dt-bindings/clock/g12a-aoclkc.h | 7 +
include/dt-bindings/clock/g12a-clkc.h | 130 ++
include/dt-bindings/clock/gxbb-clkc.h | 65 +
include/dt-bindings/clock/meson8b-clkc.h | 97 ++
32 files changed, 3205 insertions(+), 3282 deletions(-)
---
base-commit: 84af914404dbc01f388c440cac72428784b8a161
change-id: 20230607-topic-amlogic-upstream-clkid-public-migration-fc1c67c44858
Best regards,
--
Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH 02/18] clk: meson: migrate meson-aoclk out of hw_onecell_data to drop NR_CLKS
2023-06-07 10:56 [PATCH 00/18] clk: meson: move all private clk IDs to public dt-bindings headers Neil Armstrong
@ 2023-06-07 10:56 ` Neil Armstrong
2023-06-07 10:56 ` [PATCH 03/18] clk: meson: migrate a1 clock drivers " Neil Armstrong
` (15 subsequent siblings)
16 siblings, 0 replies; 35+ messages in thread
From: Neil Armstrong @ 2023-06-07 10:56 UTC (permalink / raw)
To: Jerome Brunet, Michael Turquette, Stephen Boyd, Kevin Hilman,
Martin Blumenstingl, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-amlogic, linux-clk, linux-arm-kernel, linux-kernel,
devicetree, Neil Armstrong
The way hw_onecell_data is declared:
struct clk_hw_onecell_data {
unsigned int num;
struct clk_hw *hws[];
};
makes it impossible to have the clk_hw table declared outside while
using ARRAY_SIZE() to determine ".num" due to ".hws" being a flexible
array member.
Completely move out of hw_onecell_data and add a custom
devm_of_clk_add_hw_provider() "get" callback to retrieve the clk_hw
from the meson_aoclk_data struct to finally get rid on the
NR_CLKS define.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
drivers/clk/meson/axg-aoclk.c | 42 +++++++++++++-------------
drivers/clk/meson/axg-aoclk.h | 2 --
drivers/clk/meson/g12a-aoclk.c | 66 ++++++++++++++++++++---------------------
drivers/clk/meson/g12a-aoclk.h | 2 --
drivers/clk/meson/gxbb-aoclk.c | 8 ++---
drivers/clk/meson/gxbb-aoclk.h | 2 --
drivers/clk/meson/meson-aoclk.c | 22 ++++++++++----
drivers/clk/meson/meson-aoclk.h | 3 +-
8 files changed, 74 insertions(+), 73 deletions(-)
diff --git a/drivers/clk/meson/axg-aoclk.c b/drivers/clk/meson/axg-aoclk.c
index af6db437bcd8..db5b53146bcc 100644
--- a/drivers/clk/meson/axg-aoclk.c
+++ b/drivers/clk/meson/axg-aoclk.c
@@ -288,27 +288,24 @@ static struct clk_regmap *axg_aoclk_regmap[] = {
&axg_aoclk_saradc_gate,
};
-static const struct clk_hw_onecell_data axg_aoclk_onecell_data = {
- .hws = {
- [CLKID_AO_REMOTE] = &axg_aoclk_remote.hw,
- [CLKID_AO_I2C_MASTER] = &axg_aoclk_i2c_master.hw,
- [CLKID_AO_I2C_SLAVE] = &axg_aoclk_i2c_slave.hw,
- [CLKID_AO_UART1] = &axg_aoclk_uart1.hw,
- [CLKID_AO_UART2] = &axg_aoclk_uart2.hw,
- [CLKID_AO_IR_BLASTER] = &axg_aoclk_ir_blaster.hw,
- [CLKID_AO_SAR_ADC] = &axg_aoclk_saradc.hw,
- [CLKID_AO_CLK81] = &axg_aoclk_clk81.hw,
- [CLKID_AO_SAR_ADC_SEL] = &axg_aoclk_saradc_mux.hw,
- [CLKID_AO_SAR_ADC_DIV] = &axg_aoclk_saradc_div.hw,
- [CLKID_AO_SAR_ADC_CLK] = &axg_aoclk_saradc_gate.hw,
- [CLKID_AO_CTS_OSCIN] = &axg_aoclk_cts_oscin.hw,
- [CLKID_AO_32K_PRE] = &axg_aoclk_32k_pre.hw,
- [CLKID_AO_32K_DIV] = &axg_aoclk_32k_div.hw,
- [CLKID_AO_32K_SEL] = &axg_aoclk_32k_sel.hw,
- [CLKID_AO_32K] = &axg_aoclk_32k.hw,
- [CLKID_AO_CTS_RTC_OSCIN] = &axg_aoclk_cts_rtc_oscin.hw,
- },
- .num = NR_CLKS,
+static struct clk_hw *axg_aoclk_hw_clks[] = {
+ [CLKID_AO_REMOTE] = &axg_aoclk_remote.hw,
+ [CLKID_AO_I2C_MASTER] = &axg_aoclk_i2c_master.hw,
+ [CLKID_AO_I2C_SLAVE] = &axg_aoclk_i2c_slave.hw,
+ [CLKID_AO_UART1] = &axg_aoclk_uart1.hw,
+ [CLKID_AO_UART2] = &axg_aoclk_uart2.hw,
+ [CLKID_AO_IR_BLASTER] = &axg_aoclk_ir_blaster.hw,
+ [CLKID_AO_SAR_ADC] = &axg_aoclk_saradc.hw,
+ [CLKID_AO_CLK81] = &axg_aoclk_clk81.hw,
+ [CLKID_AO_SAR_ADC_SEL] = &axg_aoclk_saradc_mux.hw,
+ [CLKID_AO_SAR_ADC_DIV] = &axg_aoclk_saradc_div.hw,
+ [CLKID_AO_SAR_ADC_CLK] = &axg_aoclk_saradc_gate.hw,
+ [CLKID_AO_CTS_OSCIN] = &axg_aoclk_cts_oscin.hw,
+ [CLKID_AO_32K_PRE] = &axg_aoclk_32k_pre.hw,
+ [CLKID_AO_32K_DIV] = &axg_aoclk_32k_div.hw,
+ [CLKID_AO_32K_SEL] = &axg_aoclk_32k_sel.hw,
+ [CLKID_AO_32K] = &axg_aoclk_32k.hw,
+ [CLKID_AO_CTS_RTC_OSCIN] = &axg_aoclk_cts_rtc_oscin.hw,
};
static const struct meson_aoclk_data axg_aoclkc_data = {
@@ -317,7 +314,8 @@ static const struct meson_aoclk_data axg_aoclkc_data = {
.reset = axg_aoclk_reset,
.num_clks = ARRAY_SIZE(axg_aoclk_regmap),
.clks = axg_aoclk_regmap,
- .hw_data = &axg_aoclk_onecell_data,
+ .hw_clks = axg_aoclk_hw_clks,
+ .hw_clk_num = ARRAY_SIZE(axg_aoclk_hw_clks),
};
static const struct of_device_id axg_aoclkc_match_table[] = {
diff --git a/drivers/clk/meson/axg-aoclk.h b/drivers/clk/meson/axg-aoclk.h
index 3cc27e85170f..fe23dc53aa73 100644
--- a/drivers/clk/meson/axg-aoclk.h
+++ b/drivers/clk/meson/axg-aoclk.h
@@ -10,8 +10,6 @@
#ifndef __AXG_AOCLKC_H
#define __AXG_AOCLKC_H
-#define NR_CLKS 17
-
#include <dt-bindings/clock/axg-aoclkc.h>
#include <dt-bindings/reset/axg-aoclkc.h>
diff --git a/drivers/clk/meson/g12a-aoclk.c b/drivers/clk/meson/g12a-aoclk.c
index b52990e574d2..52501ec709f7 100644
--- a/drivers/clk/meson/g12a-aoclk.c
+++ b/drivers/clk/meson/g12a-aoclk.c
@@ -411,39 +411,36 @@ static struct clk_regmap *g12a_aoclk_regmap[] = {
&g12a_aoclk_saradc_gate,
};
-static const struct clk_hw_onecell_data g12a_aoclk_onecell_data = {
- .hws = {
- [CLKID_AO_AHB] = &g12a_aoclk_ahb.hw,
- [CLKID_AO_IR_IN] = &g12a_aoclk_ir_in.hw,
- [CLKID_AO_I2C_M0] = &g12a_aoclk_i2c_m0.hw,
- [CLKID_AO_I2C_S0] = &g12a_aoclk_i2c_s0.hw,
- [CLKID_AO_UART] = &g12a_aoclk_uart.hw,
- [CLKID_AO_PROD_I2C] = &g12a_aoclk_prod_i2c.hw,
- [CLKID_AO_UART2] = &g12a_aoclk_uart2.hw,
- [CLKID_AO_IR_OUT] = &g12a_aoclk_ir_out.hw,
- [CLKID_AO_SAR_ADC] = &g12a_aoclk_saradc.hw,
- [CLKID_AO_MAILBOX] = &g12a_aoclk_mailbox.hw,
- [CLKID_AO_M3] = &g12a_aoclk_m3.hw,
- [CLKID_AO_AHB_SRAM] = &g12a_aoclk_ahb_sram.hw,
- [CLKID_AO_RTI] = &g12a_aoclk_rti.hw,
- [CLKID_AO_M4_FCLK] = &g12a_aoclk_m4_fclk.hw,
- [CLKID_AO_M4_HCLK] = &g12a_aoclk_m4_hclk.hw,
- [CLKID_AO_CLK81] = &g12a_aoclk_clk81.hw,
- [CLKID_AO_SAR_ADC_SEL] = &g12a_aoclk_saradc_mux.hw,
- [CLKID_AO_SAR_ADC_DIV] = &g12a_aoclk_saradc_div.hw,
- [CLKID_AO_SAR_ADC_CLK] = &g12a_aoclk_saradc_gate.hw,
- [CLKID_AO_CTS_OSCIN] = &g12a_aoclk_cts_oscin.hw,
- [CLKID_AO_32K_PRE] = &g12a_aoclk_32k_by_oscin_pre.hw,
- [CLKID_AO_32K_DIV] = &g12a_aoclk_32k_by_oscin_div.hw,
- [CLKID_AO_32K_SEL] = &g12a_aoclk_32k_by_oscin_sel.hw,
- [CLKID_AO_32K] = &g12a_aoclk_32k_by_oscin.hw,
- [CLKID_AO_CEC_PRE] = &g12a_aoclk_cec_pre.hw,
- [CLKID_AO_CEC_DIV] = &g12a_aoclk_cec_div.hw,
- [CLKID_AO_CEC_SEL] = &g12a_aoclk_cec_sel.hw,
- [CLKID_AO_CEC] = &g12a_aoclk_cec.hw,
- [CLKID_AO_CTS_RTC_OSCIN] = &g12a_aoclk_cts_rtc_oscin.hw,
- },
- .num = NR_CLKS,
+static struct clk_hw *g12a_aoclk_hw_clks[] = {
+ [CLKID_AO_AHB] = &g12a_aoclk_ahb.hw,
+ [CLKID_AO_IR_IN] = &g12a_aoclk_ir_in.hw,
+ [CLKID_AO_I2C_M0] = &g12a_aoclk_i2c_m0.hw,
+ [CLKID_AO_I2C_S0] = &g12a_aoclk_i2c_s0.hw,
+ [CLKID_AO_UART] = &g12a_aoclk_uart.hw,
+ [CLKID_AO_PROD_I2C] = &g12a_aoclk_prod_i2c.hw,
+ [CLKID_AO_UART2] = &g12a_aoclk_uart2.hw,
+ [CLKID_AO_IR_OUT] = &g12a_aoclk_ir_out.hw,
+ [CLKID_AO_SAR_ADC] = &g12a_aoclk_saradc.hw,
+ [CLKID_AO_MAILBOX] = &g12a_aoclk_mailbox.hw,
+ [CLKID_AO_M3] = &g12a_aoclk_m3.hw,
+ [CLKID_AO_AHB_SRAM] = &g12a_aoclk_ahb_sram.hw,
+ [CLKID_AO_RTI] = &g12a_aoclk_rti.hw,
+ [CLKID_AO_M4_FCLK] = &g12a_aoclk_m4_fclk.hw,
+ [CLKID_AO_M4_HCLK] = &g12a_aoclk_m4_hclk.hw,
+ [CLKID_AO_CLK81] = &g12a_aoclk_clk81.hw,
+ [CLKID_AO_SAR_ADC_SEL] = &g12a_aoclk_saradc_mux.hw,
+ [CLKID_AO_SAR_ADC_DIV] = &g12a_aoclk_saradc_div.hw,
+ [CLKID_AO_SAR_ADC_CLK] = &g12a_aoclk_saradc_gate.hw,
+ [CLKID_AO_CTS_OSCIN] = &g12a_aoclk_cts_oscin.hw,
+ [CLKID_AO_32K_PRE] = &g12a_aoclk_32k_by_oscin_pre.hw,
+ [CLKID_AO_32K_DIV] = &g12a_aoclk_32k_by_oscin_div.hw,
+ [CLKID_AO_32K_SEL] = &g12a_aoclk_32k_by_oscin_sel.hw,
+ [CLKID_AO_32K] = &g12a_aoclk_32k_by_oscin.hw,
+ [CLKID_AO_CEC_PRE] = &g12a_aoclk_cec_pre.hw,
+ [CLKID_AO_CEC_DIV] = &g12a_aoclk_cec_div.hw,
+ [CLKID_AO_CEC_SEL] = &g12a_aoclk_cec_sel.hw,
+ [CLKID_AO_CEC] = &g12a_aoclk_cec.hw,
+ [CLKID_AO_CTS_RTC_OSCIN] = &g12a_aoclk_cts_rtc_oscin.hw,
};
static const struct meson_aoclk_data g12a_aoclkc_data = {
@@ -452,7 +449,8 @@ static const struct meson_aoclk_data g12a_aoclkc_data = {
.reset = g12a_aoclk_reset,
.num_clks = ARRAY_SIZE(g12a_aoclk_regmap),
.clks = g12a_aoclk_regmap,
- .hw_data = &g12a_aoclk_onecell_data,
+ .hw_clks = g12a_aoclk_hw_clks,
+ .hw_clk_num = ARRAY_SIZE(g12a_aoclk_hw_clks),
};
static const struct of_device_id g12a_aoclkc_match_table[] = {
diff --git a/drivers/clk/meson/g12a-aoclk.h b/drivers/clk/meson/g12a-aoclk.h
index a67c8a7cd7c4..077bd25b94a1 100644
--- a/drivers/clk/meson/g12a-aoclk.h
+++ b/drivers/clk/meson/g12a-aoclk.h
@@ -24,8 +24,6 @@
#define CLKID_AO_CEC_DIV 25
#define CLKID_AO_CEC_SEL 26
-#define NR_CLKS 29
-
#include <dt-bindings/clock/g12a-aoclkc.h>
#include <dt-bindings/reset/g12a-aoclkc.h>
diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c
index fce95cf89836..b08f60f5a73d 100644
--- a/drivers/clk/meson/gxbb-aoclk.c
+++ b/drivers/clk/meson/gxbb-aoclk.c
@@ -252,8 +252,7 @@ static struct clk_regmap *gxbb_aoclk[] = {
&ao_cts_cec,
};
-static const struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
- .hws = {
+static struct clk_hw *gxbb_aoclk_hw_clks[] = {
[CLKID_AO_REMOTE] = &remote_ao.hw,
[CLKID_AO_I2C_MASTER] = &i2c_master_ao.hw,
[CLKID_AO_I2C_SLAVE] = &i2c_slave_ao.hw,
@@ -268,8 +267,6 @@ static const struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
[CLKID_AO_32K] = &ao_32k.hw,
[CLKID_AO_CTS_RTC_OSCIN] = &ao_cts_rtc_oscin.hw,
[CLKID_AO_CLK81] = &ao_clk81.hw,
- },
- .num = NR_CLKS,
};
static const struct meson_aoclk_data gxbb_aoclkc_data = {
@@ -278,7 +275,8 @@ static const struct meson_aoclk_data gxbb_aoclkc_data = {
.reset = gxbb_aoclk_reset,
.num_clks = ARRAY_SIZE(gxbb_aoclk),
.clks = gxbb_aoclk,
- .hw_data = &gxbb_aoclk_onecell_data,
+ .hw_clks = gxbb_aoclk_hw_clks,
+ .hw_clk_num = ARRAY_SIZE(gxbb_aoclk_hw_clks),
};
static const struct of_device_id gxbb_aoclkc_match_table[] = {
diff --git a/drivers/clk/meson/gxbb-aoclk.h b/drivers/clk/meson/gxbb-aoclk.h
index 1db16f9b37d4..94197b957512 100644
--- a/drivers/clk/meson/gxbb-aoclk.h
+++ b/drivers/clk/meson/gxbb-aoclk.h
@@ -7,8 +7,6 @@
#ifndef __GXBB_AOCLKC_H
#define __GXBB_AOCLKC_H
-#define NR_CLKS 14
-
#include <dt-bindings/clock/gxbb-aoclkc.h>
#include <dt-bindings/reset/gxbb-aoclkc.h>
diff --git a/drivers/clk/meson/meson-aoclk.c b/drivers/clk/meson/meson-aoclk.c
index 434cd8f9de82..3515144aaee5 100644
--- a/drivers/clk/meson/meson-aoclk.c
+++ b/drivers/clk/meson/meson-aoclk.c
@@ -33,6 +33,19 @@ static const struct reset_control_ops meson_aoclk_reset_ops = {
.reset = meson_aoclk_do_reset,
};
+static struct clk_hw *meson_aoclkc_hw_get(struct of_phandle_args *clkspec, void *clk_data)
+{
+ const struct meson_aoclk_data *data = clk_data;
+ unsigned int idx = clkspec->args[0];
+
+ if (idx >= data->hw_clk_num) {
+ pr_err("%s: invalid index %u\n", __func__, idx);
+ return ERR_PTR(-EINVAL);
+ }
+
+ return data->hw_clks[idx];
+}
+
int meson_aoclkc_probe(struct platform_device *pdev)
{
struct meson_aoclk_reset_controller *rstc;
@@ -75,19 +88,18 @@ int meson_aoclkc_probe(struct platform_device *pdev)
data->clks[clkid]->map = regmap;
/* Register all clks */
- for (clkid = 0; clkid < data->hw_data->num; clkid++) {
- if (!data->hw_data->hws[clkid])
+ for (clkid = 0; clkid < data->hw_clk_num; clkid++) {
+ if (!data->hw_clks[clkid])
continue;
- ret = devm_clk_hw_register(dev, data->hw_data->hws[clkid]);
+ ret = devm_clk_hw_register(dev, data->hw_clks[clkid]);
if (ret) {
dev_err(dev, "Clock registration failed\n");
return ret;
}
}
- return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
- (void *) data->hw_data);
+ return devm_of_clk_add_hw_provider(dev, meson_aoclkc_hw_get, data);
}
EXPORT_SYMBOL_GPL(meson_aoclkc_probe);
MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/meson/meson-aoclk.h b/drivers/clk/meson/meson-aoclk.h
index 605b43855a69..4b7dda9c997d 100644
--- a/drivers/clk/meson/meson-aoclk.h
+++ b/drivers/clk/meson/meson-aoclk.h
@@ -24,7 +24,8 @@ struct meson_aoclk_data {
const unsigned int *reset;
const int num_clks;
struct clk_regmap **clks;
- const struct clk_hw_onecell_data *hw_data;
+ struct clk_hw **hw_clks;
+ unsigned int hw_clk_num;
};
struct meson_aoclk_reset_controller {
--
2.34.1
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 03/18] clk: meson: migrate a1 clock drivers out of hw_onecell_data to drop NR_CLKS
2023-06-07 10:56 [PATCH 00/18] clk: meson: move all private clk IDs to public dt-bindings headers Neil Armstrong
2023-06-07 10:56 ` [PATCH 02/18] clk: meson: migrate meson-aoclk out of hw_onecell_data to drop NR_CLKS Neil Armstrong
@ 2023-06-07 10:56 ` Neil Armstrong
2023-06-08 12:45 ` Jerome Brunet
2023-06-07 10:56 ` [PATCH 04/18] clk: meson: migrate meson8b " Neil Armstrong
` (14 subsequent siblings)
16 siblings, 1 reply; 35+ messages in thread
From: Neil Armstrong @ 2023-06-07 10:56 UTC (permalink / raw)
To: Jerome Brunet, Michael Turquette, Stephen Boyd, Kevin Hilman,
Martin Blumenstingl, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-amlogic, linux-clk, linux-arm-kernel, linux-kernel,
devicetree, Neil Armstrong
The way hw_onecell_data is declared:
struct clk_hw_onecell_data {
unsigned int num;
struct clk_hw *hws[];
};
makes it impossible to have the clk_hw table declared outside while
using ARRAY_SIZE() to determine ".num" due to ".hws" being a flexible
array member.
Completely move out of hw_onecell_data and add a custom
devm_of_clk_add_hw_provider() "get" callback to retrieve the clk_hw
in order to finally get rid on the NR_CLKS define.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
drivers/clk/meson/a1-peripherals.c | 343 +++++++++++++++++++------------------
drivers/clk/meson/a1-peripherals.h | 1 -
drivers/clk/meson/a1-pll.c | 57 ++++--
drivers/clk/meson/a1-pll.h | 1 -
4 files changed, 219 insertions(+), 183 deletions(-)
diff --git a/drivers/clk/meson/a1-peripherals.c b/drivers/clk/meson/a1-peripherals.c
index b320134fefeb..094246cb5f6c 100644
--- a/drivers/clk/meson/a1-peripherals.c
+++ b/drivers/clk/meson/a1-peripherals.c
@@ -1866,165 +1866,161 @@ static MESON_GATE(rom, AXI_CLK_EN, 11);
static MESON_GATE(prod_i2c, AXI_CLK_EN, 12);
/* Array of all clocks registered by this provider */
-static struct clk_hw_onecell_data a1_periphs_clks = {
- .hws = {
- [CLKID_XTAL_IN] = &xtal_in.hw,
- [CLKID_FIXPLL_IN] = &fixpll_in.hw,
- [CLKID_USB_PHY_IN] = &usb_phy_in.hw,
- [CLKID_USB_CTRL_IN] = &usb_ctrl_in.hw,
- [CLKID_HIFIPLL_IN] = &hifipll_in.hw,
- [CLKID_SYSPLL_IN] = &syspll_in.hw,
- [CLKID_DDS_IN] = &dds_in.hw,
- [CLKID_SYS] = &sys.hw,
- [CLKID_CLKTREE] = &clktree.hw,
- [CLKID_RESET_CTRL] = &reset_ctrl.hw,
- [CLKID_ANALOG_CTRL] = &analog_ctrl.hw,
- [CLKID_PWR_CTRL] = &pwr_ctrl.hw,
- [CLKID_PAD_CTRL] = &pad_ctrl.hw,
- [CLKID_SYS_CTRL] = &sys_ctrl.hw,
- [CLKID_TEMP_SENSOR] = &temp_sensor.hw,
- [CLKID_AM2AXI_DIV] = &am2axi_dev.hw,
- [CLKID_SPICC_B] = &spicc_b.hw,
- [CLKID_SPICC_A] = &spicc_a.hw,
- [CLKID_MSR] = &msr.hw,
- [CLKID_AUDIO] = &audio.hw,
- [CLKID_JTAG_CTRL] = &jtag_ctrl.hw,
- [CLKID_SARADC_EN] = &saradc_en.hw,
- [CLKID_PWM_EF] = &pwm_ef.hw,
- [CLKID_PWM_CD] = &pwm_cd.hw,
- [CLKID_PWM_AB] = &pwm_ab.hw,
- [CLKID_CEC] = &cec.hw,
- [CLKID_I2C_S] = &i2c_s.hw,
- [CLKID_IR_CTRL] = &ir_ctrl.hw,
- [CLKID_I2C_M_D] = &i2c_m_d.hw,
- [CLKID_I2C_M_C] = &i2c_m_c.hw,
- [CLKID_I2C_M_B] = &i2c_m_b.hw,
- [CLKID_I2C_M_A] = &i2c_m_a.hw,
- [CLKID_ACODEC] = &acodec.hw,
- [CLKID_OTP] = &otp.hw,
- [CLKID_SD_EMMC_A] = &sd_emmc_a.hw,
- [CLKID_USB_PHY] = &usb_phy.hw,
- [CLKID_USB_CTRL] = &usb_ctrl.hw,
- [CLKID_SYS_DSPB] = &sys_dspb.hw,
- [CLKID_SYS_DSPA] = &sys_dspa.hw,
- [CLKID_DMA] = &dma.hw,
- [CLKID_IRQ_CTRL] = &irq_ctrl.hw,
- [CLKID_NIC] = &nic.hw,
- [CLKID_GIC] = &gic.hw,
- [CLKID_UART_C] = &uart_c.hw,
- [CLKID_UART_B] = &uart_b.hw,
- [CLKID_UART_A] = &uart_a.hw,
- [CLKID_SYS_PSRAM] = &sys_psram.hw,
- [CLKID_RSA] = &rsa.hw,
- [CLKID_CORESIGHT] = &coresight.hw,
- [CLKID_AM2AXI_VAD] = &am2axi_vad.hw,
- [CLKID_AUDIO_VAD] = &audio_vad.hw,
- [CLKID_AXI_DMC] = &axi_dmc.hw,
- [CLKID_AXI_PSRAM] = &axi_psram.hw,
- [CLKID_RAMB] = &ramb.hw,
- [CLKID_RAMA] = &rama.hw,
- [CLKID_AXI_SPIFC] = &axi_spifc.hw,
- [CLKID_AXI_NIC] = &axi_nic.hw,
- [CLKID_AXI_DMA] = &axi_dma.hw,
- [CLKID_CPU_CTRL] = &cpu_ctrl.hw,
- [CLKID_ROM] = &rom.hw,
- [CLKID_PROC_I2C] = &prod_i2c.hw,
- [CLKID_DSPA_SEL] = &dspa_sel.hw,
- [CLKID_DSPB_SEL] = &dspb_sel.hw,
- [CLKID_DSPA_EN] = &dspa_en.hw,
- [CLKID_DSPA_EN_NIC] = &dspa_en_nic.hw,
- [CLKID_DSPB_EN] = &dspb_en.hw,
- [CLKID_DSPB_EN_NIC] = &dspb_en_nic.hw,
- [CLKID_RTC] = &rtc.hw,
- [CLKID_CECA_32K] = &ceca_32k_out.hw,
- [CLKID_CECB_32K] = &cecb_32k_out.hw,
- [CLKID_24M] = &clk_24m.hw,
- [CLKID_12M] = &clk_12m.hw,
- [CLKID_FCLK_DIV2_DIVN] = &fclk_div2_divn.hw,
- [CLKID_GEN] = &gen.hw,
- [CLKID_SARADC_SEL] = &saradc_sel.hw,
- [CLKID_SARADC] = &saradc.hw,
- [CLKID_PWM_A] = &pwm_a.hw,
- [CLKID_PWM_B] = &pwm_b.hw,
- [CLKID_PWM_C] = &pwm_c.hw,
- [CLKID_PWM_D] = &pwm_d.hw,
- [CLKID_PWM_E] = &pwm_e.hw,
- [CLKID_PWM_F] = &pwm_f.hw,
- [CLKID_SPICC] = &spicc.hw,
- [CLKID_TS] = &ts.hw,
- [CLKID_SPIFC] = &spifc.hw,
- [CLKID_USB_BUS] = &usb_bus.hw,
- [CLKID_SD_EMMC] = &sd_emmc.hw,
- [CLKID_PSRAM] = &psram.hw,
- [CLKID_DMC] = &dmc.hw,
- [CLKID_SYS_A_SEL] = &sys_a_sel.hw,
- [CLKID_SYS_A_DIV] = &sys_a_div.hw,
- [CLKID_SYS_A] = &sys_a.hw,
- [CLKID_SYS_B_SEL] = &sys_b_sel.hw,
- [CLKID_SYS_B_DIV] = &sys_b_div.hw,
- [CLKID_SYS_B] = &sys_b.hw,
- [CLKID_DSPA_A_SEL] = &dspa_a_sel.hw,
- [CLKID_DSPA_A_DIV] = &dspa_a_div.hw,
- [CLKID_DSPA_A] = &dspa_a.hw,
- [CLKID_DSPA_B_SEL] = &dspa_b_sel.hw,
- [CLKID_DSPA_B_DIV] = &dspa_b_div.hw,
- [CLKID_DSPA_B] = &dspa_b.hw,
- [CLKID_DSPB_A_SEL] = &dspb_a_sel.hw,
- [CLKID_DSPB_A_DIV] = &dspb_a_div.hw,
- [CLKID_DSPB_A] = &dspb_a.hw,
- [CLKID_DSPB_B_SEL] = &dspb_b_sel.hw,
- [CLKID_DSPB_B_DIV] = &dspb_b_div.hw,
- [CLKID_DSPB_B] = &dspb_b.hw,
- [CLKID_RTC_32K_IN] = &rtc_32k_in.hw,
- [CLKID_RTC_32K_DIV] = &rtc_32k_div.hw,
- [CLKID_RTC_32K_XTAL] = &rtc_32k_xtal.hw,
- [CLKID_RTC_32K_SEL] = &rtc_32k_sel.hw,
- [CLKID_CECB_32K_IN] = &cecb_32k_in.hw,
- [CLKID_CECB_32K_DIV] = &cecb_32k_div.hw,
- [CLKID_CECB_32K_SEL_PRE] = &cecb_32k_sel_pre.hw,
- [CLKID_CECB_32K_SEL] = &cecb_32k_sel.hw,
- [CLKID_CECA_32K_IN] = &ceca_32k_in.hw,
- [CLKID_CECA_32K_DIV] = &ceca_32k_div.hw,
- [CLKID_CECA_32K_SEL_PRE] = &ceca_32k_sel_pre.hw,
- [CLKID_CECA_32K_SEL] = &ceca_32k_sel.hw,
- [CLKID_DIV2_PRE] = &fclk_div2_divn_pre.hw,
- [CLKID_24M_DIV2] = &clk_24m_div2.hw,
- [CLKID_GEN_SEL] = &gen_sel.hw,
- [CLKID_GEN_DIV] = &gen_div.hw,
- [CLKID_SARADC_DIV] = &saradc_div.hw,
- [CLKID_PWM_A_SEL] = &pwm_a_sel.hw,
- [CLKID_PWM_A_DIV] = &pwm_a_div.hw,
- [CLKID_PWM_B_SEL] = &pwm_b_sel.hw,
- [CLKID_PWM_B_DIV] = &pwm_b_div.hw,
- [CLKID_PWM_C_SEL] = &pwm_c_sel.hw,
- [CLKID_PWM_C_DIV] = &pwm_c_div.hw,
- [CLKID_PWM_D_SEL] = &pwm_d_sel.hw,
- [CLKID_PWM_D_DIV] = &pwm_d_div.hw,
- [CLKID_PWM_E_SEL] = &pwm_e_sel.hw,
- [CLKID_PWM_E_DIV] = &pwm_e_div.hw,
- [CLKID_PWM_F_SEL] = &pwm_f_sel.hw,
- [CLKID_PWM_F_DIV] = &pwm_f_div.hw,
- [CLKID_SPICC_SEL] = &spicc_sel.hw,
- [CLKID_SPICC_DIV] = &spicc_div.hw,
- [CLKID_SPICC_SEL2] = &spicc_sel2.hw,
- [CLKID_TS_DIV] = &ts_div.hw,
- [CLKID_SPIFC_SEL] = &spifc_sel.hw,
- [CLKID_SPIFC_DIV] = &spifc_div.hw,
- [CLKID_SPIFC_SEL2] = &spifc_sel2.hw,
- [CLKID_USB_BUS_SEL] = &usb_bus_sel.hw,
- [CLKID_USB_BUS_DIV] = &usb_bus_div.hw,
- [CLKID_SD_EMMC_SEL] = &sd_emmc_sel.hw,
- [CLKID_SD_EMMC_DIV] = &sd_emmc_div.hw,
- [CLKID_SD_EMMC_SEL2] = &sd_emmc_sel2.hw,
- [CLKID_PSRAM_SEL] = &psram_sel.hw,
- [CLKID_PSRAM_DIV] = &psram_div.hw,
- [CLKID_PSRAM_SEL2] = &psram_sel2.hw,
- [CLKID_DMC_SEL] = &dmc_sel.hw,
- [CLKID_DMC_DIV] = &dmc_div.hw,
- [CLKID_DMC_SEL2] = &dmc_sel2.hw,
- [NR_CLKS] = NULL,
- },
- .num = NR_CLKS,
+static struct clk_hw *a1_periphs_hw_clks[] = {
+ [CLKID_XTAL_IN] = &xtal_in.hw,
+ [CLKID_FIXPLL_IN] = &fixpll_in.hw,
+ [CLKID_USB_PHY_IN] = &usb_phy_in.hw,
+ [CLKID_USB_CTRL_IN] = &usb_ctrl_in.hw,
+ [CLKID_HIFIPLL_IN] = &hifipll_in.hw,
+ [CLKID_SYSPLL_IN] = &syspll_in.hw,
+ [CLKID_DDS_IN] = &dds_in.hw,
+ [CLKID_SYS] = &sys.hw,
+ [CLKID_CLKTREE] = &clktree.hw,
+ [CLKID_RESET_CTRL] = &reset_ctrl.hw,
+ [CLKID_ANALOG_CTRL] = &analog_ctrl.hw,
+ [CLKID_PWR_CTRL] = &pwr_ctrl.hw,
+ [CLKID_PAD_CTRL] = &pad_ctrl.hw,
+ [CLKID_SYS_CTRL] = &sys_ctrl.hw,
+ [CLKID_TEMP_SENSOR] = &temp_sensor.hw,
+ [CLKID_AM2AXI_DIV] = &am2axi_dev.hw,
+ [CLKID_SPICC_B] = &spicc_b.hw,
+ [CLKID_SPICC_A] = &spicc_a.hw,
+ [CLKID_MSR] = &msr.hw,
+ [CLKID_AUDIO] = &audio.hw,
+ [CLKID_JTAG_CTRL] = &jtag_ctrl.hw,
+ [CLKID_SARADC_EN] = &saradc_en.hw,
+ [CLKID_PWM_EF] = &pwm_ef.hw,
+ [CLKID_PWM_CD] = &pwm_cd.hw,
+ [CLKID_PWM_AB] = &pwm_ab.hw,
+ [CLKID_CEC] = &cec.hw,
+ [CLKID_I2C_S] = &i2c_s.hw,
+ [CLKID_IR_CTRL] = &ir_ctrl.hw,
+ [CLKID_I2C_M_D] = &i2c_m_d.hw,
+ [CLKID_I2C_M_C] = &i2c_m_c.hw,
+ [CLKID_I2C_M_B] = &i2c_m_b.hw,
+ [CLKID_I2C_M_A] = &i2c_m_a.hw,
+ [CLKID_ACODEC] = &acodec.hw,
+ [CLKID_OTP] = &otp.hw,
+ [CLKID_SD_EMMC_A] = &sd_emmc_a.hw,
+ [CLKID_USB_PHY] = &usb_phy.hw,
+ [CLKID_USB_CTRL] = &usb_ctrl.hw,
+ [CLKID_SYS_DSPB] = &sys_dspb.hw,
+ [CLKID_SYS_DSPA] = &sys_dspa.hw,
+ [CLKID_DMA] = &dma.hw,
+ [CLKID_IRQ_CTRL] = &irq_ctrl.hw,
+ [CLKID_NIC] = &nic.hw,
+ [CLKID_GIC] = &gic.hw,
+ [CLKID_UART_C] = &uart_c.hw,
+ [CLKID_UART_B] = &uart_b.hw,
+ [CLKID_UART_A] = &uart_a.hw,
+ [CLKID_SYS_PSRAM] = &sys_psram.hw,
+ [CLKID_RSA] = &rsa.hw,
+ [CLKID_CORESIGHT] = &coresight.hw,
+ [CLKID_AM2AXI_VAD] = &am2axi_vad.hw,
+ [CLKID_AUDIO_VAD] = &audio_vad.hw,
+ [CLKID_AXI_DMC] = &axi_dmc.hw,
+ [CLKID_AXI_PSRAM] = &axi_psram.hw,
+ [CLKID_RAMB] = &ramb.hw,
+ [CLKID_RAMA] = &rama.hw,
+ [CLKID_AXI_SPIFC] = &axi_spifc.hw,
+ [CLKID_AXI_NIC] = &axi_nic.hw,
+ [CLKID_AXI_DMA] = &axi_dma.hw,
+ [CLKID_CPU_CTRL] = &cpu_ctrl.hw,
+ [CLKID_ROM] = &rom.hw,
+ [CLKID_PROC_I2C] = &prod_i2c.hw,
+ [CLKID_DSPA_SEL] = &dspa_sel.hw,
+ [CLKID_DSPB_SEL] = &dspb_sel.hw,
+ [CLKID_DSPA_EN] = &dspa_en.hw,
+ [CLKID_DSPA_EN_NIC] = &dspa_en_nic.hw,
+ [CLKID_DSPB_EN] = &dspb_en.hw,
+ [CLKID_DSPB_EN_NIC] = &dspb_en_nic.hw,
+ [CLKID_RTC] = &rtc.hw,
+ [CLKID_CECA_32K] = &ceca_32k_out.hw,
+ [CLKID_CECB_32K] = &cecb_32k_out.hw,
+ [CLKID_24M] = &clk_24m.hw,
+ [CLKID_12M] = &clk_12m.hw,
+ [CLKID_FCLK_DIV2_DIVN] = &fclk_div2_divn.hw,
+ [CLKID_GEN] = &gen.hw,
+ [CLKID_SARADC_SEL] = &saradc_sel.hw,
+ [CLKID_SARADC] = &saradc.hw,
+ [CLKID_PWM_A] = &pwm_a.hw,
+ [CLKID_PWM_B] = &pwm_b.hw,
+ [CLKID_PWM_C] = &pwm_c.hw,
+ [CLKID_PWM_D] = &pwm_d.hw,
+ [CLKID_PWM_E] = &pwm_e.hw,
+ [CLKID_PWM_F] = &pwm_f.hw,
+ [CLKID_SPICC] = &spicc.hw,
+ [CLKID_TS] = &ts.hw,
+ [CLKID_SPIFC] = &spifc.hw,
+ [CLKID_USB_BUS] = &usb_bus.hw,
+ [CLKID_SD_EMMC] = &sd_emmc.hw,
+ [CLKID_PSRAM] = &psram.hw,
+ [CLKID_DMC] = &dmc.hw,
+ [CLKID_SYS_A_SEL] = &sys_a_sel.hw,
+ [CLKID_SYS_A_DIV] = &sys_a_div.hw,
+ [CLKID_SYS_A] = &sys_a.hw,
+ [CLKID_SYS_B_SEL] = &sys_b_sel.hw,
+ [CLKID_SYS_B_DIV] = &sys_b_div.hw,
+ [CLKID_SYS_B] = &sys_b.hw,
+ [CLKID_DSPA_A_SEL] = &dspa_a_sel.hw,
+ [CLKID_DSPA_A_DIV] = &dspa_a_div.hw,
+ [CLKID_DSPA_A] = &dspa_a.hw,
+ [CLKID_DSPA_B_SEL] = &dspa_b_sel.hw,
+ [CLKID_DSPA_B_DIV] = &dspa_b_div.hw,
+ [CLKID_DSPA_B] = &dspa_b.hw,
+ [CLKID_DSPB_A_SEL] = &dspb_a_sel.hw,
+ [CLKID_DSPB_A_DIV] = &dspb_a_div.hw,
+ [CLKID_DSPB_A] = &dspb_a.hw,
+ [CLKID_DSPB_B_SEL] = &dspb_b_sel.hw,
+ [CLKID_DSPB_B_DIV] = &dspb_b_div.hw,
+ [CLKID_DSPB_B] = &dspb_b.hw,
+ [CLKID_RTC_32K_IN] = &rtc_32k_in.hw,
+ [CLKID_RTC_32K_DIV] = &rtc_32k_div.hw,
+ [CLKID_RTC_32K_XTAL] = &rtc_32k_xtal.hw,
+ [CLKID_RTC_32K_SEL] = &rtc_32k_sel.hw,
+ [CLKID_CECB_32K_IN] = &cecb_32k_in.hw,
+ [CLKID_CECB_32K_DIV] = &cecb_32k_div.hw,
+ [CLKID_CECB_32K_SEL_PRE] = &cecb_32k_sel_pre.hw,
+ [CLKID_CECB_32K_SEL] = &cecb_32k_sel.hw,
+ [CLKID_CECA_32K_IN] = &ceca_32k_in.hw,
+ [CLKID_CECA_32K_DIV] = &ceca_32k_div.hw,
+ [CLKID_CECA_32K_SEL_PRE] = &ceca_32k_sel_pre.hw,
+ [CLKID_CECA_32K_SEL] = &ceca_32k_sel.hw,
+ [CLKID_DIV2_PRE] = &fclk_div2_divn_pre.hw,
+ [CLKID_24M_DIV2] = &clk_24m_div2.hw,
+ [CLKID_GEN_SEL] = &gen_sel.hw,
+ [CLKID_GEN_DIV] = &gen_div.hw,
+ [CLKID_SARADC_DIV] = &saradc_div.hw,
+ [CLKID_PWM_A_SEL] = &pwm_a_sel.hw,
+ [CLKID_PWM_A_DIV] = &pwm_a_div.hw,
+ [CLKID_PWM_B_SEL] = &pwm_b_sel.hw,
+ [CLKID_PWM_B_DIV] = &pwm_b_div.hw,
+ [CLKID_PWM_C_SEL] = &pwm_c_sel.hw,
+ [CLKID_PWM_C_DIV] = &pwm_c_div.hw,
+ [CLKID_PWM_D_SEL] = &pwm_d_sel.hw,
+ [CLKID_PWM_D_DIV] = &pwm_d_div.hw,
+ [CLKID_PWM_E_SEL] = &pwm_e_sel.hw,
+ [CLKID_PWM_E_DIV] = &pwm_e_div.hw,
+ [CLKID_PWM_F_SEL] = &pwm_f_sel.hw,
+ [CLKID_PWM_F_DIV] = &pwm_f_div.hw,
+ [CLKID_SPICC_SEL] = &spicc_sel.hw,
+ [CLKID_SPICC_DIV] = &spicc_div.hw,
+ [CLKID_SPICC_SEL2] = &spicc_sel2.hw,
+ [CLKID_TS_DIV] = &ts_div.hw,
+ [CLKID_SPIFC_SEL] = &spifc_sel.hw,
+ [CLKID_SPIFC_DIV] = &spifc_div.hw,
+ [CLKID_SPIFC_SEL2] = &spifc_sel2.hw,
+ [CLKID_USB_BUS_SEL] = &usb_bus_sel.hw,
+ [CLKID_USB_BUS_DIV] = &usb_bus_div.hw,
+ [CLKID_SD_EMMC_SEL] = &sd_emmc_sel.hw,
+ [CLKID_SD_EMMC_DIV] = &sd_emmc_div.hw,
+ [CLKID_SD_EMMC_SEL2] = &sd_emmc_sel2.hw,
+ [CLKID_PSRAM_SEL] = &psram_sel.hw,
+ [CLKID_PSRAM_DIV] = &psram_div.hw,
+ [CLKID_PSRAM_SEL2] = &psram_sel2.hw,
+ [CLKID_DMC_SEL] = &dmc_sel.hw,
+ [CLKID_DMC_DIV] = &dmc_div.hw,
+ [CLKID_DMC_SEL2] = &dmc_sel2.hw,
};
/* Convenience table to populate regmap in .probe */
@@ -2190,6 +2186,29 @@ static struct regmap_config a1_periphs_regmap_cfg = {
.reg_stride = 4,
};
+struct meson_a1_periphs_clks {
+ struct clk_hw **hw_clks;
+ unsigned int hw_clk_num;
+};
+
+static struct meson_a1_periphs_clks a1_periphs_clks = {
+ .hw_clks = a1_periphs_hw_clks,
+ .hw_clk_num = ARRAY_SIZE(a1_periphs_hw_clks),
+};
+
+static struct clk_hw *meson_a1_periphs_hw_get(struct of_phandle_args *clkspec, void *clk_data)
+{
+ const struct meson_a1_periphs_clks *data = clk_data;
+ unsigned int idx = clkspec->args[0];
+
+ if (idx >= data->hw_clk_num) {
+ pr_err("%s: invalid index %u\n", __func__, idx);
+ return ERR_PTR(-EINVAL);
+ }
+
+ return data->hw_clks[idx];
+}
+
static int meson_a1_periphs_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -2211,15 +2230,15 @@ static int meson_a1_periphs_probe(struct platform_device *pdev)
for (i = 0; i < ARRAY_SIZE(a1_periphs_regmaps); i++)
a1_periphs_regmaps[i]->map = map;
- for (clkid = 0; clkid < a1_periphs_clks.num; clkid++) {
- err = devm_clk_hw_register(dev, a1_periphs_clks.hws[clkid]);
+ for (clkid = 0; clkid < a1_periphs_clks.hw_clk_num; clkid++) {
+ err = devm_clk_hw_register(dev, a1_periphs_clks.hw_clks[clkid]);
if (err)
return dev_err_probe(dev, err,
"clock[%d] registration failed\n",
clkid);
}
- return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
+ return devm_of_clk_add_hw_provider(dev, meson_a1_periphs_hw_get,
&a1_periphs_clks);
}
diff --git a/drivers/clk/meson/a1-peripherals.h b/drivers/clk/meson/a1-peripherals.h
index 526fc9ba5c9f..4d60456a95a9 100644
--- a/drivers/clk/meson/a1-peripherals.h
+++ b/drivers/clk/meson/a1-peripherals.h
@@ -108,6 +108,5 @@
#define CLKID_DMC_SEL 151
#define CLKID_DMC_DIV 152
#define CLKID_DMC_SEL2 153
-#define NR_CLKS 154
#endif /* __A1_PERIPHERALS_H */
diff --git a/drivers/clk/meson/a1-pll.c b/drivers/clk/meson/a1-pll.c
index bd2f1d1ec6e4..25d102dc8a5d 100644
--- a/drivers/clk/meson/a1-pll.c
+++ b/drivers/clk/meson/a1-pll.c
@@ -268,22 +268,18 @@ static struct clk_regmap fclk_div7 = {
};
/* Array of all clocks registered by this provider */
-static struct clk_hw_onecell_data a1_pll_clks = {
- .hws = {
- [CLKID_FIXED_PLL_DCO] = &fixed_pll_dco.hw,
- [CLKID_FIXED_PLL] = &fixed_pll.hw,
- [CLKID_FCLK_DIV2_DIV] = &fclk_div2_div.hw,
- [CLKID_FCLK_DIV3_DIV] = &fclk_div3_div.hw,
- [CLKID_FCLK_DIV5_DIV] = &fclk_div5_div.hw,
- [CLKID_FCLK_DIV7_DIV] = &fclk_div7_div.hw,
- [CLKID_FCLK_DIV2] = &fclk_div2.hw,
- [CLKID_FCLK_DIV3] = &fclk_div3.hw,
- [CLKID_FCLK_DIV5] = &fclk_div5.hw,
- [CLKID_FCLK_DIV7] = &fclk_div7.hw,
- [CLKID_HIFI_PLL] = &hifi_pll.hw,
- [NR_PLL_CLKS] = NULL,
- },
- .num = NR_PLL_CLKS,
+static struct clk_hw *a1_pll_hw_clks[] = {
+ [CLKID_FIXED_PLL_DCO] = &fixed_pll_dco.hw,
+ [CLKID_FIXED_PLL] = &fixed_pll.hw,
+ [CLKID_FCLK_DIV2_DIV] = &fclk_div2_div.hw,
+ [CLKID_FCLK_DIV3_DIV] = &fclk_div3_div.hw,
+ [CLKID_FCLK_DIV5_DIV] = &fclk_div5_div.hw,
+ [CLKID_FCLK_DIV7_DIV] = &fclk_div7_div.hw,
+ [CLKID_FCLK_DIV2] = &fclk_div2.hw,
+ [CLKID_FCLK_DIV3] = &fclk_div3.hw,
+ [CLKID_FCLK_DIV5] = &fclk_div5.hw,
+ [CLKID_FCLK_DIV7] = &fclk_div7.hw,
+ [CLKID_HIFI_PLL] = &hifi_pll.hw,
};
static struct clk_regmap *const a1_pll_regmaps[] = {
@@ -302,6 +298,29 @@ static struct regmap_config a1_pll_regmap_cfg = {
.reg_stride = 4,
};
+struct meson_a1_pll_clks {
+ struct clk_hw **hw_clks;
+ unsigned int hw_clk_num;
+};
+
+static struct meson_a1_pll_clks a1_pll_clks = {
+ .hw_clks = a1_pll_hw_clks,
+ .hw_clk_num = ARRAY_SIZE(a1_pll_hw_clks),
+};
+
+static struct clk_hw *meson_a1_pll_hw_get(struct of_phandle_args *clkspec, void *clk_data)
+{
+ const struct meson_a1_pll_clks *data = clk_data;
+ unsigned int idx = clkspec->args[0];
+
+ if (idx >= data->hw_clk_num) {
+ pr_err("%s: invalid index %u\n", __func__, idx);
+ return ERR_PTR(-EINVAL);
+ }
+
+ return data->hw_clks[idx];
+}
+
static int meson_a1_pll_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -324,15 +343,15 @@ static int meson_a1_pll_probe(struct platform_device *pdev)
a1_pll_regmaps[i]->map = map;
/* Register clocks */
- for (clkid = 0; clkid < a1_pll_clks.num; clkid++) {
- err = devm_clk_hw_register(dev, a1_pll_clks.hws[clkid]);
+ for (clkid = 0; clkid < a1_pll_clks.hw_clk_num; clkid++) {
+ err = devm_clk_hw_register(dev, a1_pll_clks.hw_clks[clkid]);
if (err)
return dev_err_probe(dev, err,
"clock[%d] registration failed\n",
clkid);
}
- return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
+ return devm_of_clk_add_hw_provider(dev, meson_a1_pll_hw_get,
&a1_pll_clks);
}
diff --git a/drivers/clk/meson/a1-pll.h b/drivers/clk/meson/a1-pll.h
index 29726651b056..82570759e6a2 100644
--- a/drivers/clk/meson/a1-pll.h
+++ b/drivers/clk/meson/a1-pll.h
@@ -42,6 +42,5 @@
#define CLKID_FCLK_DIV3_DIV 3
#define CLKID_FCLK_DIV5_DIV 4
#define CLKID_FCLK_DIV7_DIV 5
-#define NR_PLL_CLKS 11
#endif /* __A1_PLL_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 04/18] clk: meson: migrate meson8b out of hw_onecell_data to drop NR_CLKS
2023-06-07 10:56 [PATCH 00/18] clk: meson: move all private clk IDs to public dt-bindings headers Neil Armstrong
2023-06-07 10:56 ` [PATCH 02/18] clk: meson: migrate meson-aoclk out of hw_onecell_data to drop NR_CLKS Neil Armstrong
2023-06-07 10:56 ` [PATCH 03/18] clk: meson: migrate a1 clock drivers " Neil Armstrong
@ 2023-06-07 10:56 ` Neil Armstrong
2023-06-07 10:56 ` [PATCH 05/18] clk: meson: migrate axg-audio " Neil Armstrong
` (13 subsequent siblings)
16 siblings, 0 replies; 35+ messages in thread
From: Neil Armstrong @ 2023-06-07 10:56 UTC (permalink / raw)
To: Jerome Brunet, Michael Turquette, Stephen Boyd, Kevin Hilman,
Martin Blumenstingl, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-amlogic, linux-clk, linux-arm-kernel, linux-kernel,
devicetree, Neil Armstrong
The way hw_onecell_data is declared:
struct clk_hw_onecell_data {
unsigned int num;
struct clk_hw *hws[];
};
makes it impossible to have the clk_hw table declared outside while
using ARRAY_SIZE() to determine ".num" due to ".hws" being a flexible
array member.
Completely move out of hw_onecell_data and add a custom
devm_of_clk_add_hw_provider() "get" callback to retrieve the clk_hw
in order to finally get rid on the NR_CLKS define.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
drivers/clk/meson/meson8b.c | 1332 ++++++++++++++++++++++---------------------
drivers/clk/meson/meson8b.h | 2 -
2 files changed, 676 insertions(+), 658 deletions(-)
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index 827e78fb16a8..1e1313991a68 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -2772,652 +2772,640 @@ static MESON_GATE(meson8b_ao_ahb_sram, HHI_GCLK_AO, 1);
static MESON_GATE(meson8b_ao_ahb_bus, HHI_GCLK_AO, 2);
static MESON_GATE(meson8b_ao_iface, HHI_GCLK_AO, 3);
-static struct clk_hw_onecell_data meson8_hw_onecell_data = {
- .hws = {
- [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
- [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
- [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
- [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
- [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
- [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
- [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
- [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
- [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
- [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
- [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
- [CLKID_CLK81] = &meson8b_clk81.hw,
- [CLKID_DDR] = &meson8b_ddr.hw,
- [CLKID_DOS] = &meson8b_dos.hw,
- [CLKID_ISA] = &meson8b_isa.hw,
- [CLKID_PL301] = &meson8b_pl301.hw,
- [CLKID_PERIPHS] = &meson8b_periphs.hw,
- [CLKID_SPICC] = &meson8b_spicc.hw,
- [CLKID_I2C] = &meson8b_i2c.hw,
- [CLKID_SAR_ADC] = &meson8b_sar_adc.hw,
- [CLKID_SMART_CARD] = &meson8b_smart_card.hw,
- [CLKID_RNG0] = &meson8b_rng0.hw,
- [CLKID_UART0] = &meson8b_uart0.hw,
- [CLKID_SDHC] = &meson8b_sdhc.hw,
- [CLKID_STREAM] = &meson8b_stream.hw,
- [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw,
- [CLKID_SDIO] = &meson8b_sdio.hw,
- [CLKID_ABUF] = &meson8b_abuf.hw,
- [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw,
- [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw,
- [CLKID_SPI] = &meson8b_spi.hw,
- [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw,
- [CLKID_ETH] = &meson8b_eth.hw,
- [CLKID_DEMUX] = &meson8b_demux.hw,
- [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw,
- [CLKID_IEC958] = &meson8b_iec958.hw,
- [CLKID_I2S_OUT] = &meson8b_i2s_out.hw,
- [CLKID_AMCLK] = &meson8b_amclk.hw,
- [CLKID_AIFIFO2] = &meson8b_aififo2.hw,
- [CLKID_MIXER] = &meson8b_mixer.hw,
- [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw,
- [CLKID_ADC] = &meson8b_adc.hw,
- [CLKID_BLKMV] = &meson8b_blkmv.hw,
- [CLKID_AIU] = &meson8b_aiu.hw,
- [CLKID_UART1] = &meson8b_uart1.hw,
- [CLKID_G2D] = &meson8b_g2d.hw,
- [CLKID_USB0] = &meson8b_usb0.hw,
- [CLKID_USB1] = &meson8b_usb1.hw,
- [CLKID_RESET] = &meson8b_reset.hw,
- [CLKID_NAND] = &meson8b_nand.hw,
- [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw,
- [CLKID_USB] = &meson8b_usb.hw,
- [CLKID_VDIN1] = &meson8b_vdin1.hw,
- [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw,
- [CLKID_EFUSE] = &meson8b_efuse.hw,
- [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw,
- [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw,
- [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw,
- [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw,
- [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw,
- [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw,
- [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw,
- [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw,
- [CLKID_DVIN] = &meson8b_dvin.hw,
- [CLKID_UART2] = &meson8b_uart2.hw,
- [CLKID_SANA] = &meson8b_sana.hw,
- [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw,
- [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
- [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw,
- [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw,
- [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw,
- [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw,
- [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw,
- [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw,
- [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw,
- [CLKID_DAC_CLK] = &meson8b_dac_clk.hw,
- [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw,
- [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw,
- [CLKID_ENC480P] = &meson8b_enc480p.hw,
- [CLKID_RNG1] = &meson8b_rng1.hw,
- [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw,
- [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw,
- [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw,
- [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw,
- [CLKID_EDP] = &meson8b_edp.hw,
- [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw,
- [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw,
- [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw,
- [CLKID_AO_IFACE] = &meson8b_ao_iface.hw,
- [CLKID_MPLL0] = &meson8b_mpll0.hw,
- [CLKID_MPLL1] = &meson8b_mpll1.hw,
- [CLKID_MPLL2] = &meson8b_mpll2.hw,
- [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
- [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw,
- [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw,
- [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw,
- [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw,
- [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw,
- [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw,
- [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw,
- [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw,
- [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw,
- [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw,
- [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw,
- [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw,
- [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw,
- [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw,
- [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw,
- [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw,
- [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw,
- [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw,
- [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw,
- [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw,
- [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw,
- [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw,
- [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw,
- [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw,
- [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw,
- [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw,
- [CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw,
- [CLKID_APB] = &meson8b_apb_clk_gate.hw,
- [CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw,
- [CLKID_PERIPH] = &meson8b_periph_clk_gate.hw,
- [CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw,
- [CLKID_AXI] = &meson8b_axi_clk_gate.hw,
- [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw,
- [CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw,
- [CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw,
- [CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw,
- [CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw,
- [CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw,
- [CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw,
- [CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw,
- [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw,
- [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
- [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
- [CLKID_VCLK_EN] = &meson8b_vclk_en.hw,
- [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
- [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
- [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
- [CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw,
- [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw,
- [CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw,
- [CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw,
- [CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw,
- [CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
- [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw,
- [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw,
- [CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw,
- [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
- [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw,
- [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw,
- [CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw,
- [CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4_div_gate.hw,
- [CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw,
- [CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6_div_gate.hw,
- [CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw,
- [CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12_div_gate.hw,
- [CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw,
- [CLKID_CTS_ENCT] = &meson8b_cts_enct.hw,
- [CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw,
- [CLKID_CTS_ENCP] = &meson8b_cts_encp.hw,
- [CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw,
- [CLKID_CTS_ENCI] = &meson8b_cts_enci.hw,
- [CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw,
- [CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw,
- [CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw,
- [CLKID_CTS_ENCL] = &meson8b_cts_encl.hw,
- [CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw,
- [CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw,
- [CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw,
- [CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw,
- [CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw,
- [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw,
- [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw,
- [CLKID_MALI] = &meson8b_mali_0.hw,
- [CLKID_VPU_0_SEL] = &meson8b_vpu_0_sel.hw,
- [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw,
- [CLKID_VPU] = &meson8b_vpu_0.hw,
- [CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw,
- [CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw,
- [CLKID_VDEC_1] = &meson8b_vdec_1_1.hw,
- [CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw,
- [CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw,
- [CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw,
- [CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw,
- [CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw,
- [CLKID_VDEC_2] = &meson8b_vdec_2.hw,
- [CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw,
- [CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw,
- [CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw,
- [CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw,
- [CLKID_CTS_AMCLK_SEL] = &meson8b_cts_amclk_sel.hw,
- [CLKID_CTS_AMCLK_DIV] = &meson8b_cts_amclk_div.hw,
- [CLKID_CTS_AMCLK] = &meson8b_cts_amclk.hw,
- [CLKID_CTS_MCLK_I958_SEL] = &meson8b_cts_mclk_i958_sel.hw,
- [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw,
- [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw,
- [CLKID_CTS_I958] = &meson8b_cts_i958.hw,
- [CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw,
- [CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw,
- [CLK_NR_CLKS] = NULL,
- },
- .num = CLK_NR_CLKS,
-};
-
-static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
- .hws = {
- [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
- [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
- [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
- [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
- [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
- [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
- [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
- [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
- [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
- [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
- [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
- [CLKID_CLK81] = &meson8b_clk81.hw,
- [CLKID_DDR] = &meson8b_ddr.hw,
- [CLKID_DOS] = &meson8b_dos.hw,
- [CLKID_ISA] = &meson8b_isa.hw,
- [CLKID_PL301] = &meson8b_pl301.hw,
- [CLKID_PERIPHS] = &meson8b_periphs.hw,
- [CLKID_SPICC] = &meson8b_spicc.hw,
- [CLKID_I2C] = &meson8b_i2c.hw,
- [CLKID_SAR_ADC] = &meson8b_sar_adc.hw,
- [CLKID_SMART_CARD] = &meson8b_smart_card.hw,
- [CLKID_RNG0] = &meson8b_rng0.hw,
- [CLKID_UART0] = &meson8b_uart0.hw,
- [CLKID_SDHC] = &meson8b_sdhc.hw,
- [CLKID_STREAM] = &meson8b_stream.hw,
- [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw,
- [CLKID_SDIO] = &meson8b_sdio.hw,
- [CLKID_ABUF] = &meson8b_abuf.hw,
- [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw,
- [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw,
- [CLKID_SPI] = &meson8b_spi.hw,
- [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw,
- [CLKID_ETH] = &meson8b_eth.hw,
- [CLKID_DEMUX] = &meson8b_demux.hw,
- [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw,
- [CLKID_IEC958] = &meson8b_iec958.hw,
- [CLKID_I2S_OUT] = &meson8b_i2s_out.hw,
- [CLKID_AMCLK] = &meson8b_amclk.hw,
- [CLKID_AIFIFO2] = &meson8b_aififo2.hw,
- [CLKID_MIXER] = &meson8b_mixer.hw,
- [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw,
- [CLKID_ADC] = &meson8b_adc.hw,
- [CLKID_BLKMV] = &meson8b_blkmv.hw,
- [CLKID_AIU] = &meson8b_aiu.hw,
- [CLKID_UART1] = &meson8b_uart1.hw,
- [CLKID_G2D] = &meson8b_g2d.hw,
- [CLKID_USB0] = &meson8b_usb0.hw,
- [CLKID_USB1] = &meson8b_usb1.hw,
- [CLKID_RESET] = &meson8b_reset.hw,
- [CLKID_NAND] = &meson8b_nand.hw,
- [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw,
- [CLKID_USB] = &meson8b_usb.hw,
- [CLKID_VDIN1] = &meson8b_vdin1.hw,
- [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw,
- [CLKID_EFUSE] = &meson8b_efuse.hw,
- [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw,
- [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw,
- [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw,
- [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw,
- [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw,
- [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw,
- [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw,
- [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw,
- [CLKID_DVIN] = &meson8b_dvin.hw,
- [CLKID_UART2] = &meson8b_uart2.hw,
- [CLKID_SANA] = &meson8b_sana.hw,
- [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw,
- [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
- [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw,
- [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw,
- [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw,
- [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw,
- [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw,
- [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw,
- [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw,
- [CLKID_DAC_CLK] = &meson8b_dac_clk.hw,
- [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw,
- [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw,
- [CLKID_ENC480P] = &meson8b_enc480p.hw,
- [CLKID_RNG1] = &meson8b_rng1.hw,
- [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw,
- [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw,
- [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw,
- [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw,
- [CLKID_EDP] = &meson8b_edp.hw,
- [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw,
- [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw,
- [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw,
- [CLKID_AO_IFACE] = &meson8b_ao_iface.hw,
- [CLKID_MPLL0] = &meson8b_mpll0.hw,
- [CLKID_MPLL1] = &meson8b_mpll1.hw,
- [CLKID_MPLL2] = &meson8b_mpll2.hw,
- [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
- [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw,
- [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw,
- [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw,
- [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw,
- [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw,
- [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw,
- [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw,
- [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw,
- [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw,
- [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw,
- [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw,
- [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw,
- [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw,
- [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw,
- [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw,
- [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw,
- [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw,
- [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw,
- [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw,
- [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw,
- [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw,
- [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw,
- [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw,
- [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw,
- [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw,
- [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw,
- [CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw,
- [CLKID_APB] = &meson8b_apb_clk_gate.hw,
- [CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw,
- [CLKID_PERIPH] = &meson8b_periph_clk_gate.hw,
- [CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw,
- [CLKID_AXI] = &meson8b_axi_clk_gate.hw,
- [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw,
- [CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw,
- [CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw,
- [CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw,
- [CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw,
- [CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw,
- [CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw,
- [CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw,
- [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw,
- [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
- [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
- [CLKID_VCLK_EN] = &meson8b_vclk_en.hw,
- [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
- [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
- [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
- [CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw,
- [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw,
- [CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw,
- [CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw,
- [CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw,
- [CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
- [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw,
- [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw,
- [CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw,
- [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
- [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw,
- [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw,
- [CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw,
- [CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4_div_gate.hw,
- [CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw,
- [CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6_div_gate.hw,
- [CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw,
- [CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12_div_gate.hw,
- [CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw,
- [CLKID_CTS_ENCT] = &meson8b_cts_enct.hw,
- [CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw,
- [CLKID_CTS_ENCP] = &meson8b_cts_encp.hw,
- [CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw,
- [CLKID_CTS_ENCI] = &meson8b_cts_enci.hw,
- [CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw,
- [CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw,
- [CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw,
- [CLKID_CTS_ENCL] = &meson8b_cts_encl.hw,
- [CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw,
- [CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw,
- [CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw,
- [CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw,
- [CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw,
- [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw,
- [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw,
- [CLKID_MALI_0] = &meson8b_mali_0.hw,
- [CLKID_MALI_1_SEL] = &meson8b_mali_1_sel.hw,
- [CLKID_MALI_1_DIV] = &meson8b_mali_1_div.hw,
- [CLKID_MALI_1] = &meson8b_mali_1.hw,
- [CLKID_MALI] = &meson8b_mali.hw,
- [CLKID_VPU_0_SEL] = &meson8b_vpu_0_sel.hw,
- [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw,
- [CLKID_VPU_0] = &meson8b_vpu_0.hw,
- [CLKID_VPU_1_SEL] = &meson8b_vpu_1_sel.hw,
- [CLKID_VPU_1_DIV] = &meson8b_vpu_1_div.hw,
- [CLKID_VPU_1] = &meson8b_vpu_1.hw,
- [CLKID_VPU] = &meson8b_vpu.hw,
- [CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw,
- [CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw,
- [CLKID_VDEC_1_1] = &meson8b_vdec_1_1.hw,
- [CLKID_VDEC_1_2_DIV] = &meson8b_vdec_1_2_div.hw,
- [CLKID_VDEC_1_2] = &meson8b_vdec_1_2.hw,
- [CLKID_VDEC_1] = &meson8b_vdec_1.hw,
- [CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw,
- [CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw,
- [CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw,
- [CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw,
- [CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw,
- [CLKID_VDEC_2] = &meson8b_vdec_2.hw,
- [CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw,
- [CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw,
- [CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw,
- [CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw,
- [CLKID_CTS_AMCLK_SEL] = &meson8b_cts_amclk_sel.hw,
- [CLKID_CTS_AMCLK_DIV] = &meson8b_cts_amclk_div.hw,
- [CLKID_CTS_AMCLK] = &meson8b_cts_amclk.hw,
- [CLKID_CTS_MCLK_I958_SEL] = &meson8b_cts_mclk_i958_sel.hw,
- [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw,
- [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw,
- [CLKID_CTS_I958] = &meson8b_cts_i958.hw,
- [CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw,
- [CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw,
- [CLK_NR_CLKS] = NULL,
- },
- .num = CLK_NR_CLKS,
-};
-
-static struct clk_hw_onecell_data meson8m2_hw_onecell_data = {
- .hws = {
- [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
- [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
- [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
- [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
- [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
- [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
- [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
- [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
- [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
- [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
- [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
- [CLKID_CLK81] = &meson8b_clk81.hw,
- [CLKID_DDR] = &meson8b_ddr.hw,
- [CLKID_DOS] = &meson8b_dos.hw,
- [CLKID_ISA] = &meson8b_isa.hw,
- [CLKID_PL301] = &meson8b_pl301.hw,
- [CLKID_PERIPHS] = &meson8b_periphs.hw,
- [CLKID_SPICC] = &meson8b_spicc.hw,
- [CLKID_I2C] = &meson8b_i2c.hw,
- [CLKID_SAR_ADC] = &meson8b_sar_adc.hw,
- [CLKID_SMART_CARD] = &meson8b_smart_card.hw,
- [CLKID_RNG0] = &meson8b_rng0.hw,
- [CLKID_UART0] = &meson8b_uart0.hw,
- [CLKID_SDHC] = &meson8b_sdhc.hw,
- [CLKID_STREAM] = &meson8b_stream.hw,
- [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw,
- [CLKID_SDIO] = &meson8b_sdio.hw,
- [CLKID_ABUF] = &meson8b_abuf.hw,
- [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw,
- [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw,
- [CLKID_SPI] = &meson8b_spi.hw,
- [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw,
- [CLKID_ETH] = &meson8b_eth.hw,
- [CLKID_DEMUX] = &meson8b_demux.hw,
- [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw,
- [CLKID_IEC958] = &meson8b_iec958.hw,
- [CLKID_I2S_OUT] = &meson8b_i2s_out.hw,
- [CLKID_AMCLK] = &meson8b_amclk.hw,
- [CLKID_AIFIFO2] = &meson8b_aififo2.hw,
- [CLKID_MIXER] = &meson8b_mixer.hw,
- [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw,
- [CLKID_ADC] = &meson8b_adc.hw,
- [CLKID_BLKMV] = &meson8b_blkmv.hw,
- [CLKID_AIU] = &meson8b_aiu.hw,
- [CLKID_UART1] = &meson8b_uart1.hw,
- [CLKID_G2D] = &meson8b_g2d.hw,
- [CLKID_USB0] = &meson8b_usb0.hw,
- [CLKID_USB1] = &meson8b_usb1.hw,
- [CLKID_RESET] = &meson8b_reset.hw,
- [CLKID_NAND] = &meson8b_nand.hw,
- [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw,
- [CLKID_USB] = &meson8b_usb.hw,
- [CLKID_VDIN1] = &meson8b_vdin1.hw,
- [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw,
- [CLKID_EFUSE] = &meson8b_efuse.hw,
- [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw,
- [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw,
- [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw,
- [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw,
- [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw,
- [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw,
- [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw,
- [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw,
- [CLKID_DVIN] = &meson8b_dvin.hw,
- [CLKID_UART2] = &meson8b_uart2.hw,
- [CLKID_SANA] = &meson8b_sana.hw,
- [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw,
- [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
- [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw,
- [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw,
- [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw,
- [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw,
- [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw,
- [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw,
- [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw,
- [CLKID_DAC_CLK] = &meson8b_dac_clk.hw,
- [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw,
- [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw,
- [CLKID_ENC480P] = &meson8b_enc480p.hw,
- [CLKID_RNG1] = &meson8b_rng1.hw,
- [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw,
- [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw,
- [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw,
- [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw,
- [CLKID_EDP] = &meson8b_edp.hw,
- [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw,
- [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw,
- [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw,
- [CLKID_AO_IFACE] = &meson8b_ao_iface.hw,
- [CLKID_MPLL0] = &meson8b_mpll0.hw,
- [CLKID_MPLL1] = &meson8b_mpll1.hw,
- [CLKID_MPLL2] = &meson8b_mpll2.hw,
- [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
- [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw,
- [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw,
- [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw,
- [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw,
- [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw,
- [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw,
- [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw,
- [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw,
- [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw,
- [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw,
- [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw,
- [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw,
- [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw,
- [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw,
- [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw,
- [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw,
- [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw,
- [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw,
- [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw,
- [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw,
- [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw,
- [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw,
- [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw,
- [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw,
- [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw,
- [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw,
- [CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw,
- [CLKID_APB] = &meson8b_apb_clk_gate.hw,
- [CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw,
- [CLKID_PERIPH] = &meson8b_periph_clk_gate.hw,
- [CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw,
- [CLKID_AXI] = &meson8b_axi_clk_gate.hw,
- [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw,
- [CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw,
- [CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw,
- [CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw,
- [CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw,
- [CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw,
- [CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw,
- [CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw,
- [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw,
- [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
- [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
- [CLKID_VCLK_EN] = &meson8b_vclk_en.hw,
- [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
- [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
- [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
- [CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw,
- [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw,
- [CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw,
- [CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw,
- [CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw,
- [CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
- [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw,
- [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw,
- [CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw,
- [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
- [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw,
- [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw,
- [CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw,
- [CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4_div_gate.hw,
- [CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw,
- [CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6_div_gate.hw,
- [CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw,
- [CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12_div_gate.hw,
- [CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw,
- [CLKID_CTS_ENCT] = &meson8b_cts_enct.hw,
- [CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw,
- [CLKID_CTS_ENCP] = &meson8b_cts_encp.hw,
- [CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw,
- [CLKID_CTS_ENCI] = &meson8b_cts_enci.hw,
- [CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw,
- [CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw,
- [CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw,
- [CLKID_CTS_ENCL] = &meson8b_cts_encl.hw,
- [CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw,
- [CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw,
- [CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw,
- [CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw,
- [CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw,
- [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw,
- [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw,
- [CLKID_MALI_0] = &meson8b_mali_0.hw,
- [CLKID_MALI_1_SEL] = &meson8b_mali_1_sel.hw,
- [CLKID_MALI_1_DIV] = &meson8b_mali_1_div.hw,
- [CLKID_MALI_1] = &meson8b_mali_1.hw,
- [CLKID_MALI] = &meson8b_mali.hw,
- [CLKID_GP_PLL_DCO] = &meson8m2_gp_pll_dco.hw,
- [CLKID_GP_PLL] = &meson8m2_gp_pll.hw,
- [CLKID_VPU_0_SEL] = &meson8m2_vpu_0_sel.hw,
- [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw,
- [CLKID_VPU_0] = &meson8b_vpu_0.hw,
- [CLKID_VPU_1_SEL] = &meson8m2_vpu_1_sel.hw,
- [CLKID_VPU_1_DIV] = &meson8b_vpu_1_div.hw,
- [CLKID_VPU_1] = &meson8b_vpu_1.hw,
- [CLKID_VPU] = &meson8b_vpu.hw,
- [CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw,
- [CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw,
- [CLKID_VDEC_1_1] = &meson8b_vdec_1_1.hw,
- [CLKID_VDEC_1_2_DIV] = &meson8b_vdec_1_2_div.hw,
- [CLKID_VDEC_1_2] = &meson8b_vdec_1_2.hw,
- [CLKID_VDEC_1] = &meson8b_vdec_1.hw,
- [CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw,
- [CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw,
- [CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw,
- [CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw,
- [CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw,
- [CLKID_VDEC_2] = &meson8b_vdec_2.hw,
- [CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw,
- [CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw,
- [CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw,
- [CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw,
- [CLKID_CTS_AMCLK_SEL] = &meson8b_cts_amclk_sel.hw,
- [CLKID_CTS_AMCLK_DIV] = &meson8b_cts_amclk_div.hw,
- [CLKID_CTS_AMCLK] = &meson8b_cts_amclk.hw,
- [CLKID_CTS_MCLK_I958_SEL] = &meson8b_cts_mclk_i958_sel.hw,
- [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw,
- [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw,
- [CLKID_CTS_I958] = &meson8b_cts_i958.hw,
- [CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw,
- [CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw,
- [CLK_NR_CLKS] = NULL,
- },
- .num = CLK_NR_CLKS,
+static struct clk_hw *meson8_hw_clks[] = {
+ [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
+ [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
+ [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
+ [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
+ [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
+ [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
+ [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
+ [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
+ [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
+ [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
+ [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
+ [CLKID_CLK81] = &meson8b_clk81.hw,
+ [CLKID_DDR] = &meson8b_ddr.hw,
+ [CLKID_DOS] = &meson8b_dos.hw,
+ [CLKID_ISA] = &meson8b_isa.hw,
+ [CLKID_PL301] = &meson8b_pl301.hw,
+ [CLKID_PERIPHS] = &meson8b_periphs.hw,
+ [CLKID_SPICC] = &meson8b_spicc.hw,
+ [CLKID_I2C] = &meson8b_i2c.hw,
+ [CLKID_SAR_ADC] = &meson8b_sar_adc.hw,
+ [CLKID_SMART_CARD] = &meson8b_smart_card.hw,
+ [CLKID_RNG0] = &meson8b_rng0.hw,
+ [CLKID_UART0] = &meson8b_uart0.hw,
+ [CLKID_SDHC] = &meson8b_sdhc.hw,
+ [CLKID_STREAM] = &meson8b_stream.hw,
+ [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw,
+ [CLKID_SDIO] = &meson8b_sdio.hw,
+ [CLKID_ABUF] = &meson8b_abuf.hw,
+ [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw,
+ [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw,
+ [CLKID_SPI] = &meson8b_spi.hw,
+ [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw,
+ [CLKID_ETH] = &meson8b_eth.hw,
+ [CLKID_DEMUX] = &meson8b_demux.hw,
+ [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw,
+ [CLKID_IEC958] = &meson8b_iec958.hw,
+ [CLKID_I2S_OUT] = &meson8b_i2s_out.hw,
+ [CLKID_AMCLK] = &meson8b_amclk.hw,
+ [CLKID_AIFIFO2] = &meson8b_aififo2.hw,
+ [CLKID_MIXER] = &meson8b_mixer.hw,
+ [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw,
+ [CLKID_ADC] = &meson8b_adc.hw,
+ [CLKID_BLKMV] = &meson8b_blkmv.hw,
+ [CLKID_AIU] = &meson8b_aiu.hw,
+ [CLKID_UART1] = &meson8b_uart1.hw,
+ [CLKID_G2D] = &meson8b_g2d.hw,
+ [CLKID_USB0] = &meson8b_usb0.hw,
+ [CLKID_USB1] = &meson8b_usb1.hw,
+ [CLKID_RESET] = &meson8b_reset.hw,
+ [CLKID_NAND] = &meson8b_nand.hw,
+ [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw,
+ [CLKID_USB] = &meson8b_usb.hw,
+ [CLKID_VDIN1] = &meson8b_vdin1.hw,
+ [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw,
+ [CLKID_EFUSE] = &meson8b_efuse.hw,
+ [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw,
+ [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw,
+ [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw,
+ [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw,
+ [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw,
+ [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw,
+ [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw,
+ [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw,
+ [CLKID_DVIN] = &meson8b_dvin.hw,
+ [CLKID_UART2] = &meson8b_uart2.hw,
+ [CLKID_SANA] = &meson8b_sana.hw,
+ [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw,
+ [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
+ [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw,
+ [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw,
+ [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw,
+ [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw,
+ [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw,
+ [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw,
+ [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw,
+ [CLKID_DAC_CLK] = &meson8b_dac_clk.hw,
+ [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw,
+ [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw,
+ [CLKID_ENC480P] = &meson8b_enc480p.hw,
+ [CLKID_RNG1] = &meson8b_rng1.hw,
+ [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw,
+ [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw,
+ [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw,
+ [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw,
+ [CLKID_EDP] = &meson8b_edp.hw,
+ [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw,
+ [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw,
+ [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw,
+ [CLKID_AO_IFACE] = &meson8b_ao_iface.hw,
+ [CLKID_MPLL0] = &meson8b_mpll0.hw,
+ [CLKID_MPLL1] = &meson8b_mpll1.hw,
+ [CLKID_MPLL2] = &meson8b_mpll2.hw,
+ [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
+ [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw,
+ [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw,
+ [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw,
+ [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw,
+ [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw,
+ [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw,
+ [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw,
+ [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw,
+ [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw,
+ [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw,
+ [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw,
+ [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw,
+ [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw,
+ [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw,
+ [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw,
+ [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw,
+ [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw,
+ [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw,
+ [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw,
+ [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw,
+ [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw,
+ [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw,
+ [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw,
+ [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw,
+ [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw,
+ [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw,
+ [CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw,
+ [CLKID_APB] = &meson8b_apb_clk_gate.hw,
+ [CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw,
+ [CLKID_PERIPH] = &meson8b_periph_clk_gate.hw,
+ [CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw,
+ [CLKID_AXI] = &meson8b_axi_clk_gate.hw,
+ [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw,
+ [CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw,
+ [CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw,
+ [CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw,
+ [CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw,
+ [CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw,
+ [CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw,
+ [CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw,
+ [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw,
+ [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
+ [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
+ [CLKID_VCLK_EN] = &meson8b_vclk_en.hw,
+ [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
+ [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
+ [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
+ [CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw,
+ [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw,
+ [CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw,
+ [CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw,
+ [CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw,
+ [CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
+ [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw,
+ [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw,
+ [CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw,
+ [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
+ [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw,
+ [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw,
+ [CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw,
+ [CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4_div_gate.hw,
+ [CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw,
+ [CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6_div_gate.hw,
+ [CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw,
+ [CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12_div_gate.hw,
+ [CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw,
+ [CLKID_CTS_ENCT] = &meson8b_cts_enct.hw,
+ [CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw,
+ [CLKID_CTS_ENCP] = &meson8b_cts_encp.hw,
+ [CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw,
+ [CLKID_CTS_ENCI] = &meson8b_cts_enci.hw,
+ [CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw,
+ [CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw,
+ [CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw,
+ [CLKID_CTS_ENCL] = &meson8b_cts_encl.hw,
+ [CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw,
+ [CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw,
+ [CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw,
+ [CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw,
+ [CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw,
+ [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw,
+ [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw,
+ [CLKID_MALI] = &meson8b_mali_0.hw,
+ [CLKID_VPU_0_SEL] = &meson8b_vpu_0_sel.hw,
+ [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw,
+ [CLKID_VPU] = &meson8b_vpu_0.hw,
+ [CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw,
+ [CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw,
+ [CLKID_VDEC_1] = &meson8b_vdec_1_1.hw,
+ [CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw,
+ [CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw,
+ [CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw,
+ [CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw,
+ [CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw,
+ [CLKID_VDEC_2] = &meson8b_vdec_2.hw,
+ [CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw,
+ [CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw,
+ [CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw,
+ [CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw,
+ [CLKID_CTS_AMCLK_SEL] = &meson8b_cts_amclk_sel.hw,
+ [CLKID_CTS_AMCLK_DIV] = &meson8b_cts_amclk_div.hw,
+ [CLKID_CTS_AMCLK] = &meson8b_cts_amclk.hw,
+ [CLKID_CTS_MCLK_I958_SEL] = &meson8b_cts_mclk_i958_sel.hw,
+ [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw,
+ [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw,
+ [CLKID_CTS_I958] = &meson8b_cts_i958.hw,
+ [CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw,
+ [CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw,
+};
+
+static struct clk_hw *meson8b_hw_clks[] = {
+ [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
+ [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
+ [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
+ [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
+ [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
+ [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
+ [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
+ [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
+ [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
+ [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
+ [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
+ [CLKID_CLK81] = &meson8b_clk81.hw,
+ [CLKID_DDR] = &meson8b_ddr.hw,
+ [CLKID_DOS] = &meson8b_dos.hw,
+ [CLKID_ISA] = &meson8b_isa.hw,
+ [CLKID_PL301] = &meson8b_pl301.hw,
+ [CLKID_PERIPHS] = &meson8b_periphs.hw,
+ [CLKID_SPICC] = &meson8b_spicc.hw,
+ [CLKID_I2C] = &meson8b_i2c.hw,
+ [CLKID_SAR_ADC] = &meson8b_sar_adc.hw,
+ [CLKID_SMART_CARD] = &meson8b_smart_card.hw,
+ [CLKID_RNG0] = &meson8b_rng0.hw,
+ [CLKID_UART0] = &meson8b_uart0.hw,
+ [CLKID_SDHC] = &meson8b_sdhc.hw,
+ [CLKID_STREAM] = &meson8b_stream.hw,
+ [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw,
+ [CLKID_SDIO] = &meson8b_sdio.hw,
+ [CLKID_ABUF] = &meson8b_abuf.hw,
+ [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw,
+ [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw,
+ [CLKID_SPI] = &meson8b_spi.hw,
+ [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw,
+ [CLKID_ETH] = &meson8b_eth.hw,
+ [CLKID_DEMUX] = &meson8b_demux.hw,
+ [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw,
+ [CLKID_IEC958] = &meson8b_iec958.hw,
+ [CLKID_I2S_OUT] = &meson8b_i2s_out.hw,
+ [CLKID_AMCLK] = &meson8b_amclk.hw,
+ [CLKID_AIFIFO2] = &meson8b_aififo2.hw,
+ [CLKID_MIXER] = &meson8b_mixer.hw,
+ [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw,
+ [CLKID_ADC] = &meson8b_adc.hw,
+ [CLKID_BLKMV] = &meson8b_blkmv.hw,
+ [CLKID_AIU] = &meson8b_aiu.hw,
+ [CLKID_UART1] = &meson8b_uart1.hw,
+ [CLKID_G2D] = &meson8b_g2d.hw,
+ [CLKID_USB0] = &meson8b_usb0.hw,
+ [CLKID_USB1] = &meson8b_usb1.hw,
+ [CLKID_RESET] = &meson8b_reset.hw,
+ [CLKID_NAND] = &meson8b_nand.hw,
+ [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw,
+ [CLKID_USB] = &meson8b_usb.hw,
+ [CLKID_VDIN1] = &meson8b_vdin1.hw,
+ [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw,
+ [CLKID_EFUSE] = &meson8b_efuse.hw,
+ [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw,
+ [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw,
+ [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw,
+ [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw,
+ [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw,
+ [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw,
+ [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw,
+ [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw,
+ [CLKID_DVIN] = &meson8b_dvin.hw,
+ [CLKID_UART2] = &meson8b_uart2.hw,
+ [CLKID_SANA] = &meson8b_sana.hw,
+ [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw,
+ [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
+ [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw,
+ [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw,
+ [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw,
+ [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw,
+ [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw,
+ [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw,
+ [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw,
+ [CLKID_DAC_CLK] = &meson8b_dac_clk.hw,
+ [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw,
+ [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw,
+ [CLKID_ENC480P] = &meson8b_enc480p.hw,
+ [CLKID_RNG1] = &meson8b_rng1.hw,
+ [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw,
+ [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw,
+ [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw,
+ [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw,
+ [CLKID_EDP] = &meson8b_edp.hw,
+ [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw,
+ [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw,
+ [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw,
+ [CLKID_AO_IFACE] = &meson8b_ao_iface.hw,
+ [CLKID_MPLL0] = &meson8b_mpll0.hw,
+ [CLKID_MPLL1] = &meson8b_mpll1.hw,
+ [CLKID_MPLL2] = &meson8b_mpll2.hw,
+ [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
+ [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw,
+ [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw,
+ [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw,
+ [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw,
+ [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw,
+ [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw,
+ [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw,
+ [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw,
+ [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw,
+ [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw,
+ [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw,
+ [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw,
+ [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw,
+ [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw,
+ [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw,
+ [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw,
+ [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw,
+ [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw,
+ [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw,
+ [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw,
+ [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw,
+ [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw,
+ [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw,
+ [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw,
+ [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw,
+ [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw,
+ [CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw,
+ [CLKID_APB] = &meson8b_apb_clk_gate.hw,
+ [CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw,
+ [CLKID_PERIPH] = &meson8b_periph_clk_gate.hw,
+ [CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw,
+ [CLKID_AXI] = &meson8b_axi_clk_gate.hw,
+ [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw,
+ [CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw,
+ [CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw,
+ [CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw,
+ [CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw,
+ [CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw,
+ [CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw,
+ [CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw,
+ [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw,
+ [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
+ [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
+ [CLKID_VCLK_EN] = &meson8b_vclk_en.hw,
+ [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
+ [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
+ [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
+ [CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw,
+ [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw,
+ [CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw,
+ [CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw,
+ [CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw,
+ [CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
+ [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw,
+ [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw,
+ [CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw,
+ [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
+ [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw,
+ [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw,
+ [CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw,
+ [CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4_div_gate.hw,
+ [CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw,
+ [CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6_div_gate.hw,
+ [CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw,
+ [CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12_div_gate.hw,
+ [CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw,
+ [CLKID_CTS_ENCT] = &meson8b_cts_enct.hw,
+ [CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw,
+ [CLKID_CTS_ENCP] = &meson8b_cts_encp.hw,
+ [CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw,
+ [CLKID_CTS_ENCI] = &meson8b_cts_enci.hw,
+ [CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw,
+ [CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw,
+ [CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw,
+ [CLKID_CTS_ENCL] = &meson8b_cts_encl.hw,
+ [CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw,
+ [CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw,
+ [CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw,
+ [CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw,
+ [CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw,
+ [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw,
+ [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw,
+ [CLKID_MALI_0] = &meson8b_mali_0.hw,
+ [CLKID_MALI_1_SEL] = &meson8b_mali_1_sel.hw,
+ [CLKID_MALI_1_DIV] = &meson8b_mali_1_div.hw,
+ [CLKID_MALI_1] = &meson8b_mali_1.hw,
+ [CLKID_MALI] = &meson8b_mali.hw,
+ [CLKID_VPU_0_SEL] = &meson8b_vpu_0_sel.hw,
+ [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw,
+ [CLKID_VPU_0] = &meson8b_vpu_0.hw,
+ [CLKID_VPU_1_SEL] = &meson8b_vpu_1_sel.hw,
+ [CLKID_VPU_1_DIV] = &meson8b_vpu_1_div.hw,
+ [CLKID_VPU_1] = &meson8b_vpu_1.hw,
+ [CLKID_VPU] = &meson8b_vpu.hw,
+ [CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw,
+ [CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw,
+ [CLKID_VDEC_1_1] = &meson8b_vdec_1_1.hw,
+ [CLKID_VDEC_1_2_DIV] = &meson8b_vdec_1_2_div.hw,
+ [CLKID_VDEC_1_2] = &meson8b_vdec_1_2.hw,
+ [CLKID_VDEC_1] = &meson8b_vdec_1.hw,
+ [CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw,
+ [CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw,
+ [CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw,
+ [CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw,
+ [CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw,
+ [CLKID_VDEC_2] = &meson8b_vdec_2.hw,
+ [CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw,
+ [CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw,
+ [CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw,
+ [CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw,
+ [CLKID_CTS_AMCLK_SEL] = &meson8b_cts_amclk_sel.hw,
+ [CLKID_CTS_AMCLK_DIV] = &meson8b_cts_amclk_div.hw,
+ [CLKID_CTS_AMCLK] = &meson8b_cts_amclk.hw,
+ [CLKID_CTS_MCLK_I958_SEL] = &meson8b_cts_mclk_i958_sel.hw,
+ [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw,
+ [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw,
+ [CLKID_CTS_I958] = &meson8b_cts_i958.hw,
+ [CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw,
+ [CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw,
+};
+
+static struct clk_hw *meson8m2_hw_clks[] = {
+ [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
+ [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
+ [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
+ [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
+ [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
+ [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
+ [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
+ [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
+ [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
+ [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
+ [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
+ [CLKID_CLK81] = &meson8b_clk81.hw,
+ [CLKID_DDR] = &meson8b_ddr.hw,
+ [CLKID_DOS] = &meson8b_dos.hw,
+ [CLKID_ISA] = &meson8b_isa.hw,
+ [CLKID_PL301] = &meson8b_pl301.hw,
+ [CLKID_PERIPHS] = &meson8b_periphs.hw,
+ [CLKID_SPICC] = &meson8b_spicc.hw,
+ [CLKID_I2C] = &meson8b_i2c.hw,
+ [CLKID_SAR_ADC] = &meson8b_sar_adc.hw,
+ [CLKID_SMART_CARD] = &meson8b_smart_card.hw,
+ [CLKID_RNG0] = &meson8b_rng0.hw,
+ [CLKID_UART0] = &meson8b_uart0.hw,
+ [CLKID_SDHC] = &meson8b_sdhc.hw,
+ [CLKID_STREAM] = &meson8b_stream.hw,
+ [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw,
+ [CLKID_SDIO] = &meson8b_sdio.hw,
+ [CLKID_ABUF] = &meson8b_abuf.hw,
+ [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw,
+ [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw,
+ [CLKID_SPI] = &meson8b_spi.hw,
+ [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw,
+ [CLKID_ETH] = &meson8b_eth.hw,
+ [CLKID_DEMUX] = &meson8b_demux.hw,
+ [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw,
+ [CLKID_IEC958] = &meson8b_iec958.hw,
+ [CLKID_I2S_OUT] = &meson8b_i2s_out.hw,
+ [CLKID_AMCLK] = &meson8b_amclk.hw,
+ [CLKID_AIFIFO2] = &meson8b_aififo2.hw,
+ [CLKID_MIXER] = &meson8b_mixer.hw,
+ [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw,
+ [CLKID_ADC] = &meson8b_adc.hw,
+ [CLKID_BLKMV] = &meson8b_blkmv.hw,
+ [CLKID_AIU] = &meson8b_aiu.hw,
+ [CLKID_UART1] = &meson8b_uart1.hw,
+ [CLKID_G2D] = &meson8b_g2d.hw,
+ [CLKID_USB0] = &meson8b_usb0.hw,
+ [CLKID_USB1] = &meson8b_usb1.hw,
+ [CLKID_RESET] = &meson8b_reset.hw,
+ [CLKID_NAND] = &meson8b_nand.hw,
+ [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw,
+ [CLKID_USB] = &meson8b_usb.hw,
+ [CLKID_VDIN1] = &meson8b_vdin1.hw,
+ [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw,
+ [CLKID_EFUSE] = &meson8b_efuse.hw,
+ [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw,
+ [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw,
+ [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw,
+ [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw,
+ [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw,
+ [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw,
+ [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw,
+ [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw,
+ [CLKID_DVIN] = &meson8b_dvin.hw,
+ [CLKID_UART2] = &meson8b_uart2.hw,
+ [CLKID_SANA] = &meson8b_sana.hw,
+ [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw,
+ [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
+ [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw,
+ [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw,
+ [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw,
+ [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw,
+ [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw,
+ [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw,
+ [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw,
+ [CLKID_DAC_CLK] = &meson8b_dac_clk.hw,
+ [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw,
+ [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw,
+ [CLKID_ENC480P] = &meson8b_enc480p.hw,
+ [CLKID_RNG1] = &meson8b_rng1.hw,
+ [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw,
+ [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw,
+ [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw,
+ [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw,
+ [CLKID_EDP] = &meson8b_edp.hw,
+ [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw,
+ [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw,
+ [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw,
+ [CLKID_AO_IFACE] = &meson8b_ao_iface.hw,
+ [CLKID_MPLL0] = &meson8b_mpll0.hw,
+ [CLKID_MPLL1] = &meson8b_mpll1.hw,
+ [CLKID_MPLL2] = &meson8b_mpll2.hw,
+ [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
+ [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw,
+ [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw,
+ [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw,
+ [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw,
+ [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw,
+ [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw,
+ [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw,
+ [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw,
+ [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw,
+ [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw,
+ [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw,
+ [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw,
+ [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw,
+ [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw,
+ [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw,
+ [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw,
+ [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw,
+ [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw,
+ [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw,
+ [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw,
+ [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw,
+ [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw,
+ [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw,
+ [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw,
+ [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw,
+ [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw,
+ [CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw,
+ [CLKID_APB] = &meson8b_apb_clk_gate.hw,
+ [CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw,
+ [CLKID_PERIPH] = &meson8b_periph_clk_gate.hw,
+ [CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw,
+ [CLKID_AXI] = &meson8b_axi_clk_gate.hw,
+ [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw,
+ [CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw,
+ [CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw,
+ [CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw,
+ [CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw,
+ [CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw,
+ [CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw,
+ [CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw,
+ [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw,
+ [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
+ [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
+ [CLKID_VCLK_EN] = &meson8b_vclk_en.hw,
+ [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
+ [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
+ [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
+ [CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw,
+ [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw,
+ [CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw,
+ [CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw,
+ [CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw,
+ [CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
+ [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw,
+ [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw,
+ [CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw,
+ [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
+ [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw,
+ [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw,
+ [CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw,
+ [CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4_div_gate.hw,
+ [CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw,
+ [CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6_div_gate.hw,
+ [CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw,
+ [CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12_div_gate.hw,
+ [CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw,
+ [CLKID_CTS_ENCT] = &meson8b_cts_enct.hw,
+ [CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw,
+ [CLKID_CTS_ENCP] = &meson8b_cts_encp.hw,
+ [CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw,
+ [CLKID_CTS_ENCI] = &meson8b_cts_enci.hw,
+ [CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw,
+ [CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw,
+ [CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw,
+ [CLKID_CTS_ENCL] = &meson8b_cts_encl.hw,
+ [CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw,
+ [CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw,
+ [CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw,
+ [CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw,
+ [CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw,
+ [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw,
+ [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw,
+ [CLKID_MALI_0] = &meson8b_mali_0.hw,
+ [CLKID_MALI_1_SEL] = &meson8b_mali_1_sel.hw,
+ [CLKID_MALI_1_DIV] = &meson8b_mali_1_div.hw,
+ [CLKID_MALI_1] = &meson8b_mali_1.hw,
+ [CLKID_MALI] = &meson8b_mali.hw,
+ [CLKID_GP_PLL_DCO] = &meson8m2_gp_pll_dco.hw,
+ [CLKID_GP_PLL] = &meson8m2_gp_pll.hw,
+ [CLKID_VPU_0_SEL] = &meson8m2_vpu_0_sel.hw,
+ [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw,
+ [CLKID_VPU_0] = &meson8b_vpu_0.hw,
+ [CLKID_VPU_1_SEL] = &meson8m2_vpu_1_sel.hw,
+ [CLKID_VPU_1_DIV] = &meson8b_vpu_1_div.hw,
+ [CLKID_VPU_1] = &meson8b_vpu_1.hw,
+ [CLKID_VPU] = &meson8b_vpu.hw,
+ [CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw,
+ [CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw,
+ [CLKID_VDEC_1_1] = &meson8b_vdec_1_1.hw,
+ [CLKID_VDEC_1_2_DIV] = &meson8b_vdec_1_2_div.hw,
+ [CLKID_VDEC_1_2] = &meson8b_vdec_1_2.hw,
+ [CLKID_VDEC_1] = &meson8b_vdec_1.hw,
+ [CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw,
+ [CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw,
+ [CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw,
+ [CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw,
+ [CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw,
+ [CLKID_VDEC_2] = &meson8b_vdec_2.hw,
+ [CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw,
+ [CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw,
+ [CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw,
+ [CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw,
+ [CLKID_CTS_AMCLK_SEL] = &meson8b_cts_amclk_sel.hw,
+ [CLKID_CTS_AMCLK_DIV] = &meson8b_cts_amclk_div.hw,
+ [CLKID_CTS_AMCLK] = &meson8b_cts_amclk.hw,
+ [CLKID_CTS_MCLK_I958_SEL] = &meson8b_cts_mclk_i958_sel.hw,
+ [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw,
+ [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw,
+ [CLKID_CTS_I958] = &meson8b_cts_i958.hw,
+ [CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw,
+ [CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw,
};
static struct clk_regmap *const meson8b_clk_regmaps[] = {
@@ -3788,8 +3776,41 @@ static struct meson8b_nb_data meson8b_cpu_nb_data = {
.nb.notifier_call = meson8b_cpu_clk_notifier_cb,
};
+struct meson8b_clks {
+ struct clk_hw **hw_clks;
+ unsigned int hw_clk_num;
+};
+
+static struct meson8b_clks meson8_clks = {
+ .hw_clks = meson8_hw_clks,
+ .hw_clk_num = ARRAY_SIZE(meson8_hw_clks),
+};
+
+static struct meson8b_clks meson8b_clks = {
+ .hw_clks = meson8b_hw_clks,
+ .hw_clk_num = ARRAY_SIZE(meson8b_hw_clks),
+};
+
+static struct meson8b_clks meson8m2_clks = {
+ .hw_clks = meson8m2_hw_clks,
+ .hw_clk_num = ARRAY_SIZE(meson8m2_hw_clks),
+};
+
+static struct clk_hw *meson8b_hw_get(struct of_phandle_args *clkspec, void *clk_data)
+{
+ const struct meson8b_clks *data = clk_data;
+ unsigned int idx = clkspec->args[0];
+
+ if (idx >= data->hw_clk_num) {
+ pr_err("%s: invalid index %u\n", __func__, idx);
+ return ERR_PTR(-EINVAL);
+ }
+
+ return data->hw_clks[idx];
+}
+
static void __init meson8b_clkc_init_common(struct device_node *np,
- struct clk_hw_onecell_data *clk_hw_onecell_data)
+ struct meson8b_clks *clks)
{
struct meson8b_clk_reset *rstc;
struct device_node *parent_np;
@@ -3830,17 +3851,17 @@ static void __init meson8b_clkc_init_common(struct device_node *np,
* register all clks and start with the first used ID (which is
* CLKID_PLL_FIXED)
*/
- for (i = CLKID_PLL_FIXED; i < CLK_NR_CLKS; i++) {
+ for (i = CLKID_PLL_FIXED; i < clks->hw_clk_num; i++) {
/* array might be sparse */
- if (!clk_hw_onecell_data->hws[i])
+ if (!clks->hw_clks[i])
continue;
- ret = of_clk_hw_register(np, clk_hw_onecell_data->hws[i]);
+ ret = of_clk_hw_register(np, clks->hw_clks[i]);
if (ret)
return;
}
- meson8b_cpu_nb_data.cpu_clk = clk_hw_onecell_data->hws[CLKID_CPUCLK];
+ meson8b_cpu_nb_data.cpu_clk = clks->hw_clks[CLKID_CPUCLK];
/*
* FIXME we shouldn't program the muxes in notifier handlers. The
@@ -3856,25 +3877,24 @@ static void __init meson8b_clkc_init_common(struct device_node *np,
return;
}
- ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
- clk_hw_onecell_data);
+ ret = of_clk_add_hw_provider(np, meson8b_hw_get, clks);
if (ret)
pr_err("%s: failed to register clock provider\n", __func__);
}
static void __init meson8_clkc_init(struct device_node *np)
{
- return meson8b_clkc_init_common(np, &meson8_hw_onecell_data);
+ return meson8b_clkc_init_common(np, &meson8_clks);
}
static void __init meson8b_clkc_init(struct device_node *np)
{
- return meson8b_clkc_init_common(np, &meson8b_hw_onecell_data);
+ return meson8b_clkc_init_common(np, &meson8b_clks);
}
static void __init meson8m2_clkc_init(struct device_node *np)
{
- return meson8b_clkc_init_common(np, &meson8m2_hw_onecell_data);
+ return meson8b_clkc_init_common(np, &meson8m2_clks);
}
CLK_OF_DECLARE_DRIVER(meson8_clkc, "amlogic,meson8-clkc",
diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index ce62ed47cbfc..f999655d4436 100644
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -185,8 +185,6 @@
#define CLKID_VID_PLL_LVDS_EN 216
#define CLKID_HDMI_PLL_DCO_IN 217
-#define CLK_NR_CLKS 218
-
/*
* include the CLKID and RESETID that have
* been made part of the stable DT binding
--
2.34.1
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 05/18] clk: meson: migrate axg-audio out of hw_onecell_data to drop NR_CLKS
2023-06-07 10:56 [PATCH 00/18] clk: meson: move all private clk IDs to public dt-bindings headers Neil Armstrong
` (2 preceding siblings ...)
2023-06-07 10:56 ` [PATCH 04/18] clk: meson: migrate meson8b " Neil Armstrong
@ 2023-06-07 10:56 ` Neil Armstrong
2023-06-07 10:56 ` [PATCH 06/18] dt-bindings: clk: gxbb-clkc: expose all clock ids Neil Armstrong
` (12 subsequent siblings)
16 siblings, 0 replies; 35+ messages in thread
From: Neil Armstrong @ 2023-06-07 10:56 UTC (permalink / raw)
To: Jerome Brunet, Michael Turquette, Stephen Boyd, Kevin Hilman,
Martin Blumenstingl, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-amlogic, linux-clk, linux-arm-kernel, linux-kernel,
devicetree, Neil Armstrong
The way hw_onecell_data is declared:
struct clk_hw_onecell_data {
unsigned int num;
struct clk_hw *hws[];
};
makes it impossible to have the clk_hw table declared outside while
using ARRAY_SIZE() to determine ".num" due to ".hws" being a flexible
array member.
Completely move out of hw_onecell_data and add a custom
devm_of_clk_add_hw_provider() "get" callback to retrieve the clk_hw
in order to finally get rid on the NR_CLKS define.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
drivers/clk/meson/axg-audio.c | 856 +++++++++++++++++++++---------------------
drivers/clk/meson/axg-audio.h | 2 -
2 files changed, 430 insertions(+), 428 deletions(-)
diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c
index 5016682e47c8..ef4e0552f77c 100644
--- a/drivers/clk/meson/axg-audio.c
+++ b/drivers/clk/meson/axg-audio.c
@@ -811,436 +811,424 @@ static struct clk_regmap sm1_tdm_sclk_pad_2 = AUD_TDM_PAD_CTRL(
* Array of all clocks provided by this provider
* The input clocks of the controller will be populated at runtime
*/
-static struct clk_hw_onecell_data axg_audio_hw_onecell_data = {
- .hws = {
- [AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
- [AUD_CLKID_PDM] = &pdm.hw,
- [AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
- [AUD_CLKID_TDMIN_B] = &tdmin_b.hw,
- [AUD_CLKID_TDMIN_C] = &tdmin_c.hw,
- [AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw,
- [AUD_CLKID_TDMOUT_A] = &tdmout_a.hw,
- [AUD_CLKID_TDMOUT_B] = &tdmout_b.hw,
- [AUD_CLKID_TDMOUT_C] = &tdmout_c.hw,
- [AUD_CLKID_FRDDR_A] = &frddr_a.hw,
- [AUD_CLKID_FRDDR_B] = &frddr_b.hw,
- [AUD_CLKID_FRDDR_C] = &frddr_c.hw,
- [AUD_CLKID_TODDR_A] = &toddr_a.hw,
- [AUD_CLKID_TODDR_B] = &toddr_b.hw,
- [AUD_CLKID_TODDR_C] = &toddr_c.hw,
- [AUD_CLKID_LOOPBACK] = &loopback.hw,
- [AUD_CLKID_SPDIFIN] = &spdifin.hw,
- [AUD_CLKID_SPDIFOUT] = &spdifout.hw,
- [AUD_CLKID_RESAMPLE] = &resample.hw,
- [AUD_CLKID_POWER_DETECT] = &power_detect.hw,
- [AUD_CLKID_MST_A_MCLK_SEL] = &mst_a_mclk_sel.hw,
- [AUD_CLKID_MST_B_MCLK_SEL] = &mst_b_mclk_sel.hw,
- [AUD_CLKID_MST_C_MCLK_SEL] = &mst_c_mclk_sel.hw,
- [AUD_CLKID_MST_D_MCLK_SEL] = &mst_d_mclk_sel.hw,
- [AUD_CLKID_MST_E_MCLK_SEL] = &mst_e_mclk_sel.hw,
- [AUD_CLKID_MST_F_MCLK_SEL] = &mst_f_mclk_sel.hw,
- [AUD_CLKID_MST_A_MCLK_DIV] = &mst_a_mclk_div.hw,
- [AUD_CLKID_MST_B_MCLK_DIV] = &mst_b_mclk_div.hw,
- [AUD_CLKID_MST_C_MCLK_DIV] = &mst_c_mclk_div.hw,
- [AUD_CLKID_MST_D_MCLK_DIV] = &mst_d_mclk_div.hw,
- [AUD_CLKID_MST_E_MCLK_DIV] = &mst_e_mclk_div.hw,
- [AUD_CLKID_MST_F_MCLK_DIV] = &mst_f_mclk_div.hw,
- [AUD_CLKID_MST_A_MCLK] = &mst_a_mclk.hw,
- [AUD_CLKID_MST_B_MCLK] = &mst_b_mclk.hw,
- [AUD_CLKID_MST_C_MCLK] = &mst_c_mclk.hw,
- [AUD_CLKID_MST_D_MCLK] = &mst_d_mclk.hw,
- [AUD_CLKID_MST_E_MCLK] = &mst_e_mclk.hw,
- [AUD_CLKID_MST_F_MCLK] = &mst_f_mclk.hw,
- [AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw,
- [AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw,
- [AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw,
- [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
- [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
- [AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw,
- [AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw,
- [AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw,
- [AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw,
- [AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw,
- [AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw,
- [AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw,
- [AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw,
- [AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw,
- [AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw,
- [AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw,
- [AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw,
- [AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw,
- [AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw,
- [AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw,
- [AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw,
- [AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw,
- [AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw,
- [AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw,
- [AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw,
- [AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw,
- [AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw,
- [AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw,
- [AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw,
- [AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw,
- [AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw,
- [AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw,
- [AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw,
- [AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw,
- [AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw,
- [AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw,
- [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
- [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
- [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
- [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
- [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
- [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
- [AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw,
- [AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw,
- [AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw,
- [AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw,
- [AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw,
- [AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw,
- [AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw,
- [AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw,
- [AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw,
- [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw,
- [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw,
- [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw,
- [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw,
- [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
- [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
- [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
- [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
- [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
- [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
- [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
- [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
- [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
- [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
- [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
- [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
- [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
- [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
- [AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw,
- [AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
- [AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
- [AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
- [AUD_CLKID_TDMOUT_A_SCLK] = &axg_tdmout_a_sclk.hw,
- [AUD_CLKID_TDMOUT_B_SCLK] = &axg_tdmout_b_sclk.hw,
- [AUD_CLKID_TDMOUT_C_SCLK] = &axg_tdmout_c_sclk.hw,
- [AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
- [AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
- [AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
- [AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw,
- [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw,
- [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
- [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
- [AUD_CLKID_TOP] = &axg_aud_top,
- [NR_CLKS] = NULL,
- },
- .num = NR_CLKS,
+static struct clk_hw *axg_audio_hw_clks[] = {
+ [AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
+ [AUD_CLKID_PDM] = &pdm.hw,
+ [AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
+ [AUD_CLKID_TDMIN_B] = &tdmin_b.hw,
+ [AUD_CLKID_TDMIN_C] = &tdmin_c.hw,
+ [AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw,
+ [AUD_CLKID_TDMOUT_A] = &tdmout_a.hw,
+ [AUD_CLKID_TDMOUT_B] = &tdmout_b.hw,
+ [AUD_CLKID_TDMOUT_C] = &tdmout_c.hw,
+ [AUD_CLKID_FRDDR_A] = &frddr_a.hw,
+ [AUD_CLKID_FRDDR_B] = &frddr_b.hw,
+ [AUD_CLKID_FRDDR_C] = &frddr_c.hw,
+ [AUD_CLKID_TODDR_A] = &toddr_a.hw,
+ [AUD_CLKID_TODDR_B] = &toddr_b.hw,
+ [AUD_CLKID_TODDR_C] = &toddr_c.hw,
+ [AUD_CLKID_LOOPBACK] = &loopback.hw,
+ [AUD_CLKID_SPDIFIN] = &spdifin.hw,
+ [AUD_CLKID_SPDIFOUT] = &spdifout.hw,
+ [AUD_CLKID_RESAMPLE] = &resample.hw,
+ [AUD_CLKID_POWER_DETECT] = &power_detect.hw,
+ [AUD_CLKID_MST_A_MCLK_SEL] = &mst_a_mclk_sel.hw,
+ [AUD_CLKID_MST_B_MCLK_SEL] = &mst_b_mclk_sel.hw,
+ [AUD_CLKID_MST_C_MCLK_SEL] = &mst_c_mclk_sel.hw,
+ [AUD_CLKID_MST_D_MCLK_SEL] = &mst_d_mclk_sel.hw,
+ [AUD_CLKID_MST_E_MCLK_SEL] = &mst_e_mclk_sel.hw,
+ [AUD_CLKID_MST_F_MCLK_SEL] = &mst_f_mclk_sel.hw,
+ [AUD_CLKID_MST_A_MCLK_DIV] = &mst_a_mclk_div.hw,
+ [AUD_CLKID_MST_B_MCLK_DIV] = &mst_b_mclk_div.hw,
+ [AUD_CLKID_MST_C_MCLK_DIV] = &mst_c_mclk_div.hw,
+ [AUD_CLKID_MST_D_MCLK_DIV] = &mst_d_mclk_div.hw,
+ [AUD_CLKID_MST_E_MCLK_DIV] = &mst_e_mclk_div.hw,
+ [AUD_CLKID_MST_F_MCLK_DIV] = &mst_f_mclk_div.hw,
+ [AUD_CLKID_MST_A_MCLK] = &mst_a_mclk.hw,
+ [AUD_CLKID_MST_B_MCLK] = &mst_b_mclk.hw,
+ [AUD_CLKID_MST_C_MCLK] = &mst_c_mclk.hw,
+ [AUD_CLKID_MST_D_MCLK] = &mst_d_mclk.hw,
+ [AUD_CLKID_MST_E_MCLK] = &mst_e_mclk.hw,
+ [AUD_CLKID_MST_F_MCLK] = &mst_f_mclk.hw,
+ [AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw,
+ [AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw,
+ [AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw,
+ [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
+ [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
+ [AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw,
+ [AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw,
+ [AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw,
+ [AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw,
+ [AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw,
+ [AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw,
+ [AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw,
+ [AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw,
+ [AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw,
+ [AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw,
+ [AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw,
+ [AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw,
+ [AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw,
+ [AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw,
+ [AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw,
+ [AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw,
+ [AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw,
+ [AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw,
+ [AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw,
+ [AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw,
+ [AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw,
+ [AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw,
+ [AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw,
+ [AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw,
+ [AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw,
+ [AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw,
+ [AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw,
+ [AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw,
+ [AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw,
+ [AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw,
+ [AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw,
+ [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
+ [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
+ [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
+ [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
+ [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
+ [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
+ [AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw,
+ [AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw,
+ [AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw,
+ [AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw,
+ [AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw,
+ [AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw,
+ [AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw,
+ [AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw,
+ [AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw,
+ [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw,
+ [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw,
+ [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw,
+ [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw,
+ [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
+ [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
+ [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
+ [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
+ [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
+ [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
+ [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
+ [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
+ [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
+ [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
+ [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
+ [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
+ [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
+ [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
+ [AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw,
+ [AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
+ [AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
+ [AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
+ [AUD_CLKID_TDMOUT_A_SCLK] = &axg_tdmout_a_sclk.hw,
+ [AUD_CLKID_TDMOUT_B_SCLK] = &axg_tdmout_b_sclk.hw,
+ [AUD_CLKID_TDMOUT_C_SCLK] = &axg_tdmout_c_sclk.hw,
+ [AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
+ [AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
+ [AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
+ [AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw,
+ [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw,
+ [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
+ [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
+ [AUD_CLKID_TOP] = &axg_aud_top,
};
/*
* Array of all G12A clocks provided by this provider
* The input clocks of the controller will be populated at runtime
*/
-static struct clk_hw_onecell_data g12a_audio_hw_onecell_data = {
- .hws = {
- [AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
- [AUD_CLKID_PDM] = &pdm.hw,
- [AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
- [AUD_CLKID_TDMIN_B] = &tdmin_b.hw,
- [AUD_CLKID_TDMIN_C] = &tdmin_c.hw,
- [AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw,
- [AUD_CLKID_TDMOUT_A] = &tdmout_a.hw,
- [AUD_CLKID_TDMOUT_B] = &tdmout_b.hw,
- [AUD_CLKID_TDMOUT_C] = &tdmout_c.hw,
- [AUD_CLKID_FRDDR_A] = &frddr_a.hw,
- [AUD_CLKID_FRDDR_B] = &frddr_b.hw,
- [AUD_CLKID_FRDDR_C] = &frddr_c.hw,
- [AUD_CLKID_TODDR_A] = &toddr_a.hw,
- [AUD_CLKID_TODDR_B] = &toddr_b.hw,
- [AUD_CLKID_TODDR_C] = &toddr_c.hw,
- [AUD_CLKID_LOOPBACK] = &loopback.hw,
- [AUD_CLKID_SPDIFIN] = &spdifin.hw,
- [AUD_CLKID_SPDIFOUT] = &spdifout.hw,
- [AUD_CLKID_RESAMPLE] = &resample.hw,
- [AUD_CLKID_POWER_DETECT] = &power_detect.hw,
- [AUD_CLKID_SPDIFOUT_B] = &spdifout_b.hw,
- [AUD_CLKID_MST_A_MCLK_SEL] = &mst_a_mclk_sel.hw,
- [AUD_CLKID_MST_B_MCLK_SEL] = &mst_b_mclk_sel.hw,
- [AUD_CLKID_MST_C_MCLK_SEL] = &mst_c_mclk_sel.hw,
- [AUD_CLKID_MST_D_MCLK_SEL] = &mst_d_mclk_sel.hw,
- [AUD_CLKID_MST_E_MCLK_SEL] = &mst_e_mclk_sel.hw,
- [AUD_CLKID_MST_F_MCLK_SEL] = &mst_f_mclk_sel.hw,
- [AUD_CLKID_MST_A_MCLK_DIV] = &mst_a_mclk_div.hw,
- [AUD_CLKID_MST_B_MCLK_DIV] = &mst_b_mclk_div.hw,
- [AUD_CLKID_MST_C_MCLK_DIV] = &mst_c_mclk_div.hw,
- [AUD_CLKID_MST_D_MCLK_DIV] = &mst_d_mclk_div.hw,
- [AUD_CLKID_MST_E_MCLK_DIV] = &mst_e_mclk_div.hw,
- [AUD_CLKID_MST_F_MCLK_DIV] = &mst_f_mclk_div.hw,
- [AUD_CLKID_MST_A_MCLK] = &mst_a_mclk.hw,
- [AUD_CLKID_MST_B_MCLK] = &mst_b_mclk.hw,
- [AUD_CLKID_MST_C_MCLK] = &mst_c_mclk.hw,
- [AUD_CLKID_MST_D_MCLK] = &mst_d_mclk.hw,
- [AUD_CLKID_MST_E_MCLK] = &mst_e_mclk.hw,
- [AUD_CLKID_MST_F_MCLK] = &mst_f_mclk.hw,
- [AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw,
- [AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw,
- [AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw,
- [AUD_CLKID_SPDIFOUT_B_CLK_SEL] = &spdifout_b_clk_sel.hw,
- [AUD_CLKID_SPDIFOUT_B_CLK_DIV] = &spdifout_b_clk_div.hw,
- [AUD_CLKID_SPDIFOUT_B_CLK] = &spdifout_b_clk.hw,
- [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
- [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
- [AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw,
- [AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw,
- [AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw,
- [AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw,
- [AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw,
- [AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw,
- [AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw,
- [AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw,
- [AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw,
- [AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw,
- [AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw,
- [AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw,
- [AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw,
- [AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw,
- [AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw,
- [AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw,
- [AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw,
- [AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw,
- [AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw,
- [AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw,
- [AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw,
- [AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw,
- [AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw,
- [AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw,
- [AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw,
- [AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw,
- [AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw,
- [AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw,
- [AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw,
- [AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw,
- [AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw,
- [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
- [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
- [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
- [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
- [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
- [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
- [AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw,
- [AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw,
- [AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw,
- [AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw,
- [AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw,
- [AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw,
- [AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw,
- [AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw,
- [AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw,
- [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw,
- [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw,
- [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw,
- [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw,
- [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
- [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
- [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
- [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
- [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
- [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
- [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
- [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
- [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
- [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
- [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
- [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
- [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
- [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
- [AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw,
- [AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
- [AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
- [AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
- [AUD_CLKID_TDMOUT_A_SCLK] = &g12a_tdmout_a_sclk.hw,
- [AUD_CLKID_TDMOUT_B_SCLK] = &g12a_tdmout_b_sclk.hw,
- [AUD_CLKID_TDMOUT_C_SCLK] = &g12a_tdmout_c_sclk.hw,
- [AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
- [AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
- [AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
- [AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw,
- [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw,
- [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
- [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
- [AUD_CLKID_TDM_MCLK_PAD0] = &g12a_tdm_mclk_pad_0.hw,
- [AUD_CLKID_TDM_MCLK_PAD1] = &g12a_tdm_mclk_pad_1.hw,
- [AUD_CLKID_TDM_LRCLK_PAD0] = &g12a_tdm_lrclk_pad_0.hw,
- [AUD_CLKID_TDM_LRCLK_PAD1] = &g12a_tdm_lrclk_pad_1.hw,
- [AUD_CLKID_TDM_LRCLK_PAD2] = &g12a_tdm_lrclk_pad_2.hw,
- [AUD_CLKID_TDM_SCLK_PAD0] = &g12a_tdm_sclk_pad_0.hw,
- [AUD_CLKID_TDM_SCLK_PAD1] = &g12a_tdm_sclk_pad_1.hw,
- [AUD_CLKID_TDM_SCLK_PAD2] = &g12a_tdm_sclk_pad_2.hw,
- [AUD_CLKID_TOP] = &axg_aud_top,
- [NR_CLKS] = NULL,
- },
- .num = NR_CLKS,
+static struct clk_hw *g12a_audio_hw_clks[] = {
+ [AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
+ [AUD_CLKID_PDM] = &pdm.hw,
+ [AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
+ [AUD_CLKID_TDMIN_B] = &tdmin_b.hw,
+ [AUD_CLKID_TDMIN_C] = &tdmin_c.hw,
+ [AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw,
+ [AUD_CLKID_TDMOUT_A] = &tdmout_a.hw,
+ [AUD_CLKID_TDMOUT_B] = &tdmout_b.hw,
+ [AUD_CLKID_TDMOUT_C] = &tdmout_c.hw,
+ [AUD_CLKID_FRDDR_A] = &frddr_a.hw,
+ [AUD_CLKID_FRDDR_B] = &frddr_b.hw,
+ [AUD_CLKID_FRDDR_C] = &frddr_c.hw,
+ [AUD_CLKID_TODDR_A] = &toddr_a.hw,
+ [AUD_CLKID_TODDR_B] = &toddr_b.hw,
+ [AUD_CLKID_TODDR_C] = &toddr_c.hw,
+ [AUD_CLKID_LOOPBACK] = &loopback.hw,
+ [AUD_CLKID_SPDIFIN] = &spdifin.hw,
+ [AUD_CLKID_SPDIFOUT] = &spdifout.hw,
+ [AUD_CLKID_RESAMPLE] = &resample.hw,
+ [AUD_CLKID_POWER_DETECT] = &power_detect.hw,
+ [AUD_CLKID_SPDIFOUT_B] = &spdifout_b.hw,
+ [AUD_CLKID_MST_A_MCLK_SEL] = &mst_a_mclk_sel.hw,
+ [AUD_CLKID_MST_B_MCLK_SEL] = &mst_b_mclk_sel.hw,
+ [AUD_CLKID_MST_C_MCLK_SEL] = &mst_c_mclk_sel.hw,
+ [AUD_CLKID_MST_D_MCLK_SEL] = &mst_d_mclk_sel.hw,
+ [AUD_CLKID_MST_E_MCLK_SEL] = &mst_e_mclk_sel.hw,
+ [AUD_CLKID_MST_F_MCLK_SEL] = &mst_f_mclk_sel.hw,
+ [AUD_CLKID_MST_A_MCLK_DIV] = &mst_a_mclk_div.hw,
+ [AUD_CLKID_MST_B_MCLK_DIV] = &mst_b_mclk_div.hw,
+ [AUD_CLKID_MST_C_MCLK_DIV] = &mst_c_mclk_div.hw,
+ [AUD_CLKID_MST_D_MCLK_DIV] = &mst_d_mclk_div.hw,
+ [AUD_CLKID_MST_E_MCLK_DIV] = &mst_e_mclk_div.hw,
+ [AUD_CLKID_MST_F_MCLK_DIV] = &mst_f_mclk_div.hw,
+ [AUD_CLKID_MST_A_MCLK] = &mst_a_mclk.hw,
+ [AUD_CLKID_MST_B_MCLK] = &mst_b_mclk.hw,
+ [AUD_CLKID_MST_C_MCLK] = &mst_c_mclk.hw,
+ [AUD_CLKID_MST_D_MCLK] = &mst_d_mclk.hw,
+ [AUD_CLKID_MST_E_MCLK] = &mst_e_mclk.hw,
+ [AUD_CLKID_MST_F_MCLK] = &mst_f_mclk.hw,
+ [AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw,
+ [AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw,
+ [AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw,
+ [AUD_CLKID_SPDIFOUT_B_CLK_SEL] = &spdifout_b_clk_sel.hw,
+ [AUD_CLKID_SPDIFOUT_B_CLK_DIV] = &spdifout_b_clk_div.hw,
+ [AUD_CLKID_SPDIFOUT_B_CLK] = &spdifout_b_clk.hw,
+ [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
+ [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
+ [AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw,
+ [AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw,
+ [AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw,
+ [AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw,
+ [AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw,
+ [AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw,
+ [AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw,
+ [AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw,
+ [AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw,
+ [AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw,
+ [AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw,
+ [AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw,
+ [AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw,
+ [AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw,
+ [AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw,
+ [AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw,
+ [AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw,
+ [AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw,
+ [AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw,
+ [AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw,
+ [AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw,
+ [AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw,
+ [AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw,
+ [AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw,
+ [AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw,
+ [AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw,
+ [AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw,
+ [AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw,
+ [AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw,
+ [AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw,
+ [AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw,
+ [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
+ [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
+ [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
+ [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
+ [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
+ [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
+ [AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw,
+ [AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw,
+ [AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw,
+ [AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw,
+ [AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw,
+ [AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw,
+ [AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw,
+ [AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw,
+ [AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw,
+ [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw,
+ [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw,
+ [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw,
+ [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw,
+ [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
+ [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
+ [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
+ [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
+ [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
+ [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
+ [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
+ [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
+ [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
+ [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
+ [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
+ [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
+ [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
+ [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
+ [AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw,
+ [AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
+ [AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
+ [AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
+ [AUD_CLKID_TDMOUT_A_SCLK] = &g12a_tdmout_a_sclk.hw,
+ [AUD_CLKID_TDMOUT_B_SCLK] = &g12a_tdmout_b_sclk.hw,
+ [AUD_CLKID_TDMOUT_C_SCLK] = &g12a_tdmout_c_sclk.hw,
+ [AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
+ [AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
+ [AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
+ [AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw,
+ [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw,
+ [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
+ [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
+ [AUD_CLKID_TDM_MCLK_PAD0] = &g12a_tdm_mclk_pad_0.hw,
+ [AUD_CLKID_TDM_MCLK_PAD1] = &g12a_tdm_mclk_pad_1.hw,
+ [AUD_CLKID_TDM_LRCLK_PAD0] = &g12a_tdm_lrclk_pad_0.hw,
+ [AUD_CLKID_TDM_LRCLK_PAD1] = &g12a_tdm_lrclk_pad_1.hw,
+ [AUD_CLKID_TDM_LRCLK_PAD2] = &g12a_tdm_lrclk_pad_2.hw,
+ [AUD_CLKID_TDM_SCLK_PAD0] = &g12a_tdm_sclk_pad_0.hw,
+ [AUD_CLKID_TDM_SCLK_PAD1] = &g12a_tdm_sclk_pad_1.hw,
+ [AUD_CLKID_TDM_SCLK_PAD2] = &g12a_tdm_sclk_pad_2.hw,
+ [AUD_CLKID_TOP] = &axg_aud_top,
};
/*
* Array of all SM1 clocks provided by this provider
* The input clocks of the controller will be populated at runtime
*/
-static struct clk_hw_onecell_data sm1_audio_hw_onecell_data = {
- .hws = {
- [AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
- [AUD_CLKID_PDM] = &pdm.hw,
- [AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
- [AUD_CLKID_TDMIN_B] = &tdmin_b.hw,
- [AUD_CLKID_TDMIN_C] = &tdmin_c.hw,
- [AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw,
- [AUD_CLKID_TDMOUT_A] = &tdmout_a.hw,
- [AUD_CLKID_TDMOUT_B] = &tdmout_b.hw,
- [AUD_CLKID_TDMOUT_C] = &tdmout_c.hw,
- [AUD_CLKID_FRDDR_A] = &frddr_a.hw,
- [AUD_CLKID_FRDDR_B] = &frddr_b.hw,
- [AUD_CLKID_FRDDR_C] = &frddr_c.hw,
- [AUD_CLKID_TODDR_A] = &toddr_a.hw,
- [AUD_CLKID_TODDR_B] = &toddr_b.hw,
- [AUD_CLKID_TODDR_C] = &toddr_c.hw,
- [AUD_CLKID_LOOPBACK] = &loopback.hw,
- [AUD_CLKID_SPDIFIN] = &spdifin.hw,
- [AUD_CLKID_SPDIFOUT] = &spdifout.hw,
- [AUD_CLKID_RESAMPLE] = &resample.hw,
- [AUD_CLKID_SPDIFOUT_B] = &spdifout_b.hw,
- [AUD_CLKID_MST_A_MCLK_SEL] = &sm1_mst_a_mclk_sel.hw,
- [AUD_CLKID_MST_B_MCLK_SEL] = &sm1_mst_b_mclk_sel.hw,
- [AUD_CLKID_MST_C_MCLK_SEL] = &sm1_mst_c_mclk_sel.hw,
- [AUD_CLKID_MST_D_MCLK_SEL] = &sm1_mst_d_mclk_sel.hw,
- [AUD_CLKID_MST_E_MCLK_SEL] = &sm1_mst_e_mclk_sel.hw,
- [AUD_CLKID_MST_F_MCLK_SEL] = &sm1_mst_f_mclk_sel.hw,
- [AUD_CLKID_MST_A_MCLK_DIV] = &sm1_mst_a_mclk_div.hw,
- [AUD_CLKID_MST_B_MCLK_DIV] = &sm1_mst_b_mclk_div.hw,
- [AUD_CLKID_MST_C_MCLK_DIV] = &sm1_mst_c_mclk_div.hw,
- [AUD_CLKID_MST_D_MCLK_DIV] = &sm1_mst_d_mclk_div.hw,
- [AUD_CLKID_MST_E_MCLK_DIV] = &sm1_mst_e_mclk_div.hw,
- [AUD_CLKID_MST_F_MCLK_DIV] = &sm1_mst_f_mclk_div.hw,
- [AUD_CLKID_MST_A_MCLK] = &sm1_mst_a_mclk.hw,
- [AUD_CLKID_MST_B_MCLK] = &sm1_mst_b_mclk.hw,
- [AUD_CLKID_MST_C_MCLK] = &sm1_mst_c_mclk.hw,
- [AUD_CLKID_MST_D_MCLK] = &sm1_mst_d_mclk.hw,
- [AUD_CLKID_MST_E_MCLK] = &sm1_mst_e_mclk.hw,
- [AUD_CLKID_MST_F_MCLK] = &sm1_mst_f_mclk.hw,
- [AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw,
- [AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw,
- [AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw,
- [AUD_CLKID_SPDIFOUT_B_CLK_SEL] = &spdifout_b_clk_sel.hw,
- [AUD_CLKID_SPDIFOUT_B_CLK_DIV] = &spdifout_b_clk_div.hw,
- [AUD_CLKID_SPDIFOUT_B_CLK] = &spdifout_b_clk.hw,
- [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
- [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
- [AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw,
- [AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw,
- [AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw,
- [AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw,
- [AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw,
- [AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw,
- [AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw,
- [AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw,
- [AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw,
- [AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw,
- [AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw,
- [AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw,
- [AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw,
- [AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw,
- [AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw,
- [AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw,
- [AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw,
- [AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw,
- [AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw,
- [AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw,
- [AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw,
- [AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw,
- [AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw,
- [AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw,
- [AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw,
- [AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw,
- [AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw,
- [AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw,
- [AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw,
- [AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw,
- [AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw,
- [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
- [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
- [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
- [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
- [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
- [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
- [AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw,
- [AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw,
- [AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw,
- [AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw,
- [AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw,
- [AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw,
- [AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw,
- [AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw,
- [AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw,
- [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw,
- [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw,
- [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw,
- [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw,
- [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
- [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
- [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
- [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
- [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
- [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
- [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
- [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
- [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
- [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
- [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
- [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
- [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
- [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
- [AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw,
- [AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
- [AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
- [AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
- [AUD_CLKID_TDMOUT_A_SCLK] = &g12a_tdmout_a_sclk.hw,
- [AUD_CLKID_TDMOUT_B_SCLK] = &g12a_tdmout_b_sclk.hw,
- [AUD_CLKID_TDMOUT_C_SCLK] = &g12a_tdmout_c_sclk.hw,
- [AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
- [AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
- [AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
- [AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw,
- [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw,
- [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
- [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
- [AUD_CLKID_TDM_MCLK_PAD0] = &sm1_tdm_mclk_pad_0.hw,
- [AUD_CLKID_TDM_MCLK_PAD1] = &sm1_tdm_mclk_pad_1.hw,
- [AUD_CLKID_TDM_LRCLK_PAD0] = &sm1_tdm_lrclk_pad_0.hw,
- [AUD_CLKID_TDM_LRCLK_PAD1] = &sm1_tdm_lrclk_pad_1.hw,
- [AUD_CLKID_TDM_LRCLK_PAD2] = &sm1_tdm_lrclk_pad_2.hw,
- [AUD_CLKID_TDM_SCLK_PAD0] = &sm1_tdm_sclk_pad_0.hw,
- [AUD_CLKID_TDM_SCLK_PAD1] = &sm1_tdm_sclk_pad_1.hw,
- [AUD_CLKID_TDM_SCLK_PAD2] = &sm1_tdm_sclk_pad_2.hw,
- [AUD_CLKID_TOP] = &sm1_aud_top.hw,
- [AUD_CLKID_TORAM] = &toram.hw,
- [AUD_CLKID_EQDRC] = &eqdrc.hw,
- [AUD_CLKID_RESAMPLE_B] = &resample_b.hw,
- [AUD_CLKID_TOVAD] = &tovad.hw,
- [AUD_CLKID_LOCKER] = &locker.hw,
- [AUD_CLKID_SPDIFIN_LB] = &spdifin_lb.hw,
- [AUD_CLKID_FRDDR_D] = &frddr_d.hw,
- [AUD_CLKID_TODDR_D] = &toddr_d.hw,
- [AUD_CLKID_LOOPBACK_B] = &loopback_b.hw,
- [AUD_CLKID_CLK81_EN] = &sm1_clk81_en.hw,
- [AUD_CLKID_SYSCLK_A_DIV] = &sm1_sysclk_a_div.hw,
- [AUD_CLKID_SYSCLK_A_EN] = &sm1_sysclk_a_en.hw,
- [AUD_CLKID_SYSCLK_B_DIV] = &sm1_sysclk_b_div.hw,
- [AUD_CLKID_SYSCLK_B_EN] = &sm1_sysclk_b_en.hw,
- [NR_CLKS] = NULL,
- },
- .num = NR_CLKS,
+static struct clk_hw *sm1_audio_hw_clks[] = {
+ [AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
+ [AUD_CLKID_PDM] = &pdm.hw,
+ [AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
+ [AUD_CLKID_TDMIN_B] = &tdmin_b.hw,
+ [AUD_CLKID_TDMIN_C] = &tdmin_c.hw,
+ [AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw,
+ [AUD_CLKID_TDMOUT_A] = &tdmout_a.hw,
+ [AUD_CLKID_TDMOUT_B] = &tdmout_b.hw,
+ [AUD_CLKID_TDMOUT_C] = &tdmout_c.hw,
+ [AUD_CLKID_FRDDR_A] = &frddr_a.hw,
+ [AUD_CLKID_FRDDR_B] = &frddr_b.hw,
+ [AUD_CLKID_FRDDR_C] = &frddr_c.hw,
+ [AUD_CLKID_TODDR_A] = &toddr_a.hw,
+ [AUD_CLKID_TODDR_B] = &toddr_b.hw,
+ [AUD_CLKID_TODDR_C] = &toddr_c.hw,
+ [AUD_CLKID_LOOPBACK] = &loopback.hw,
+ [AUD_CLKID_SPDIFIN] = &spdifin.hw,
+ [AUD_CLKID_SPDIFOUT] = &spdifout.hw,
+ [AUD_CLKID_RESAMPLE] = &resample.hw,
+ [AUD_CLKID_SPDIFOUT_B] = &spdifout_b.hw,
+ [AUD_CLKID_MST_A_MCLK_SEL] = &sm1_mst_a_mclk_sel.hw,
+ [AUD_CLKID_MST_B_MCLK_SEL] = &sm1_mst_b_mclk_sel.hw,
+ [AUD_CLKID_MST_C_MCLK_SEL] = &sm1_mst_c_mclk_sel.hw,
+ [AUD_CLKID_MST_D_MCLK_SEL] = &sm1_mst_d_mclk_sel.hw,
+ [AUD_CLKID_MST_E_MCLK_SEL] = &sm1_mst_e_mclk_sel.hw,
+ [AUD_CLKID_MST_F_MCLK_SEL] = &sm1_mst_f_mclk_sel.hw,
+ [AUD_CLKID_MST_A_MCLK_DIV] = &sm1_mst_a_mclk_div.hw,
+ [AUD_CLKID_MST_B_MCLK_DIV] = &sm1_mst_b_mclk_div.hw,
+ [AUD_CLKID_MST_C_MCLK_DIV] = &sm1_mst_c_mclk_div.hw,
+ [AUD_CLKID_MST_D_MCLK_DIV] = &sm1_mst_d_mclk_div.hw,
+ [AUD_CLKID_MST_E_MCLK_DIV] = &sm1_mst_e_mclk_div.hw,
+ [AUD_CLKID_MST_F_MCLK_DIV] = &sm1_mst_f_mclk_div.hw,
+ [AUD_CLKID_MST_A_MCLK] = &sm1_mst_a_mclk.hw,
+ [AUD_CLKID_MST_B_MCLK] = &sm1_mst_b_mclk.hw,
+ [AUD_CLKID_MST_C_MCLK] = &sm1_mst_c_mclk.hw,
+ [AUD_CLKID_MST_D_MCLK] = &sm1_mst_d_mclk.hw,
+ [AUD_CLKID_MST_E_MCLK] = &sm1_mst_e_mclk.hw,
+ [AUD_CLKID_MST_F_MCLK] = &sm1_mst_f_mclk.hw,
+ [AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw,
+ [AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw,
+ [AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw,
+ [AUD_CLKID_SPDIFOUT_B_CLK_SEL] = &spdifout_b_clk_sel.hw,
+ [AUD_CLKID_SPDIFOUT_B_CLK_DIV] = &spdifout_b_clk_div.hw,
+ [AUD_CLKID_SPDIFOUT_B_CLK] = &spdifout_b_clk.hw,
+ [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
+ [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
+ [AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw,
+ [AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw,
+ [AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw,
+ [AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw,
+ [AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw,
+ [AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw,
+ [AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw,
+ [AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw,
+ [AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw,
+ [AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw,
+ [AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw,
+ [AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw,
+ [AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw,
+ [AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw,
+ [AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw,
+ [AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw,
+ [AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw,
+ [AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw,
+ [AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw,
+ [AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw,
+ [AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw,
+ [AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw,
+ [AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw,
+ [AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw,
+ [AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw,
+ [AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw,
+ [AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw,
+ [AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw,
+ [AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw,
+ [AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw,
+ [AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw,
+ [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
+ [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
+ [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
+ [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
+ [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
+ [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
+ [AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw,
+ [AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw,
+ [AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw,
+ [AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw,
+ [AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw,
+ [AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw,
+ [AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw,
+ [AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw,
+ [AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw,
+ [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw,
+ [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw,
+ [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw,
+ [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw,
+ [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
+ [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
+ [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
+ [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
+ [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
+ [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
+ [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
+ [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
+ [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
+ [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
+ [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
+ [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
+ [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
+ [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
+ [AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw,
+ [AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
+ [AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
+ [AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
+ [AUD_CLKID_TDMOUT_A_SCLK] = &g12a_tdmout_a_sclk.hw,
+ [AUD_CLKID_TDMOUT_B_SCLK] = &g12a_tdmout_b_sclk.hw,
+ [AUD_CLKID_TDMOUT_C_SCLK] = &g12a_tdmout_c_sclk.hw,
+ [AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
+ [AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
+ [AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
+ [AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw,
+ [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw,
+ [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
+ [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
+ [AUD_CLKID_TDM_MCLK_PAD0] = &sm1_tdm_mclk_pad_0.hw,
+ [AUD_CLKID_TDM_MCLK_PAD1] = &sm1_tdm_mclk_pad_1.hw,
+ [AUD_CLKID_TDM_LRCLK_PAD0] = &sm1_tdm_lrclk_pad_0.hw,
+ [AUD_CLKID_TDM_LRCLK_PAD1] = &sm1_tdm_lrclk_pad_1.hw,
+ [AUD_CLKID_TDM_LRCLK_PAD2] = &sm1_tdm_lrclk_pad_2.hw,
+ [AUD_CLKID_TDM_SCLK_PAD0] = &sm1_tdm_sclk_pad_0.hw,
+ [AUD_CLKID_TDM_SCLK_PAD1] = &sm1_tdm_sclk_pad_1.hw,
+ [AUD_CLKID_TDM_SCLK_PAD2] = &sm1_tdm_sclk_pad_2.hw,
+ [AUD_CLKID_TOP] = &sm1_aud_top.hw,
+ [AUD_CLKID_TORAM] = &toram.hw,
+ [AUD_CLKID_EQDRC] = &eqdrc.hw,
+ [AUD_CLKID_RESAMPLE_B] = &resample_b.hw,
+ [AUD_CLKID_TOVAD] = &tovad.hw,
+ [AUD_CLKID_LOCKER] = &locker.hw,
+ [AUD_CLKID_SPDIFIN_LB] = &spdifin_lb.hw,
+ [AUD_CLKID_FRDDR_D] = &frddr_d.hw,
+ [AUD_CLKID_TODDR_D] = &toddr_d.hw,
+ [AUD_CLKID_LOOPBACK_B] = &loopback_b.hw,
+ [AUD_CLKID_CLK81_EN] = &sm1_clk81_en.hw,
+ [AUD_CLKID_SYSCLK_A_DIV] = &sm1_sysclk_a_div.hw,
+ [AUD_CLKID_SYSCLK_A_EN] = &sm1_sysclk_a_en.hw,
+ [AUD_CLKID_SYSCLK_B_DIV] = &sm1_sysclk_b_div.hw,
+ [AUD_CLKID_SYSCLK_B_EN] = &sm1_sysclk_b_en.hw,
};
@@ -1745,11 +1733,25 @@ static const struct regmap_config axg_audio_regmap_cfg = {
struct audioclk_data {
struct clk_regmap *const *regmap_clks;
unsigned int regmap_clk_num;
- struct clk_hw_onecell_data *hw_onecell_data;
+ struct clk_hw **hw_clks;
+ unsigned int hw_clk_num;
unsigned int reset_offset;
unsigned int reset_num;
};
+static struct clk_hw *axg_audio_clkc_hw_get(struct of_phandle_args *clkspec, void *clk_data)
+{
+ const struct audioclk_data *data = clk_data;
+ unsigned int idx = clkspec->args[0];
+
+ if (idx >= data->hw_clk_num) {
+ pr_err("%s: invalid index %u\n", __func__, idx);
+ return ERR_PTR(-EINVAL);
+ }
+
+ return data->hw_clks[idx];
+}
+
static int axg_audio_clkc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -1791,10 +1793,10 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
data->regmap_clks[i]->map = map;
/* Take care to skip the registered input clocks */
- for (i = AUD_CLKID_DDR_ARB; i < data->hw_onecell_data->num; i++) {
+ for (i = AUD_CLKID_DDR_ARB; i < data->hw_clk_num; i++) {
const char *name;
- hw = data->hw_onecell_data->hws[i];
+ hw = data->hw_clks[i];
/* array might be sparse */
if (!hw)
continue;
@@ -1808,8 +1810,7 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
}
}
- ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
- data->hw_onecell_data);
+ ret = devm_of_clk_add_hw_provider(dev, axg_audio_clkc_hw_get, (void *)data);
if (ret)
return ret;
@@ -1834,13 +1835,15 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
static const struct audioclk_data axg_audioclk_data = {
.regmap_clks = axg_clk_regmaps,
.regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps),
- .hw_onecell_data = &axg_audio_hw_onecell_data,
+ .hw_clks = axg_audio_hw_clks,
+ .hw_clk_num = ARRAY_SIZE(axg_audio_hw_clks),
};
static const struct audioclk_data g12a_audioclk_data = {
.regmap_clks = g12a_clk_regmaps,
.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
- .hw_onecell_data = &g12a_audio_hw_onecell_data,
+ .hw_clks = g12a_audio_hw_clks,
+ .hw_clk_num = ARRAY_SIZE(g12a_audio_hw_clks),
.reset_offset = AUDIO_SW_RESET,
.reset_num = 26,
};
@@ -1848,7 +1851,8 @@ static const struct audioclk_data g12a_audioclk_data = {
static const struct audioclk_data sm1_audioclk_data = {
.regmap_clks = sm1_clk_regmaps,
.regmap_clk_num = ARRAY_SIZE(sm1_clk_regmaps),
- .hw_onecell_data = &sm1_audio_hw_onecell_data,
+ .hw_clks = sm1_audio_hw_clks,
+ .hw_clk_num = ARRAY_SIZE(sm1_audio_hw_clks),
.reset_offset = AUDIO_SM1_SW_RESET0,
.reset_num = 39,
};
diff --git a/drivers/clk/meson/axg-audio.h b/drivers/clk/meson/axg-audio.h
index fd65a7d0704b..d6ed27c77729 100644
--- a/drivers/clk/meson/axg-audio.h
+++ b/drivers/clk/meson/axg-audio.h
@@ -138,6 +138,4 @@
/* include the CLKIDs which are part of the DT bindings */
#include <dt-bindings/clock/axg-audio-clkc.h>
-#define NR_CLKS 178
-
#endif /*__AXG_AUDIO_CLKC_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 06/18] dt-bindings: clk: gxbb-clkc: expose all clock ids
2023-06-07 10:56 [PATCH 00/18] clk: meson: move all private clk IDs to public dt-bindings headers Neil Armstrong
` (3 preceding siblings ...)
2023-06-07 10:56 ` [PATCH 05/18] clk: meson: migrate axg-audio " Neil Armstrong
@ 2023-06-07 10:56 ` Neil Armstrong
2023-06-10 16:38 ` Krzysztof Kozlowski
2023-06-07 10:56 ` [PATCH 07/18] dt-bindings: clk: axg-clkc: " Neil Armstrong
` (11 subsequent siblings)
16 siblings, 1 reply; 35+ messages in thread
From: Neil Armstrong @ 2023-06-07 10:56 UTC (permalink / raw)
To: Jerome Brunet, Michael Turquette, Stephen Boyd, Kevin Hilman,
Martin Blumenstingl, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-amlogic, linux-clk, linux-arm-kernel, linux-kernel,
devicetree, Neil Armstrong
Due to a policy change in clock ID bindings handling, expose
all the "private" clock IDs to the public clock dt-bindings
to move out of the previous maintenance scheme.
This refers to a discussion at [1] & [2] with Krzysztof about
the issue with the current maintenance.
It was decided to move every gxbb-clkc ID to the public clock
dt-bindings headers to be merged in a single tree so we
can safely add new clocks without having merge issues.
[1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/
[2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
drivers/clk/meson/gxbb.h | 76 -----------------------------------
include/dt-bindings/clock/gxbb-clkc.h | 65 ++++++++++++++++++++++++++++++
2 files changed, 65 insertions(+), 76 deletions(-)
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index 6751cda25986..798ffb911103 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -112,82 +112,6 @@
#define HHI_BT656_CLK_CNTL 0x3D4 /* 0xf5 offset in data sheet */
#define HHI_SAR_CLK_CNTL 0x3D8 /* 0xf6 offset in data sheet */
-/*
- * CLKID index values
- *
- * These indices are entirely contrived and do not map onto the hardware.
- * It has now been decided to expose everything by default in the DT header:
- * include/dt-bindings/clock/gxbb-clkc.h. Only the clocks ids we don't want
- * to expose, such as the internal muxes and dividers of composite clocks,
- * will remain defined here.
- */
-/* ID 1 is unused (it was used by the non-existing CLKID_CPUCLK before) */
-#define CLKID_MPEG_SEL 10
-#define CLKID_MPEG_DIV 11
-#define CLKID_SAR_ADC_DIV 99
-#define CLKID_MALI_0_DIV 101
-#define CLKID_MALI_1_DIV 104
-#define CLKID_CTS_AMCLK_SEL 108
-#define CLKID_CTS_AMCLK_DIV 109
-#define CLKID_CTS_MCLK_I958_SEL 111
-#define CLKID_CTS_MCLK_I958_DIV 112
-#define CLKID_32K_CLK_SEL 115
-#define CLKID_32K_CLK_DIV 116
-#define CLKID_SD_EMMC_A_CLK0_SEL 117
-#define CLKID_SD_EMMC_A_CLK0_DIV 118
-#define CLKID_SD_EMMC_B_CLK0_SEL 120
-#define CLKID_SD_EMMC_B_CLK0_DIV 121
-#define CLKID_SD_EMMC_C_CLK0_SEL 123
-#define CLKID_SD_EMMC_C_CLK0_DIV 124
-#define CLKID_VPU_0_DIV 127
-#define CLKID_VPU_1_DIV 130
-#define CLKID_VAPB_0_DIV 134
-#define CLKID_VAPB_1_DIV 137
-#define CLKID_HDMI_PLL_PRE_MULT 141
-#define CLKID_MPLL0_DIV 142
-#define CLKID_MPLL1_DIV 143
-#define CLKID_MPLL2_DIV 144
-#define CLKID_MPLL_PREDIV 145
-#define CLKID_FCLK_DIV2_DIV 146
-#define CLKID_FCLK_DIV3_DIV 147
-#define CLKID_FCLK_DIV4_DIV 148
-#define CLKID_FCLK_DIV5_DIV 149
-#define CLKID_FCLK_DIV7_DIV 150
-#define CLKID_VDEC_1_SEL 151
-#define CLKID_VDEC_1_DIV 152
-#define CLKID_VDEC_HEVC_SEL 154
-#define CLKID_VDEC_HEVC_DIV 155
-#define CLKID_GEN_CLK_SEL 157
-#define CLKID_GEN_CLK_DIV 158
-#define CLKID_FIXED_PLL_DCO 160
-#define CLKID_HDMI_PLL_DCO 161
-#define CLKID_HDMI_PLL_OD 162
-#define CLKID_HDMI_PLL_OD2 163
-#define CLKID_SYS_PLL_DCO 164
-#define CLKID_GP0_PLL_DCO 165
-#define CLKID_VID_PLL_SEL 167
-#define CLKID_VID_PLL_DIV 168
-#define CLKID_VCLK_SEL 169
-#define CLKID_VCLK2_SEL 170
-#define CLKID_VCLK_INPUT 171
-#define CLKID_VCLK2_INPUT 172
-#define CLKID_VCLK_DIV 173
-#define CLKID_VCLK2_DIV 174
-#define CLKID_VCLK_DIV2_EN 177
-#define CLKID_VCLK_DIV4_EN 178
-#define CLKID_VCLK_DIV6_EN 179
-#define CLKID_VCLK_DIV12_EN 180
-#define CLKID_VCLK2_DIV2_EN 181
-#define CLKID_VCLK2_DIV4_EN 182
-#define CLKID_VCLK2_DIV6_EN 183
-#define CLKID_VCLK2_DIV12_EN 184
-#define CLKID_CTS_ENCI_SEL 195
-#define CLKID_CTS_ENCP_SEL 196
-#define CLKID_CTS_VDAC_SEL 197
-#define CLKID_HDMI_TX_SEL 198
-#define CLKID_HDMI_SEL 203
-#define CLKID_HDMI_DIV 204
-
/* include the CLKIDs that have been made part of the DT binding */
#include <dt-bindings/clock/gxbb-clkc.h>
diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
index 4073eb7a9da1..c0ce5e9c4151 100644
--- a/include/dt-bindings/clock/gxbb-clkc.h
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -15,6 +15,8 @@
#define CLKID_FCLK_DIV5 7
#define CLKID_FCLK_DIV7 8
#define CLKID_GP0_PLL 9
+#define CLKID_MPEG_SEL 10
+#define CLKID_MPEG_DIV 11
#define CLKID_CLK81 12
#define CLKID_MPLL0 13
#define CLKID_MPLL1 14
@@ -102,35 +104,92 @@
#define CLKID_SD_EMMC_C 96
#define CLKID_SAR_ADC_CLK 97
#define CLKID_SAR_ADC_SEL 98
+#define CLKID_SAR_ADC_DIV 99
#define CLKID_MALI_0_SEL 100
+#define CLKID_MALI_0_DIV 101
#define CLKID_MALI_0 102
#define CLKID_MALI_1_SEL 103
+#define CLKID_MALI_1_DIV 104
#define CLKID_MALI_1 105
#define CLKID_MALI 106
#define CLKID_CTS_AMCLK 107
+#define CLKID_CTS_AMCLK_SEL 108
+#define CLKID_CTS_AMCLK_DIV 109
#define CLKID_CTS_MCLK_I958 110
+#define CLKID_CTS_MCLK_I958_SEL 111
+#define CLKID_CTS_MCLK_I958_DIV 112
#define CLKID_CTS_I958 113
#define CLKID_32K_CLK 114
+#define CLKID_32K_CLK_SEL 115
+#define CLKID_32K_CLK_DIV 116
+#define CLKID_SD_EMMC_A_CLK0_SEL 117
+#define CLKID_SD_EMMC_A_CLK0_DIV 118
#define CLKID_SD_EMMC_A_CLK0 119
+#define CLKID_SD_EMMC_B_CLK0_SEL 120
+#define CLKID_SD_EMMC_B_CLK0_DIV 121
#define CLKID_SD_EMMC_B_CLK0 122
+#define CLKID_SD_EMMC_C_CLK0_SEL 123
+#define CLKID_SD_EMMC_C_CLK0_DIV 124
#define CLKID_SD_EMMC_C_CLK0 125
#define CLKID_VPU_0_SEL 126
+#define CLKID_VPU_0_DIV 127
#define CLKID_VPU_0 128
#define CLKID_VPU_1_SEL 129
+#define CLKID_VPU_1_DIV 130
#define CLKID_VPU_1 131
#define CLKID_VPU 132
#define CLKID_VAPB_0_SEL 133
+#define CLKID_VAPB_0_DIV 134
#define CLKID_VAPB_0 135
#define CLKID_VAPB_1_SEL 136
+#define CLKID_VAPB_1_DIV 137
#define CLKID_VAPB_1 138
#define CLKID_VAPB_SEL 139
#define CLKID_VAPB 140
+#define CLKID_HDMI_PLL_PRE_MULT 141
+#define CLKID_MPLL0_DIV 142
+#define CLKID_MPLL1_DIV 143
+#define CLKID_MPLL2_DIV 144
+#define CLKID_MPLL_PREDIV 145
+#define CLKID_FCLK_DIV2_DIV 146
+#define CLKID_FCLK_DIV3_DIV 147
+#define CLKID_FCLK_DIV4_DIV 148
+#define CLKID_FCLK_DIV5_DIV 149
+#define CLKID_FCLK_DIV7_DIV 150
+#define CLKID_VDEC_1_SEL 151
+#define CLKID_VDEC_1_DIV 152
#define CLKID_VDEC_1 153
+#define CLKID_VDEC_HEVC_SEL 154
+#define CLKID_VDEC_HEVC_DIV 155
#define CLKID_VDEC_HEVC 156
+#define CLKID_GEN_CLK_SEL 157
+#define CLKID_GEN_CLK_DIV 158
#define CLKID_GEN_CLK 159
+#define CLKID_FIXED_PLL_DCO 160
+#define CLKID_HDMI_PLL_DCO 161
+#define CLKID_HDMI_PLL_OD 162
+#define CLKID_HDMI_PLL_OD2 163
+#define CLKID_SYS_PLL_DCO 164
+#define CLKID_GP0_PLL_DCO 165
#define CLKID_VID_PLL 166
+#define CLKID_VID_PLL_SEL 167
+#define CLKID_VID_PLL_DIV 168
+#define CLKID_VCLK_SEL 169
+#define CLKID_VCLK2_SEL 170
+#define CLKID_VCLK_INPUT 171
+#define CLKID_VCLK2_INPUT 172
+#define CLKID_VCLK_DIV 173
+#define CLKID_VCLK2_DIV 174
#define CLKID_VCLK 175
#define CLKID_VCLK2 176
+#define CLKID_VCLK_DIV2_EN 177
+#define CLKID_VCLK_DIV4_EN 178
+#define CLKID_VCLK_DIV6_EN 179
+#define CLKID_VCLK_DIV12_EN 180
+#define CLKID_VCLK2_DIV2_EN 181
+#define CLKID_VCLK2_DIV4_EN 182
+#define CLKID_VCLK2_DIV6_EN 183
+#define CLKID_VCLK2_DIV12_EN 184
#define CLKID_VCLK_DIV1 185
#define CLKID_VCLK_DIV2 186
#define CLKID_VCLK_DIV4 187
@@ -141,10 +200,16 @@
#define CLKID_VCLK2_DIV4 192
#define CLKID_VCLK2_DIV6 193
#define CLKID_VCLK2_DIV12 194
+#define CLKID_CTS_ENCI_SEL 195
+#define CLKID_CTS_ENCP_SEL 196
+#define CLKID_CTS_VDAC_SEL 197
+#define CLKID_HDMI_TX_SEL 198
#define CLKID_CTS_ENCI 199
#define CLKID_CTS_ENCP 200
#define CLKID_CTS_VDAC 201
#define CLKID_HDMI_TX 202
+#define CLKID_HDMI_SEL 203
+#define CLKID_HDMI_DIV 204
#define CLKID_HDMI 205
#define CLKID_ACODEC 206
--
2.34.1
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 07/18] dt-bindings: clk: axg-clkc: expose all clock ids
2023-06-07 10:56 [PATCH 00/18] clk: meson: move all private clk IDs to public dt-bindings headers Neil Armstrong
` (4 preceding siblings ...)
2023-06-07 10:56 ` [PATCH 06/18] dt-bindings: clk: gxbb-clkc: expose all clock ids Neil Armstrong
@ 2023-06-07 10:56 ` Neil Armstrong
2023-06-10 16:38 ` Krzysztof Kozlowski
2023-06-07 10:56 ` [PATCH 08/18] dt-bindings: clk: g12a-clks: " Neil Armstrong
` (10 subsequent siblings)
16 siblings, 1 reply; 35+ messages in thread
From: Neil Armstrong @ 2023-06-07 10:56 UTC (permalink / raw)
To: Jerome Brunet, Michael Turquette, Stephen Boyd, Kevin Hilman,
Martin Blumenstingl, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-amlogic, linux-clk, linux-arm-kernel, linux-kernel,
devicetree, Neil Armstrong
Due to a policy change in clock ID bindings handling, expose
all the "private" clock IDs to the public clock dt-bindings
to move out of the previous maintenance scheme.
This refers to a discussion at [1] & [2] with Krzysztof about
the issue with the current maintenance.
It was decided to move every axg-clkc ID to the public clock
dt-bindings headers to be merged in a single tree so we
can safely add new clocks without having merge issues.
[1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/
[2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
drivers/clk/meson/axg.h | 58 ------------------------------------
include/dt-bindings/clock/axg-clkc.h | 48 +++++++++++++++++++++++++++++
2 files changed, 48 insertions(+), 58 deletions(-)
diff --git a/drivers/clk/meson/axg.h b/drivers/clk/meson/axg.h
index 39f9e2db82bd..ed157532b4d7 100644
--- a/drivers/clk/meson/axg.h
+++ b/drivers/clk/meson/axg.h
@@ -102,64 +102,6 @@
#define HHI_DPLL_TOP_I 0x318
#define HHI_DPLL_TOP2_I 0x31C
-/*
- * CLKID index values
- *
- * These indices are entirely contrived and do not map onto the hardware.
- * It has now been decided to expose everything by default in the DT header:
- * include/dt-bindings/clock/axg-clkc.h. Only the clocks ids we don't want
- * to expose, such as the internal muxes and dividers of composite clocks,
- * will remain defined here.
- */
-#define CLKID_MPEG_SEL 8
-#define CLKID_MPEG_DIV 9
-#define CLKID_SD_EMMC_B_CLK0_SEL 61
-#define CLKID_SD_EMMC_B_CLK0_DIV 62
-#define CLKID_SD_EMMC_C_CLK0_SEL 63
-#define CLKID_SD_EMMC_C_CLK0_DIV 64
-#define CLKID_MPLL0_DIV 65
-#define CLKID_MPLL1_DIV 66
-#define CLKID_MPLL2_DIV 67
-#define CLKID_MPLL3_DIV 68
-#define CLKID_MPLL_PREDIV 70
-#define CLKID_FCLK_DIV2_DIV 71
-#define CLKID_FCLK_DIV3_DIV 72
-#define CLKID_FCLK_DIV4_DIV 73
-#define CLKID_FCLK_DIV5_DIV 74
-#define CLKID_FCLK_DIV7_DIV 75
-#define CLKID_PCIE_PLL 76
-#define CLKID_PCIE_MUX 77
-#define CLKID_PCIE_REF 78
-#define CLKID_GEN_CLK_SEL 82
-#define CLKID_GEN_CLK_DIV 83
-#define CLKID_SYS_PLL_DCO 85
-#define CLKID_FIXED_PLL_DCO 86
-#define CLKID_GP0_PLL_DCO 87
-#define CLKID_HIFI_PLL_DCO 88
-#define CLKID_PCIE_PLL_DCO 89
-#define CLKID_PCIE_PLL_OD 90
-#define CLKID_VPU_0_DIV 91
-#define CLKID_VPU_1_DIV 94
-#define CLKID_VAPB_0_DIV 98
-#define CLKID_VAPB_1_DIV 101
-#define CLKID_VCLK_SEL 108
-#define CLKID_VCLK2_SEL 109
-#define CLKID_VCLK_INPUT 110
-#define CLKID_VCLK2_INPUT 111
-#define CLKID_VCLK_DIV 112
-#define CLKID_VCLK2_DIV 113
-#define CLKID_VCLK_DIV2_EN 114
-#define CLKID_VCLK_DIV4_EN 115
-#define CLKID_VCLK_DIV6_EN 116
-#define CLKID_VCLK_DIV12_EN 117
-#define CLKID_VCLK2_DIV2_EN 118
-#define CLKID_VCLK2_DIV4_EN 119
-#define CLKID_VCLK2_DIV6_EN 120
-#define CLKID_VCLK2_DIV12_EN 121
-#define CLKID_CTS_ENCL_SEL 132
-#define CLKID_VDIN_MEAS_SEL 134
-#define CLKID_VDIN_MEAS_DIV 135
-
/* include the CLKIDs that have been made part of the DT binding */
#include <dt-bindings/clock/axg-clkc.h>
diff --git a/include/dt-bindings/clock/axg-clkc.h b/include/dt-bindings/clock/axg-clkc.h
index 93752ea107e3..442162822b88 100644
--- a/include/dt-bindings/clock/axg-clkc.h
+++ b/include/dt-bindings/clock/axg-clkc.h
@@ -16,6 +16,8 @@
#define CLKID_FCLK_DIV5 5
#define CLKID_FCLK_DIV7 6
#define CLKID_GP0_PLL 7
+#define CLKID_MPEG_SEL 8
+#define CLKID_MPEG_DIV 9
#define CLKID_CLK81 10
#define CLKID_MPLL0 11
#define CLKID_MPLL1 12
@@ -67,23 +69,66 @@
#define CLKID_AO_I2C 58
#define CLKID_SD_EMMC_B_CLK0 59
#define CLKID_SD_EMMC_C_CLK0 60
+#define CLKID_SD_EMMC_B_CLK0_SEL 61
+#define CLKID_SD_EMMC_B_CLK0_DIV 62
+#define CLKID_SD_EMMC_C_CLK0_SEL 63
+#define CLKID_SD_EMMC_C_CLK0_DIV 64
+#define CLKID_MPLL0_DIV 65
+#define CLKID_MPLL1_DIV 66
+#define CLKID_MPLL2_DIV 67
+#define CLKID_MPLL3_DIV 68
#define CLKID_HIFI_PLL 69
+#define CLKID_MPLL_PREDIV 70
+#define CLKID_FCLK_DIV2_DIV 71
+#define CLKID_FCLK_DIV3_DIV 72
+#define CLKID_FCLK_DIV4_DIV 73
+#define CLKID_FCLK_DIV5_DIV 74
+#define CLKID_FCLK_DIV7_DIV 75
+#define CLKID_PCIE_PLL 76
+#define CLKID_PCIE_MUX 77
+#define CLKID_PCIE_REF 78
#define CLKID_PCIE_CML_EN0 79
#define CLKID_PCIE_CML_EN1 80
+#define CLKID_GEN_CLK_SEL 82
+#define CLKID_GEN_CLK_DIV 83
#define CLKID_GEN_CLK 84
+#define CLKID_SYS_PLL_DCO 85
+#define CLKID_FIXED_PLL_DCO 86
+#define CLKID_GP0_PLL_DCO 87
+#define CLKID_HIFI_PLL_DCO 88
+#define CLKID_PCIE_PLL_DCO 89
+#define CLKID_PCIE_PLL_OD 90
+#define CLKID_VPU_0_DIV 91
#define CLKID_VPU_0_SEL 92
#define CLKID_VPU_0 93
+#define CLKID_VPU_1_DIV 94
#define CLKID_VPU_1_SEL 95
#define CLKID_VPU_1 96
#define CLKID_VPU 97
+#define CLKID_VAPB_0_DIV 98
#define CLKID_VAPB_0_SEL 99
#define CLKID_VAPB_0 100
+#define CLKID_VAPB_1_DIV 101
#define CLKID_VAPB_1_SEL 102
#define CLKID_VAPB_1 103
#define CLKID_VAPB_SEL 104
#define CLKID_VAPB 105
#define CLKID_VCLK 106
#define CLKID_VCLK2 107
+#define CLKID_VCLK_SEL 108
+#define CLKID_VCLK2_SEL 109
+#define CLKID_VCLK_INPUT 110
+#define CLKID_VCLK2_INPUT 111
+#define CLKID_VCLK_DIV 112
+#define CLKID_VCLK2_DIV 113
+#define CLKID_VCLK_DIV2_EN 114
+#define CLKID_VCLK_DIV4_EN 115
+#define CLKID_VCLK_DIV6_EN 116
+#define CLKID_VCLK_DIV12_EN 117
+#define CLKID_VCLK2_DIV2_EN 118
+#define CLKID_VCLK2_DIV4_EN 119
+#define CLKID_VCLK2_DIV6_EN 120
+#define CLKID_VCLK2_DIV12_EN 121
#define CLKID_VCLK_DIV1 122
#define CLKID_VCLK_DIV2 123
#define CLKID_VCLK_DIV4 124
@@ -94,7 +139,10 @@
#define CLKID_VCLK2_DIV4 129
#define CLKID_VCLK2_DIV6 130
#define CLKID_VCLK2_DIV12 131
+#define CLKID_CTS_ENCL_SEL 132
#define CLKID_CTS_ENCL 133
+#define CLKID_VDIN_MEAS_SEL 134
+#define CLKID_VDIN_MEAS_DIV 135
#define CLKID_VDIN_MEAS 136
#endif /* __AXG_CLKC_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 08/18] dt-bindings: clk: g12a-clks: expose all clock ids
2023-06-07 10:56 [PATCH 00/18] clk: meson: move all private clk IDs to public dt-bindings headers Neil Armstrong
` (5 preceding siblings ...)
2023-06-07 10:56 ` [PATCH 07/18] dt-bindings: clk: axg-clkc: " Neil Armstrong
@ 2023-06-07 10:56 ` Neil Armstrong
2023-06-10 16:38 ` Krzysztof Kozlowski
2023-06-07 10:56 ` [PATCH 09/18] dt-bindings: clk: g12a-aoclkc: " Neil Armstrong
` (9 subsequent siblings)
16 siblings, 1 reply; 35+ messages in thread
From: Neil Armstrong @ 2023-06-07 10:56 UTC (permalink / raw)
To: Jerome Brunet, Michael Turquette, Stephen Boyd, Kevin Hilman,
Martin Blumenstingl, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-amlogic, linux-clk, linux-arm-kernel, linux-kernel,
devicetree, Neil Armstrong
Due to a policy change in clock ID bindings handling, expose
all the "private" clock IDs to the public clock dt-bindings
to move out of the previous maintenance scheme.
This refers to a discussion at [1] & [2] with Krzysztof about
the issue with the current maintenance.
It was decided to move every g12a-clkc ID to the public clock
dt-bindings headers to be merged in a single tree so we
can safely add new clocks without having merge issues.
[1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/
[2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
drivers/clk/meson/g12a.h | 140 ----------------------------------
include/dt-bindings/clock/g12a-clkc.h | 130 +++++++++++++++++++++++++++++++
2 files changed, 130 insertions(+), 140 deletions(-)
diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h
index a70a0cba892b..8e08af3c1476 100644
--- a/drivers/clk/meson/g12a.h
+++ b/drivers/clk/meson/g12a.h
@@ -126,146 +126,6 @@
#define HHI_SYS1_PLL_CNTL5 0x394
#define HHI_SYS1_PLL_CNTL6 0x398
-/*
- * CLKID index values
- *
- * These indices are entirely contrived and do not map onto the hardware.
- * It has now been decided to expose everything by default in the DT header:
- * include/dt-bindings/clock/g12a-clkc.h. Only the clocks ids we don't want
- * to expose, such as the internal muxes and dividers of composite clocks,
- * will remain defined here.
- */
-#define CLKID_MPEG_SEL 8
-#define CLKID_MPEG_DIV 9
-#define CLKID_SD_EMMC_A_CLK0_SEL 63
-#define CLKID_SD_EMMC_A_CLK0_DIV 64
-#define CLKID_SD_EMMC_B_CLK0_SEL 65
-#define CLKID_SD_EMMC_B_CLK0_DIV 66
-#define CLKID_SD_EMMC_C_CLK0_SEL 67
-#define CLKID_SD_EMMC_C_CLK0_DIV 68
-#define CLKID_MPLL0_DIV 69
-#define CLKID_MPLL1_DIV 70
-#define CLKID_MPLL2_DIV 71
-#define CLKID_MPLL3_DIV 72
-#define CLKID_MPLL_PREDIV 73
-#define CLKID_FCLK_DIV2_DIV 75
-#define CLKID_FCLK_DIV3_DIV 76
-#define CLKID_FCLK_DIV4_DIV 77
-#define CLKID_FCLK_DIV5_DIV 78
-#define CLKID_FCLK_DIV7_DIV 79
-#define CLKID_FCLK_DIV2P5_DIV 100
-#define CLKID_FIXED_PLL_DCO 101
-#define CLKID_SYS_PLL_DCO 102
-#define CLKID_GP0_PLL_DCO 103
-#define CLKID_HIFI_PLL_DCO 104
-#define CLKID_VPU_0_DIV 111
-#define CLKID_VPU_1_DIV 114
-#define CLKID_VAPB_0_DIV 118
-#define CLKID_VAPB_1_DIV 121
-#define CLKID_HDMI_PLL_DCO 125
-#define CLKID_HDMI_PLL_OD 126
-#define CLKID_HDMI_PLL_OD2 127
-#define CLKID_VID_PLL_SEL 130
-#define CLKID_VID_PLL_DIV 131
-#define CLKID_VCLK_SEL 132
-#define CLKID_VCLK2_SEL 133
-#define CLKID_VCLK_INPUT 134
-#define CLKID_VCLK2_INPUT 135
-#define CLKID_VCLK_DIV 136
-#define CLKID_VCLK2_DIV 137
-#define CLKID_VCLK_DIV2_EN 140
-#define CLKID_VCLK_DIV4_EN 141
-#define CLKID_VCLK_DIV6_EN 142
-#define CLKID_VCLK_DIV12_EN 143
-#define CLKID_VCLK2_DIV2_EN 144
-#define CLKID_VCLK2_DIV4_EN 145
-#define CLKID_VCLK2_DIV6_EN 146
-#define CLKID_VCLK2_DIV12_EN 147
-#define CLKID_CTS_ENCI_SEL 158
-#define CLKID_CTS_ENCP_SEL 159
-#define CLKID_CTS_VDAC_SEL 160
-#define CLKID_HDMI_TX_SEL 161
-#define CLKID_HDMI_SEL 166
-#define CLKID_HDMI_DIV 167
-#define CLKID_MALI_0_DIV 170
-#define CLKID_MALI_1_DIV 173
-#define CLKID_MPLL_50M_DIV 176
-#define CLKID_SYS_PLL_DIV16_EN 178
-#define CLKID_SYS_PLL_DIV16 179
-#define CLKID_CPU_CLK_DYN0_SEL 180
-#define CLKID_CPU_CLK_DYN0_DIV 181
-#define CLKID_CPU_CLK_DYN0 182
-#define CLKID_CPU_CLK_DYN1_SEL 183
-#define CLKID_CPU_CLK_DYN1_DIV 184
-#define CLKID_CPU_CLK_DYN1 185
-#define CLKID_CPU_CLK_DYN 186
-#define CLKID_CPU_CLK_DIV16_EN 188
-#define CLKID_CPU_CLK_DIV16 189
-#define CLKID_CPU_CLK_APB_DIV 190
-#define CLKID_CPU_CLK_APB 191
-#define CLKID_CPU_CLK_ATB_DIV 192
-#define CLKID_CPU_CLK_ATB 193
-#define CLKID_CPU_CLK_AXI_DIV 194
-#define CLKID_CPU_CLK_AXI 195
-#define CLKID_CPU_CLK_TRACE_DIV 196
-#define CLKID_CPU_CLK_TRACE 197
-#define CLKID_PCIE_PLL_DCO 198
-#define CLKID_PCIE_PLL_DCO_DIV2 199
-#define CLKID_PCIE_PLL_OD 200
-#define CLKID_VDEC_1_SEL 202
-#define CLKID_VDEC_1_DIV 203
-#define CLKID_VDEC_HEVC_SEL 205
-#define CLKID_VDEC_HEVC_DIV 206
-#define CLKID_VDEC_HEVCF_SEL 208
-#define CLKID_VDEC_HEVCF_DIV 209
-#define CLKID_TS_DIV 211
-#define CLKID_SYS1_PLL_DCO 213
-#define CLKID_SYS1_PLL 214
-#define CLKID_SYS1_PLL_DIV16_EN 215
-#define CLKID_SYS1_PLL_DIV16 216
-#define CLKID_CPUB_CLK_DYN0_SEL 217
-#define CLKID_CPUB_CLK_DYN0_DIV 218
-#define CLKID_CPUB_CLK_DYN0 219
-#define CLKID_CPUB_CLK_DYN1_SEL 220
-#define CLKID_CPUB_CLK_DYN1_DIV 221
-#define CLKID_CPUB_CLK_DYN1 222
-#define CLKID_CPUB_CLK_DYN 223
-#define CLKID_CPUB_CLK_DIV16_EN 225
-#define CLKID_CPUB_CLK_DIV16 226
-#define CLKID_CPUB_CLK_DIV2 227
-#define CLKID_CPUB_CLK_DIV3 228
-#define CLKID_CPUB_CLK_DIV4 229
-#define CLKID_CPUB_CLK_DIV5 230
-#define CLKID_CPUB_CLK_DIV6 231
-#define CLKID_CPUB_CLK_DIV7 232
-#define CLKID_CPUB_CLK_DIV8 233
-#define CLKID_CPUB_CLK_APB_SEL 234
-#define CLKID_CPUB_CLK_APB 235
-#define CLKID_CPUB_CLK_ATB_SEL 236
-#define CLKID_CPUB_CLK_ATB 237
-#define CLKID_CPUB_CLK_AXI_SEL 238
-#define CLKID_CPUB_CLK_AXI 239
-#define CLKID_CPUB_CLK_TRACE_SEL 240
-#define CLKID_CPUB_CLK_TRACE 241
-#define CLKID_GP1_PLL_DCO 242
-#define CLKID_DSU_CLK_DYN0_SEL 244
-#define CLKID_DSU_CLK_DYN0_DIV 245
-#define CLKID_DSU_CLK_DYN0 246
-#define CLKID_DSU_CLK_DYN1_SEL 247
-#define CLKID_DSU_CLK_DYN1_DIV 248
-#define CLKID_DSU_CLK_DYN1 249
-#define CLKID_DSU_CLK_DYN 250
-#define CLKID_DSU_CLK_FINAL 251
-#define CLKID_SPICC0_SCLK_SEL 256
-#define CLKID_SPICC0_SCLK_DIV 257
-#define CLKID_SPICC1_SCLK_SEL 259
-#define CLKID_SPICC1_SCLK_DIV 260
-#define CLKID_NNA_AXI_CLK_SEL 262
-#define CLKID_NNA_AXI_CLK_DIV 263
-#define CLKID_NNA_CORE_CLK_SEL 265
-#define CLKID_NNA_CORE_CLK_DIV 266
-#define CLKID_MIPI_DSI_PXCLK_DIV 268
-
/* include the CLKIDs that have been made part of the DT binding */
#include <dt-bindings/clock/g12a-clkc.h>
diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h
index a93b58c5e18e..387767f4e298 100644
--- a/include/dt-bindings/clock/g12a-clkc.h
+++ b/include/dt-bindings/clock/g12a-clkc.h
@@ -16,6 +16,8 @@
#define CLKID_FCLK_DIV5 5
#define CLKID_FCLK_DIV7 6
#define CLKID_GP0_PLL 7
+#define CLKID_MPEG_SEL 8
+#define CLKID_MPEG_DIV 9
#define CLKID_CLK81 10
#define CLKID_MPLL0 11
#define CLKID_MPLL1 12
@@ -69,7 +71,23 @@
#define CLKID_SD_EMMC_A_CLK0 60
#define CLKID_SD_EMMC_B_CLK0 61
#define CLKID_SD_EMMC_C_CLK0 62
+#define CLKID_SD_EMMC_A_CLK0_SEL 63
+#define CLKID_SD_EMMC_A_CLK0_DIV 64
+#define CLKID_SD_EMMC_B_CLK0_SEL 65
+#define CLKID_SD_EMMC_B_CLK0_DIV 66
+#define CLKID_SD_EMMC_C_CLK0_SEL 67
+#define CLKID_SD_EMMC_C_CLK0_DIV 68
+#define CLKID_MPLL0_DIV 69
+#define CLKID_MPLL1_DIV 70
+#define CLKID_MPLL2_DIV 71
+#define CLKID_MPLL3_DIV 72
+#define CLKID_MPLL_PREDIV 73
#define CLKID_HIFI_PLL 74
+#define CLKID_FCLK_DIV2_DIV 75
+#define CLKID_FCLK_DIV3_DIV 76
+#define CLKID_FCLK_DIV4_DIV 77
+#define CLKID_FCLK_DIV5_DIV 78
+#define CLKID_FCLK_DIV7_DIV 79
#define CLKID_VCLK2_VENCI0 80
#define CLKID_VCLK2_VENCI1 81
#define CLKID_VCLK2_VENCP0 82
@@ -90,26 +108,54 @@
#define CLKID_VCLK2_VENCL 97
#define CLKID_VCLK2_OTHER1 98
#define CLKID_FCLK_DIV2P5 99
+#define CLKID_FCLK_DIV2P5_DIV 100
+#define CLKID_FIXED_PLL_DCO 101
+#define CLKID_SYS_PLL_DCO 102
+#define CLKID_GP0_PLL_DCO 103
+#define CLKID_HIFI_PLL_DCO 104
#define CLKID_DMA 105
#define CLKID_EFUSE 106
#define CLKID_ROM_BOOT 107
#define CLKID_RESET_SEC 108
#define CLKID_SEC_AHB_APB3 109
#define CLKID_VPU_0_SEL 110
+#define CLKID_VPU_0_DIV 111
#define CLKID_VPU_0 112
#define CLKID_VPU_1_SEL 113
+#define CLKID_VPU_1_DIV 114
#define CLKID_VPU_1 115
#define CLKID_VPU 116
#define CLKID_VAPB_0_SEL 117
+#define CLKID_VAPB_0_DIV 118
#define CLKID_VAPB_0 119
#define CLKID_VAPB_1_SEL 120
+#define CLKID_VAPB_1_DIV 121
#define CLKID_VAPB_1 122
#define CLKID_VAPB_SEL 123
#define CLKID_VAPB 124
+#define CLKID_HDMI_PLL_DCO 125
+#define CLKID_HDMI_PLL_OD 126
+#define CLKID_HDMI_PLL_OD2 127
#define CLKID_HDMI_PLL 128
#define CLKID_VID_PLL 129
+#define CLKID_VID_PLL_SEL 130
+#define CLKID_VID_PLL_DIV 131
+#define CLKID_VCLK_SEL 132
+#define CLKID_VCLK2_SEL 133
+#define CLKID_VCLK_INPUT 134
+#define CLKID_VCLK2_INPUT 135
+#define CLKID_VCLK_DIV 136
+#define CLKID_VCLK2_DIV 137
#define CLKID_VCLK 138
#define CLKID_VCLK2 139
+#define CLKID_VCLK_DIV2_EN 140
+#define CLKID_VCLK_DIV4_EN 141
+#define CLKID_VCLK_DIV6_EN 142
+#define CLKID_VCLK_DIV12_EN 143
+#define CLKID_VCLK2_DIV2_EN 144
+#define CLKID_VCLK2_DIV4_EN 145
+#define CLKID_VCLK2_DIV6_EN 146
+#define CLKID_VCLK2_DIV12_EN 147
#define CLKID_VCLK_DIV1 148
#define CLKID_VCLK_DIV2 149
#define CLKID_VCLK_DIV4 150
@@ -120,33 +166,117 @@
#define CLKID_VCLK2_DIV4 155
#define CLKID_VCLK2_DIV6 156
#define CLKID_VCLK2_DIV12 157
+#define CLKID_CTS_ENCI_SEL 158
+#define CLKID_CTS_ENCP_SEL 159
+#define CLKID_CTS_VDAC_SEL 160
+#define CLKID_HDMI_TX_SEL 161
#define CLKID_CTS_ENCI 162
#define CLKID_CTS_ENCP 163
#define CLKID_CTS_VDAC 164
#define CLKID_HDMI_TX 165
+#define CLKID_HDMI_SEL 166
+#define CLKID_HDMI_DIV 167
#define CLKID_HDMI 168
#define CLKID_MALI_0_SEL 169
+#define CLKID_MALI_0_DIV 170
#define CLKID_MALI_0 171
#define CLKID_MALI_1_SEL 172
+#define CLKID_MALI_1_DIV 173
#define CLKID_MALI_1 174
#define CLKID_MALI 175
+#define CLKID_MPLL_50M_DIV 176
#define CLKID_MPLL_50M 177
+#define CLKID_SYS_PLL_DIV16_EN 178
+#define CLKID_SYS_PLL_DIV16 179
+#define CLKID_CPU_CLK_DYN0_SEL 180
+#define CLKID_CPU_CLK_DYN0_DIV 181
+#define CLKID_CPU_CLK_DYN0 182
+#define CLKID_CPU_CLK_DYN1_SEL 183
+#define CLKID_CPU_CLK_DYN1_DIV 184
+#define CLKID_CPU_CLK_DYN1 185
+#define CLKID_CPU_CLK_DYN 186
#define CLKID_CPU_CLK 187
+#define CLKID_CPU_CLK_DIV16_EN 188
+#define CLKID_CPU_CLK_DIV16 189
+#define CLKID_CPU_CLK_APB_DIV 190
+#define CLKID_CPU_CLK_APB 191
+#define CLKID_CPU_CLK_ATB_DIV 192
+#define CLKID_CPU_CLK_ATB 193
+#define CLKID_CPU_CLK_AXI_DIV 194
+#define CLKID_CPU_CLK_AXI 195
+#define CLKID_CPU_CLK_TRACE_DIV 196
+#define CLKID_CPU_CLK_TRACE 197
+#define CLKID_PCIE_PLL_DCO 198
+#define CLKID_PCIE_PLL_DCO_DIV2 199
+#define CLKID_PCIE_PLL_OD 200
#define CLKID_PCIE_PLL 201
+#define CLKID_VDEC_1_SEL 202
+#define CLKID_VDEC_1_DIV 203
#define CLKID_VDEC_1 204
+#define CLKID_VDEC_HEVC_SEL 205
+#define CLKID_VDEC_HEVC_DIV 206
#define CLKID_VDEC_HEVC 207
+#define CLKID_VDEC_HEVCF_SEL 208
+#define CLKID_VDEC_HEVCF_DIV 209
#define CLKID_VDEC_HEVCF 210
+#define CLKID_TS_DIV 211
#define CLKID_TS 212
+#define CLKID_SYS1_PLL_DCO 213
+#define CLKID_SYS1_PLL 214
+#define CLKID_SYS1_PLL_DIV16_EN 215
+#define CLKID_SYS1_PLL_DIV16 216
+#define CLKID_CPUB_CLK_DYN0_SEL 217
+#define CLKID_CPUB_CLK_DYN0_DIV 218
+#define CLKID_CPUB_CLK_DYN0 219
+#define CLKID_CPUB_CLK_DYN1_SEL 220
+#define CLKID_CPUB_CLK_DYN1_DIV 221
+#define CLKID_CPUB_CLK_DYN1 222
+#define CLKID_CPUB_CLK_DYN 223
#define CLKID_CPUB_CLK 224
+#define CLKID_CPUB_CLK_DIV16_EN 225
+#define CLKID_CPUB_CLK_DIV16 226
+#define CLKID_CPUB_CLK_DIV2 227
+#define CLKID_CPUB_CLK_DIV3 228
+#define CLKID_CPUB_CLK_DIV4 229
+#define CLKID_CPUB_CLK_DIV5 230
+#define CLKID_CPUB_CLK_DIV6 231
+#define CLKID_CPUB_CLK_DIV7 232
+#define CLKID_CPUB_CLK_DIV8 233
+#define CLKID_CPUB_CLK_APB_SEL 234
+#define CLKID_CPUB_CLK_APB 235
+#define CLKID_CPUB_CLK_ATB_SEL 236
+#define CLKID_CPUB_CLK_ATB 237
+#define CLKID_CPUB_CLK_AXI_SEL 238
+#define CLKID_CPUB_CLK_AXI 239
+#define CLKID_CPUB_CLK_TRACE_SEL 240
+#define CLKID_CPUB_CLK_TRACE 241
+#define CLKID_GP1_PLL_DCO 242
#define CLKID_GP1_PLL 243
+#define CLKID_DSU_CLK_DYN0_SEL 244
+#define CLKID_DSU_CLK_DYN0_DIV 245
+#define CLKID_DSU_CLK_DYN0 246
+#define CLKID_DSU_CLK_DYN1_SEL 247
+#define CLKID_DSU_CLK_DYN1_DIV 248
+#define CLKID_DSU_CLK_DYN1 249
+#define CLKID_DSU_CLK_DYN 250
+#define CLKID_DSU_CLK_FINAL 251
#define CLKID_DSU_CLK 252
#define CLKID_CPU1_CLK 253
#define CLKID_CPU2_CLK 254
#define CLKID_CPU3_CLK 255
+#define CLKID_SPICC0_SCLK_SEL 256
+#define CLKID_SPICC0_SCLK_DIV 257
#define CLKID_SPICC0_SCLK 258
+#define CLKID_SPICC1_SCLK_SEL 259
+#define CLKID_SPICC1_SCLK_DIV 260
#define CLKID_SPICC1_SCLK 261
+#define CLKID_NNA_AXI_CLK_SEL 262
+#define CLKID_NNA_AXI_CLK_DIV 263
#define CLKID_NNA_AXI_CLK 264
+#define CLKID_NNA_CORE_CLK_SEL 265
+#define CLKID_NNA_CORE_CLK_DIV 266
#define CLKID_NNA_CORE_CLK 267
+#define CLKID_MIPI_DSI_PXCLK_DIV 268
#define CLKID_MIPI_DSI_PXCLK_SEL 269
#define CLKID_MIPI_DSI_PXCLK 270
--
2.34.1
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 09/18] dt-bindings: clk: g12a-aoclkc: expose all clock ids
2023-06-07 10:56 [PATCH 00/18] clk: meson: move all private clk IDs to public dt-bindings headers Neil Armstrong
` (6 preceding siblings ...)
2023-06-07 10:56 ` [PATCH 08/18] dt-bindings: clk: g12a-clks: " Neil Armstrong
@ 2023-06-07 10:56 ` Neil Armstrong
2023-06-10 16:38 ` Krzysztof Kozlowski
2023-06-07 10:56 ` [PATCH 10/18] dt-bindings: clk: meson8b-clkc: " Neil Armstrong
` (8 subsequent siblings)
16 siblings, 1 reply; 35+ messages in thread
From: Neil Armstrong @ 2023-06-07 10:56 UTC (permalink / raw)
To: Jerome Brunet, Michael Turquette, Stephen Boyd, Kevin Hilman,
Martin Blumenstingl, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-amlogic, linux-clk, linux-arm-kernel, linux-kernel,
devicetree, Neil Armstrong
Due to a policy change in clock ID bindings handling, expose
all the "private" clock IDs to the public clock dt-bindings
to move out of the previous maintenance scheme.
This refers to a discussion at [1] & [2] with Krzysztof about
the issue with the current maintenance.
It was decided to move every g12a-aoclkc ID to the public clock
dt-bindings headers to be merged in a single tree so we
can safely add new clocks without having merge issues.
[1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/
[2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
drivers/clk/meson/g12a-aoclk.h | 17 -----------------
include/dt-bindings/clock/g12a-aoclkc.h | 7 +++++++
2 files changed, 7 insertions(+), 17 deletions(-)
diff --git a/drivers/clk/meson/g12a-aoclk.h b/drivers/clk/meson/g12a-aoclk.h
index 077bd25b94a1..9d6eeb24ae0c 100644
--- a/drivers/clk/meson/g12a-aoclk.h
+++ b/drivers/clk/meson/g12a-aoclk.h
@@ -7,23 +7,6 @@
#ifndef __G12A_AOCLKC_H
#define __G12A_AOCLKC_H
-/*
- * CLKID index values
- *
- * These indices are entirely contrived and do not map onto the hardware.
- * It has now been decided to expose everything by default in the DT header:
- * include/dt-bindings/clock/g12a-aoclkc.h. Only the clocks ids we don't want
- * to expose, such as the internal muxes and dividers of composite clocks,
- * will remain defined here.
- */
-#define CLKID_AO_SAR_ADC_DIV 17
-#define CLKID_AO_32K_PRE 20
-#define CLKID_AO_32K_DIV 21
-#define CLKID_AO_32K_SEL 22
-#define CLKID_AO_CEC_PRE 24
-#define CLKID_AO_CEC_DIV 25
-#define CLKID_AO_CEC_SEL 26
-
#include <dt-bindings/clock/g12a-aoclkc.h>
#include <dt-bindings/reset/g12a-aoclkc.h>
diff --git a/include/dt-bindings/clock/g12a-aoclkc.h b/include/dt-bindings/clock/g12a-aoclkc.h
index e916e49ff288..8fe7712fb12d 100644
--- a/include/dt-bindings/clock/g12a-aoclkc.h
+++ b/include/dt-bindings/clock/g12a-aoclkc.h
@@ -26,10 +26,17 @@
#define CLKID_AO_M4_FCLK 13
#define CLKID_AO_M4_HCLK 14
#define CLKID_AO_CLK81 15
+#define CLKID_AO_SAR_ADC_DIV 17
#define CLKID_AO_SAR_ADC_SEL 16
#define CLKID_AO_SAR_ADC_CLK 18
#define CLKID_AO_CTS_OSCIN 19
+#define CLKID_AO_32K_PRE 20
+#define CLKID_AO_32K_DIV 21
+#define CLKID_AO_32K_SEL 22
#define CLKID_AO_32K 23
+#define CLKID_AO_CEC_PRE 24
+#define CLKID_AO_CEC_DIV 25
+#define CLKID_AO_CEC_SEL 26
#define CLKID_AO_CEC 27
#define CLKID_AO_CTS_RTC_OSCIN 28
--
2.34.1
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 10/18] dt-bindings: clk: meson8b-clkc: expose all clock ids
2023-06-07 10:56 [PATCH 00/18] clk: meson: move all private clk IDs to public dt-bindings headers Neil Armstrong
` (7 preceding siblings ...)
2023-06-07 10:56 ` [PATCH 09/18] dt-bindings: clk: g12a-aoclkc: " Neil Armstrong
@ 2023-06-07 10:56 ` Neil Armstrong
2023-06-10 16:38 ` Krzysztof Kozlowski
2023-06-07 10:56 ` [PATCH 11/18] dt-bindings: clk: amlogic,a1-peripherals-clkc: " Neil Armstrong
` (7 subsequent siblings)
16 siblings, 1 reply; 35+ messages in thread
From: Neil Armstrong @ 2023-06-07 10:56 UTC (permalink / raw)
To: Jerome Brunet, Michael Turquette, Stephen Boyd, Kevin Hilman,
Martin Blumenstingl, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-amlogic, linux-clk, linux-arm-kernel, linux-kernel,
devicetree, Neil Armstrong
Due to a policy change in clock ID bindings handling, expose
all the "private" clock IDs to the public clock dt-bindings
to move out of the previous maintenance scheme.
This refers to a discussion at [1] & [2] with Krzysztof about
the issue with the current maintenance.
It was decided to move every meson8b-clkc ID to the public clock
dt-bindings headers to be merged in a single tree so we
can safely add new clocks without having merge issues.
[1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/
[2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
drivers/clk/meson/meson8b.h | 108 -------------------------------
include/dt-bindings/clock/meson8b-clkc.h | 97 +++++++++++++++++++++++++++
2 files changed, 97 insertions(+), 108 deletions(-)
diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index f999655d4436..2a9c4fe29ca2 100644
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -77,114 +77,6 @@
#define HHI_MPLL_CNTL9 0x2A0 /* 0xa8 offset in data sheet */
#define HHI_MPLL_CNTL10 0x2A4 /* 0xa9 offset in data sheet */
-/*
- * CLKID index values
- *
- * These indices are entirely contrived and do not map onto the hardware.
- * It has now been decided to expose everything by default in the DT header:
- * include/dt-bindings/clock/gxbb-clkc.h. Only the clocks ids we don't want
- * to expose, such as the internal muxes and dividers of composite clocks,
- * will remain defined here.
- */
-
-#define CLKID_MPLL0_DIV 96
-#define CLKID_MPLL1_DIV 97
-#define CLKID_MPLL2_DIV 98
-#define CLKID_CPU_IN_SEL 99
-#define CLKID_CPU_IN_DIV2 100
-#define CLKID_CPU_IN_DIV3 101
-#define CLKID_CPU_SCALE_DIV 102
-#define CLKID_CPU_SCALE_OUT_SEL 103
-#define CLKID_MPLL_PREDIV 104
-#define CLKID_FCLK_DIV2_DIV 105
-#define CLKID_FCLK_DIV3_DIV 106
-#define CLKID_FCLK_DIV4_DIV 107
-#define CLKID_FCLK_DIV5_DIV 108
-#define CLKID_FCLK_DIV7_DIV 109
-#define CLKID_NAND_SEL 110
-#define CLKID_NAND_DIV 111
-#define CLKID_PLL_FIXED_DCO 113
-#define CLKID_HDMI_PLL_DCO 114
-#define CLKID_PLL_SYS_DCO 115
-#define CLKID_CPU_CLK_DIV2 116
-#define CLKID_CPU_CLK_DIV3 117
-#define CLKID_CPU_CLK_DIV4 118
-#define CLKID_CPU_CLK_DIV5 119
-#define CLKID_CPU_CLK_DIV6 120
-#define CLKID_CPU_CLK_DIV7 121
-#define CLKID_CPU_CLK_DIV8 122
-#define CLKID_APB_SEL 123
-#define CLKID_PERIPH_SEL 125
-#define CLKID_AXI_SEL 127
-#define CLKID_L2_DRAM_SEL 129
-#define CLKID_HDMI_PLL_LVDS_OUT 131
-#define CLKID_VID_PLL_IN_SEL 133
-#define CLKID_VID_PLL_IN_EN 134
-#define CLKID_VID_PLL_PRE_DIV 135
-#define CLKID_VID_PLL_POST_DIV 136
-#define CLKID_VCLK_IN_EN 139
-#define CLKID_VCLK_DIV1 140
-#define CLKID_VCLK_DIV2_DIV 141
-#define CLKID_VCLK_DIV2 142
-#define CLKID_VCLK_DIV4_DIV 143
-#define CLKID_VCLK_DIV4 144
-#define CLKID_VCLK_DIV6_DIV 145
-#define CLKID_VCLK_DIV6 146
-#define CLKID_VCLK_DIV12_DIV 147
-#define CLKID_VCLK_DIV12 148
-#define CLKID_VCLK2_IN_EN 150
-#define CLKID_VCLK2_DIV1 151
-#define CLKID_VCLK2_DIV2_DIV 152
-#define CLKID_VCLK2_DIV2 153
-#define CLKID_VCLK2_DIV4_DIV 154
-#define CLKID_VCLK2_DIV4 155
-#define CLKID_VCLK2_DIV6_DIV 156
-#define CLKID_VCLK2_DIV6 157
-#define CLKID_VCLK2_DIV12_DIV 158
-#define CLKID_VCLK2_DIV12 159
-#define CLKID_CTS_ENCT_SEL 160
-#define CLKID_CTS_ENCP_SEL 162
-#define CLKID_CTS_ENCI_SEL 164
-#define CLKID_HDMI_TX_PIXEL_SEL 166
-#define CLKID_CTS_ENCL_SEL 168
-#define CLKID_CTS_VDAC0_SEL 170
-#define CLKID_HDMI_SYS_SEL 172
-#define CLKID_HDMI_SYS_DIV 173
-#define CLKID_MALI_0_SEL 175
-#define CLKID_MALI_0_DIV 176
-#define CLKID_MALI_0 177
-#define CLKID_MALI_1_SEL 178
-#define CLKID_MALI_1_DIV 179
-#define CLKID_MALI_1 180
-#define CLKID_GP_PLL_DCO 181
-#define CLKID_GP_PLL 182
-#define CLKID_VPU_0_SEL 183
-#define CLKID_VPU_0_DIV 184
-#define CLKID_VPU_0 185
-#define CLKID_VPU_1_SEL 186
-#define CLKID_VPU_1_DIV 187
-#define CLKID_VPU_1 189
-#define CLKID_VDEC_1_SEL 191
-#define CLKID_VDEC_1_1_DIV 192
-#define CLKID_VDEC_1_1 193
-#define CLKID_VDEC_1_2_DIV 194
-#define CLKID_VDEC_1_2 195
-#define CLKID_VDEC_HCODEC_SEL 197
-#define CLKID_VDEC_HCODEC_DIV 198
-#define CLKID_VDEC_2_SEL 200
-#define CLKID_VDEC_2_DIV 201
-#define CLKID_VDEC_HEVC_SEL 203
-#define CLKID_VDEC_HEVC_DIV 204
-#define CLKID_VDEC_HEVC_EN 205
-#define CLKID_CTS_AMCLK_SEL 207
-#define CLKID_CTS_AMCLK_DIV 208
-#define CLKID_CTS_MCLK_I958_SEL 210
-#define CLKID_CTS_MCLK_I958_DIV 211
-#define CLKID_VCLK_EN 214
-#define CLKID_VCLK2_EN 215
-#define CLKID_VID_PLL_LVDS_EN 216
-#define CLKID_HDMI_PLL_DCO_IN 217
-
/*
* include the CLKID and RESETID that have
* been made part of the stable DT binding
diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
index 78aa07fd7cc0..385bf243c56c 100644
--- a/include/dt-bindings/clock/meson8b-clkc.h
+++ b/include/dt-bindings/clock/meson8b-clkc.h
@@ -100,29 +100,126 @@
#define CLKID_MPLL0 93
#define CLKID_MPLL1 94
#define CLKID_MPLL2 95
+#define CLKID_MPLL0_DIV 96
+#define CLKID_MPLL1_DIV 97
+#define CLKID_MPLL2_DIV 98
+#define CLKID_CPU_IN_SEL 99
+#define CLKID_CPU_IN_DIV2 100
+#define CLKID_CPU_IN_DIV3 101
+#define CLKID_CPU_SCALE_DIV 102
+#define CLKID_CPU_SCALE_OUT_SEL 103
+#define CLKID_MPLL_PREDIV 104
+#define CLKID_FCLK_DIV2_DIV 105
+#define CLKID_FCLK_DIV3_DIV 106
+#define CLKID_FCLK_DIV4_DIV 107
+#define CLKID_FCLK_DIV5_DIV 108
+#define CLKID_FCLK_DIV7_DIV 109
+#define CLKID_NAND_SEL 110
+#define CLKID_NAND_DIV 111
#define CLKID_NAND_CLK 112
+#define CLKID_PLL_FIXED_DCO 113
+#define CLKID_HDMI_PLL_DCO 114
+#define CLKID_PLL_SYS_DCO 115
+#define CLKID_CPU_CLK_DIV2 116
+#define CLKID_CPU_CLK_DIV3 117
+#define CLKID_CPU_CLK_DIV4 118
+#define CLKID_CPU_CLK_DIV5 119
+#define CLKID_CPU_CLK_DIV6 120
+#define CLKID_CPU_CLK_DIV7 121
+#define CLKID_CPU_CLK_DIV8 122
+#define CLKID_APB_SEL 123
#define CLKID_APB 124
+#define CLKID_PERIPH_SEL 125
#define CLKID_PERIPH 126
+#define CLKID_AXI_SEL 127
#define CLKID_AXI 128
#define CLKID_L2_DRAM 130
+#define CLKID_L2_DRAM_SEL 129
+#define CLKID_HDMI_PLL_LVDS_OUT 131
#define CLKID_HDMI_PLL_HDMI_OUT 132
+#define CLKID_VID_PLL_IN_SEL 133
+#define CLKID_VID_PLL_IN_EN 134
+#define CLKID_VID_PLL_PRE_DIV 135
+#define CLKID_VID_PLL_POST_DIV 136
#define CLKID_VID_PLL_FINAL_DIV 137
#define CLKID_VCLK_IN_SEL 138
+#define CLKID_VCLK_IN_EN 139
+#define CLKID_VCLK_DIV1 140
+#define CLKID_VCLK_DIV2_DIV 141
+#define CLKID_VCLK_DIV2 142
+#define CLKID_VCLK_DIV4_DIV 143
+#define CLKID_VCLK_DIV4 144
+#define CLKID_VCLK_DIV6_DIV 145
+#define CLKID_VCLK_DIV6 146
+#define CLKID_VCLK_DIV12_DIV 147
+#define CLKID_VCLK_DIV12 148
#define CLKID_VCLK2_IN_SEL 149
+#define CLKID_VCLK2_IN_EN 150
+#define CLKID_VCLK2_DIV1 151
+#define CLKID_VCLK2_DIV2_DIV 152
+#define CLKID_VCLK2_DIV2 153
+#define CLKID_VCLK2_DIV4_DIV 154
+#define CLKID_VCLK2_DIV4 155
+#define CLKID_VCLK2_DIV6_DIV 156
+#define CLKID_VCLK2_DIV6 157
+#define CLKID_VCLK2_DIV12_DIV 158
+#define CLKID_VCLK2_DIV12 159
+#define CLKID_CTS_ENCT_SEL 160
#define CLKID_CTS_ENCT 161
+#define CLKID_CTS_ENCP_SEL 162
#define CLKID_CTS_ENCP 163
+#define CLKID_CTS_ENCI_SEL 164
#define CLKID_CTS_ENCI 165
+#define CLKID_HDMI_TX_PIXEL_SEL 166
#define CLKID_HDMI_TX_PIXEL 167
+#define CLKID_CTS_ENCL_SEL 168
#define CLKID_CTS_ENCL 169
+#define CLKID_CTS_VDAC0_SEL 170
#define CLKID_CTS_VDAC0 171
+#define CLKID_HDMI_SYS_SEL 172
+#define CLKID_HDMI_SYS_DIV 173
#define CLKID_HDMI_SYS 174
+#define CLKID_MALI_0_SEL 175
+#define CLKID_MALI_0_DIV 176
+#define CLKID_MALI_0 177
+#define CLKID_MALI_1_SEL 178
+#define CLKID_MALI_1_DIV 179
+#define CLKID_MALI_1 180
+#define CLKID_GP_PLL_DCO 181
+#define CLKID_GP_PLL 182
+#define CLKID_VPU_0_SEL 183
+#define CLKID_VPU_0_DIV 184
+#define CLKID_VPU_0 185
+#define CLKID_VPU_1_SEL 186
+#define CLKID_VPU_1_DIV 187
+#define CLKID_VPU_1 189
#define CLKID_VPU 190
+#define CLKID_VDEC_1_SEL 191
+#define CLKID_VDEC_1_1_DIV 192
+#define CLKID_VDEC_1_1 193
+#define CLKID_VDEC_1_2_DIV 194
+#define CLKID_VDEC_1_2 195
#define CLKID_VDEC_1 196
+#define CLKID_VDEC_HCODEC_SEL 197
+#define CLKID_VDEC_HCODEC_DIV 198
#define CLKID_VDEC_HCODEC 199
+#define CLKID_VDEC_2_SEL 200
+#define CLKID_VDEC_2_DIV 201
#define CLKID_VDEC_2 202
+#define CLKID_VDEC_HEVC_SEL 203
+#define CLKID_VDEC_HEVC_DIV 204
+#define CLKID_VDEC_HEVC_EN 205
#define CLKID_VDEC_HEVC 206
+#define CLKID_CTS_AMCLK_SEL 207
+#define CLKID_CTS_AMCLK_DIV 208
#define CLKID_CTS_AMCLK 209
+#define CLKID_CTS_MCLK_I958_SEL 210
+#define CLKID_CTS_MCLK_I958_DIV 211
#define CLKID_CTS_MCLK_I958 212
#define CLKID_CTS_I958 213
+#define CLKID_VCLK_EN 214
+#define CLKID_VCLK2_EN 215
+#define CLKID_VID_PLL_LVDS_EN 216
+#define CLKID_HDMI_PLL_DCO_IN 217
#endif /* __MESON8B_CLKC_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 11/18] dt-bindings: clk: amlogic,a1-peripherals-clkc: expose all clock ids
2023-06-07 10:56 [PATCH 00/18] clk: meson: move all private clk IDs to public dt-bindings headers Neil Armstrong
` (8 preceding siblings ...)
2023-06-07 10:56 ` [PATCH 10/18] dt-bindings: clk: meson8b-clkc: " Neil Armstrong
@ 2023-06-07 10:56 ` Neil Armstrong
2023-06-09 12:04 ` Dmitry Rokosov
2023-06-10 16:38 ` Krzysztof Kozlowski
2023-06-07 10:56 ` [PATCH 12/18] dt-bindings: clk: amlogic,a1-pll-clkc: " Neil Armstrong
` (6 subsequent siblings)
16 siblings, 2 replies; 35+ messages in thread
From: Neil Armstrong @ 2023-06-07 10:56 UTC (permalink / raw)
To: Jerome Brunet, Michael Turquette, Stephen Boyd, Kevin Hilman,
Martin Blumenstingl, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-amlogic, linux-clk, linux-arm-kernel, linux-kernel,
devicetree, Neil Armstrong
Due to a policy change in clock ID bindings handling, expose
all the "private" clock IDs to the public clock dt-bindings
to move out of the previous maintenance scheme.
This refers to a discussion at [1] & [2] with Krzysztof about
the issue with the current maintenance.
It was decided to move every A1 peripherals ID to the public clock
dt-bindings headers to be merged in a single tree so we
can safely add new clocks without having merge issues.
[1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/
[2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
drivers/clk/meson/a1-peripherals.h | 63 ----------------------
.../clock/amlogic,a1-peripherals-clkc.h | 53 ++++++++++++++++++
2 files changed, 53 insertions(+), 63 deletions(-)
diff --git a/drivers/clk/meson/a1-peripherals.h b/drivers/clk/meson/a1-peripherals.h
index 4d60456a95a9..842b52634ed0 100644
--- a/drivers/clk/meson/a1-peripherals.h
+++ b/drivers/clk/meson/a1-peripherals.h
@@ -46,67 +46,4 @@
/* include the CLKIDs that have been made part of the DT binding */
#include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
-/*
- * CLKID index values for internal clocks
- *
- * These indices are entirely contrived and do not map onto the hardware.
- * It has now been decided to expose everything by default in the DT header:
- * include/dt-bindings/clock/a1-peripherals-clkc.h.
- * Only the clocks ids we don't want to expose, such as the internal muxes and
- * dividers of composite clocks, will remain defined here.
- */
-#define CLKID_XTAL_IN 0
-#define CLKID_DSPA_SEL 61
-#define CLKID_DSPB_SEL 62
-#define CLKID_SARADC_SEL 74
-#define CLKID_SYS_A_SEL 89
-#define CLKID_SYS_A_DIV 90
-#define CLKID_SYS_A 91
-#define CLKID_SYS_B_SEL 92
-#define CLKID_SYS_B_DIV 93
-#define CLKID_SYS_B 94
-#define CLKID_DSPA_A_DIV 96
-#define CLKID_DSPA_A 97
-#define CLKID_DSPA_B_DIV 99
-#define CLKID_DSPA_B 100
-#define CLKID_DSPB_A_DIV 102
-#define CLKID_DSPB_A 103
-#define CLKID_DSPB_B_DIV 105
-#define CLKID_DSPB_B 106
-#define CLKID_RTC_32K_IN 107
-#define CLKID_RTC_32K_DIV 108
-#define CLKID_RTC_32K_XTAL 109
-#define CLKID_RTC_32K_SEL 110
-#define CLKID_CECB_32K_IN 111
-#define CLKID_CECB_32K_DIV 112
-#define CLKID_CECA_32K_IN 115
-#define CLKID_CECA_32K_DIV 116
-#define CLKID_DIV2_PRE 119
-#define CLKID_24M_DIV2 120
-#define CLKID_GEN_DIV 122
-#define CLKID_SARADC_DIV 123
-#define CLKID_PWM_A_DIV 125
-#define CLKID_PWM_B_DIV 127
-#define CLKID_PWM_C_DIV 129
-#define CLKID_PWM_D_DIV 131
-#define CLKID_PWM_E_DIV 133
-#define CLKID_PWM_F_DIV 135
-#define CLKID_SPICC_SEL 136
-#define CLKID_SPICC_DIV 137
-#define CLKID_SPICC_SEL2 138
-#define CLKID_TS_DIV 139
-#define CLKID_SPIFC_SEL 140
-#define CLKID_SPIFC_DIV 141
-#define CLKID_SPIFC_SEL2 142
-#define CLKID_USB_BUS_SEL 143
-#define CLKID_USB_BUS_DIV 144
-#define CLKID_SD_EMMC_SEL 145
-#define CLKID_SD_EMMC_DIV 146
-#define CLKID_PSRAM_SEL 148
-#define CLKID_PSRAM_DIV 149
-#define CLKID_PSRAM_SEL2 150
-#define CLKID_DMC_SEL 151
-#define CLKID_DMC_DIV 152
-#define CLKID_DMC_SEL2 153
-
#endif /* __A1_PERIPHERALS_H */
diff --git a/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h b/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h
index ff2730f398a6..06f198ee7623 100644
--- a/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h
+++ b/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h
@@ -10,6 +10,7 @@
#ifndef __A1_PERIPHERALS_CLKC_H
#define __A1_PERIPHERALS_CLKC_H
+#define CLKID_XTAL_IN 0
#define CLKID_FIXPLL_IN 1
#define CLKID_USB_PHY_IN 2
#define CLKID_USB_CTRL_IN 3
@@ -70,6 +71,8 @@
#define CLKID_CPU_CTRL 58
#define CLKID_ROM 59
#define CLKID_PROC_I2C 60
+#define CLKID_DSPA_SEL 61
+#define CLKID_DSPB_SEL 62
#define CLKID_DSPA_EN 63
#define CLKID_DSPA_EN_NIC 64
#define CLKID_DSPB_EN 65
@@ -81,6 +84,7 @@
#define CLKID_12M 71
#define CLKID_FCLK_DIV2_DIVN 72
#define CLKID_GEN 73
+#define CLKID_SARADC_SEL 74
#define CLKID_SARADC 75
#define CLKID_PWM_A 76
#define CLKID_PWM_B 77
@@ -95,21 +99,70 @@
#define CLKID_SD_EMMC 86
#define CLKID_PSRAM 87
#define CLKID_DMC 88
+#define CLKID_SYS_A_SEL 89
+#define CLKID_SYS_A_DIV 90
+#define CLKID_SYS_A 91
+#define CLKID_SYS_B_SEL 92
+#define CLKID_SYS_B_DIV 93
+#define CLKID_SYS_B 94
#define CLKID_DSPA_A_SEL 95
+#define CLKID_DSPA_A_DIV 96
+#define CLKID_DSPA_A 97
#define CLKID_DSPA_B_SEL 98
+#define CLKID_DSPA_B_DIV 99
+#define CLKID_DSPA_B 100
#define CLKID_DSPB_A_SEL 101
+#define CLKID_DSPB_A_DIV 102
+#define CLKID_DSPB_A 103
#define CLKID_DSPB_B_SEL 104
+#define CLKID_DSPB_B_DIV 105
+#define CLKID_DSPB_B 106
+#define CLKID_RTC_32K_IN 107
+#define CLKID_RTC_32K_DIV 108
+#define CLKID_RTC_32K_XTAL 109
+#define CLKID_RTC_32K_SEL 110
+#define CLKID_CECB_32K_IN 111
+#define CLKID_CECB_32K_DIV 112
#define CLKID_CECB_32K_SEL_PRE 113
#define CLKID_CECB_32K_SEL 114
+#define CLKID_CECA_32K_IN 115
+#define CLKID_CECA_32K_DIV 116
#define CLKID_CECA_32K_SEL_PRE 117
#define CLKID_CECA_32K_SEL 118
+#define CLKID_DIV2_PRE 119
+#define CLKID_24M_DIV2 120
#define CLKID_GEN_SEL 121
+#define CLKID_GEN_DIV 122
+#define CLKID_SARADC_DIV 123
#define CLKID_PWM_A_SEL 124
+#define CLKID_PWM_A_DIV 125
#define CLKID_PWM_B_SEL 126
+#define CLKID_PWM_B_DIV 127
#define CLKID_PWM_C_SEL 128
+#define CLKID_PWM_C_DIV 129
#define CLKID_PWM_D_SEL 130
+#define CLKID_PWM_D_DIV 131
#define CLKID_PWM_E_SEL 132
+#define CLKID_PWM_E_DIV 133
#define CLKID_PWM_F_SEL 134
+#define CLKID_PWM_F_DIV 135
+#define CLKID_SPICC_SEL 136
+#define CLKID_SPICC_DIV 137
+#define CLKID_SPICC_SEL2 138
+#define CLKID_TS_DIV 139
+#define CLKID_SPIFC_SEL 140
+#define CLKID_SPIFC_DIV 141
+#define CLKID_SPIFC_SEL2 142
+#define CLKID_USB_BUS_SEL 143
+#define CLKID_USB_BUS_DIV 144
+#define CLKID_SD_EMMC_SEL 145
+#define CLKID_SD_EMMC_DIV 146
#define CLKID_SD_EMMC_SEL2 147
+#define CLKID_PSRAM_SEL 148
+#define CLKID_PSRAM_DIV 149
+#define CLKID_PSRAM_SEL2 150
+#define CLKID_DMC_SEL 151
+#define CLKID_DMC_DIV 152
+#define CLKID_DMC_SEL2 153
#endif /* __A1_PERIPHERALS_CLKC_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 12/18] dt-bindings: clk: amlogic,a1-pll-clkc: expose all clock ids
2023-06-07 10:56 [PATCH 00/18] clk: meson: move all private clk IDs to public dt-bindings headers Neil Armstrong
` (9 preceding siblings ...)
2023-06-07 10:56 ` [PATCH 11/18] dt-bindings: clk: amlogic,a1-peripherals-clkc: " Neil Armstrong
@ 2023-06-07 10:56 ` Neil Armstrong
2023-06-09 12:10 ` Dmitry Rokosov
2023-06-10 16:39 ` Krzysztof Kozlowski
2023-06-07 10:56 ` [PATCH 13/18] dt-bindings: clk: axg-audio-clkc: " Neil Armstrong
` (5 subsequent siblings)
16 siblings, 2 replies; 35+ messages in thread
From: Neil Armstrong @ 2023-06-07 10:56 UTC (permalink / raw)
To: Jerome Brunet, Michael Turquette, Stephen Boyd, Kevin Hilman,
Martin Blumenstingl, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-amlogic, linux-clk, linux-arm-kernel, linux-kernel,
devicetree, Neil Armstrong
Due to a policy change in clock ID bindings handling, expose
all the "private" clock IDs to the public clock dt-bindings
to move out of the previous maintenance scheme.
This refers to a discussion at [1] & [2] with Krzysztof about
the issue with the current maintenance.
It was decided to move every A1 pll ID to the public clock
dt-bindings headers to be merged in a single tree so we
can safely add new clocks without having merge issues.
[1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/
[2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
drivers/clk/meson/a1-pll.h | 15 ---------------
include/dt-bindings/clock/amlogic,a1-pll-clkc.h | 5 +++++
2 files changed, 5 insertions(+), 15 deletions(-)
diff --git a/drivers/clk/meson/a1-pll.h b/drivers/clk/meson/a1-pll.h
index 82570759e6a2..0add1c7ea9f5 100644
--- a/drivers/clk/meson/a1-pll.h
+++ b/drivers/clk/meson/a1-pll.h
@@ -28,19 +28,4 @@
/* include the CLKIDs that have been made part of the DT binding */
#include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
-/*
- * CLKID index values for internal clocks
- *
- * These indices are entirely contrived and do not map onto the hardware.
- * It has now been decided to expose everything by default in the DT header:
- * include/dt-bindings/clock/a1-pll-clkc.h. Only the clocks ids we don't want
- * to expose, such as the internal muxes and dividers of composite clocks,
- * will remain defined here.
- */
-#define CLKID_FIXED_PLL_DCO 0
-#define CLKID_FCLK_DIV2_DIV 2
-#define CLKID_FCLK_DIV3_DIV 3
-#define CLKID_FCLK_DIV5_DIV 4
-#define CLKID_FCLK_DIV7_DIV 5
-
#endif /* __A1_PLL_H */
diff --git a/include/dt-bindings/clock/amlogic,a1-pll-clkc.h b/include/dt-bindings/clock/amlogic,a1-pll-clkc.h
index 01fb8164ac29..2b660c0f2c9f 100644
--- a/include/dt-bindings/clock/amlogic,a1-pll-clkc.h
+++ b/include/dt-bindings/clock/amlogic,a1-pll-clkc.h
@@ -10,7 +10,12 @@
#ifndef __A1_PLL_CLKC_H
#define __A1_PLL_CLKC_H
+#define CLKID_FIXED_PLL_DCO 0
#define CLKID_FIXED_PLL 1
+#define CLKID_FCLK_DIV2_DIV 2
+#define CLKID_FCLK_DIV3_DIV 3
+#define CLKID_FCLK_DIV5_DIV 4
+#define CLKID_FCLK_DIV7_DIV 5
#define CLKID_FCLK_DIV2 6
#define CLKID_FCLK_DIV3 7
#define CLKID_FCLK_DIV5 8
--
2.34.1
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 13/18] dt-bindings: clk: axg-audio-clkc: expose all clock ids
2023-06-07 10:56 [PATCH 00/18] clk: meson: move all private clk IDs to public dt-bindings headers Neil Armstrong
` (10 preceding siblings ...)
2023-06-07 10:56 ` [PATCH 12/18] dt-bindings: clk: amlogic,a1-pll-clkc: " Neil Armstrong
@ 2023-06-07 10:56 ` Neil Armstrong
2023-06-10 16:39 ` Krzysztof Kozlowski
2023-06-07 10:56 ` [PATCH 14/18] clk: meson: aoclk: move bindings include to main driver Neil Armstrong
` (4 subsequent siblings)
16 siblings, 1 reply; 35+ messages in thread
From: Neil Armstrong @ 2023-06-07 10:56 UTC (permalink / raw)
To: Jerome Brunet, Michael Turquette, Stephen Boyd, Kevin Hilman,
Martin Blumenstingl, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-amlogic, linux-clk, linux-arm-kernel, linux-kernel,
devicetree, Neil Armstrong
Due to a policy change in clock ID bindings handling, expose
all the "private" clock IDs to the public clock dt-bindings
to move out of the previous maintenance scheme.
This refers to a discussion at [1] & [2] with Krzysztof about
the issue with the current maintenance.
It was decided to move every axg-audio-clkc ID to the public clock
dt-bindings headers to be merged in a single tree so we
can safely add new clocks without having merge issues.
[1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/
[2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
drivers/clk/meson/axg-audio.h | 70 ------------------------------
include/dt-bindings/clock/axg-audio-clkc.h | 65 +++++++++++++++++++++++++++
2 files changed, 65 insertions(+), 70 deletions(-)
diff --git a/drivers/clk/meson/axg-audio.h b/drivers/clk/meson/axg-audio.h
index d6ed27c77729..faf08748b205 100644
--- a/drivers/clk/meson/axg-audio.h
+++ b/drivers/clk/meson/axg-audio.h
@@ -64,76 +64,6 @@
#define AUDIO_SM1_SW_RESET1 0x02C
#define AUDIO_CLK81_CTRL 0x030
#define AUDIO_CLK81_EN 0x034
-/*
- * CLKID index values
- * These indices are entirely contrived and do not map onto the hardware.
- */
-
-#define AUD_CLKID_MST_A_MCLK_SEL 59
-#define AUD_CLKID_MST_B_MCLK_SEL 60
-#define AUD_CLKID_MST_C_MCLK_SEL 61
-#define AUD_CLKID_MST_D_MCLK_SEL 62
-#define AUD_CLKID_MST_E_MCLK_SEL 63
-#define AUD_CLKID_MST_F_MCLK_SEL 64
-#define AUD_CLKID_MST_A_MCLK_DIV 65
-#define AUD_CLKID_MST_B_MCLK_DIV 66
-#define AUD_CLKID_MST_C_MCLK_DIV 67
-#define AUD_CLKID_MST_D_MCLK_DIV 68
-#define AUD_CLKID_MST_E_MCLK_DIV 69
-#define AUD_CLKID_MST_F_MCLK_DIV 70
-#define AUD_CLKID_SPDIFOUT_CLK_SEL 71
-#define AUD_CLKID_SPDIFOUT_CLK_DIV 72
-#define AUD_CLKID_SPDIFIN_CLK_SEL 73
-#define AUD_CLKID_SPDIFIN_CLK_DIV 74
-#define AUD_CLKID_PDM_DCLK_SEL 75
-#define AUD_CLKID_PDM_DCLK_DIV 76
-#define AUD_CLKID_PDM_SYSCLK_SEL 77
-#define AUD_CLKID_PDM_SYSCLK_DIV 78
-#define AUD_CLKID_MST_A_SCLK_PRE_EN 92
-#define AUD_CLKID_MST_B_SCLK_PRE_EN 93
-#define AUD_CLKID_MST_C_SCLK_PRE_EN 94
-#define AUD_CLKID_MST_D_SCLK_PRE_EN 95
-#define AUD_CLKID_MST_E_SCLK_PRE_EN 96
-#define AUD_CLKID_MST_F_SCLK_PRE_EN 97
-#define AUD_CLKID_MST_A_SCLK_DIV 98
-#define AUD_CLKID_MST_B_SCLK_DIV 99
-#define AUD_CLKID_MST_C_SCLK_DIV 100
-#define AUD_CLKID_MST_D_SCLK_DIV 101
-#define AUD_CLKID_MST_E_SCLK_DIV 102
-#define AUD_CLKID_MST_F_SCLK_DIV 103
-#define AUD_CLKID_MST_A_SCLK_POST_EN 104
-#define AUD_CLKID_MST_B_SCLK_POST_EN 105
-#define AUD_CLKID_MST_C_SCLK_POST_EN 106
-#define AUD_CLKID_MST_D_SCLK_POST_EN 107
-#define AUD_CLKID_MST_E_SCLK_POST_EN 108
-#define AUD_CLKID_MST_F_SCLK_POST_EN 109
-#define AUD_CLKID_MST_A_LRCLK_DIV 110
-#define AUD_CLKID_MST_B_LRCLK_DIV 111
-#define AUD_CLKID_MST_C_LRCLK_DIV 112
-#define AUD_CLKID_MST_D_LRCLK_DIV 113
-#define AUD_CLKID_MST_E_LRCLK_DIV 114
-#define AUD_CLKID_MST_F_LRCLK_DIV 115
-#define AUD_CLKID_TDMIN_A_SCLK_PRE_EN 137
-#define AUD_CLKID_TDMIN_B_SCLK_PRE_EN 138
-#define AUD_CLKID_TDMIN_C_SCLK_PRE_EN 139
-#define AUD_CLKID_TDMIN_LB_SCLK_PRE_EN 140
-#define AUD_CLKID_TDMOUT_A_SCLK_PRE_EN 141
-#define AUD_CLKID_TDMOUT_B_SCLK_PRE_EN 142
-#define AUD_CLKID_TDMOUT_C_SCLK_PRE_EN 143
-#define AUD_CLKID_TDMIN_A_SCLK_POST_EN 144
-#define AUD_CLKID_TDMIN_B_SCLK_POST_EN 145
-#define AUD_CLKID_TDMIN_C_SCLK_POST_EN 146
-#define AUD_CLKID_TDMIN_LB_SCLK_POST_EN 147
-#define AUD_CLKID_TDMOUT_A_SCLK_POST_EN 148
-#define AUD_CLKID_TDMOUT_B_SCLK_POST_EN 149
-#define AUD_CLKID_TDMOUT_C_SCLK_POST_EN 150
-#define AUD_CLKID_SPDIFOUT_B_CLK_SEL 153
-#define AUD_CLKID_SPDIFOUT_B_CLK_DIV 154
-#define AUD_CLKID_CLK81_EN 173
-#define AUD_CLKID_SYSCLK_A_DIV 174
-#define AUD_CLKID_SYSCLK_B_DIV 175
-#define AUD_CLKID_SYSCLK_A_EN 176
-#define AUD_CLKID_SYSCLK_B_EN 177
/* include the CLKIDs which are part of the DT bindings */
#include <dt-bindings/clock/axg-audio-clkc.h>
diff --git a/include/dt-bindings/clock/axg-audio-clkc.h b/include/dt-bindings/clock/axg-audio-clkc.h
index f561f5c5ef8f..08c82c22fa5f 100644
--- a/include/dt-bindings/clock/axg-audio-clkc.h
+++ b/include/dt-bindings/clock/axg-audio-clkc.h
@@ -37,6 +37,26 @@
#define AUD_CLKID_SPDIFIN_CLK 56
#define AUD_CLKID_PDM_DCLK 57
#define AUD_CLKID_PDM_SYSCLK 58
+#define AUD_CLKID_MST_A_MCLK_SEL 59
+#define AUD_CLKID_MST_B_MCLK_SEL 60
+#define AUD_CLKID_MST_C_MCLK_SEL 61
+#define AUD_CLKID_MST_D_MCLK_SEL 62
+#define AUD_CLKID_MST_E_MCLK_SEL 63
+#define AUD_CLKID_MST_F_MCLK_SEL 64
+#define AUD_CLKID_MST_A_MCLK_DIV 65
+#define AUD_CLKID_MST_B_MCLK_DIV 66
+#define AUD_CLKID_MST_C_MCLK_DIV 67
+#define AUD_CLKID_MST_D_MCLK_DIV 68
+#define AUD_CLKID_MST_E_MCLK_DIV 69
+#define AUD_CLKID_MST_F_MCLK_DIV 70
+#define AUD_CLKID_SPDIFOUT_CLK_SEL 71
+#define AUD_CLKID_SPDIFOUT_CLK_DIV 72
+#define AUD_CLKID_SPDIFIN_CLK_SEL 73
+#define AUD_CLKID_SPDIFIN_CLK_DIV 74
+#define AUD_CLKID_PDM_DCLK_SEL 75
+#define AUD_CLKID_PDM_DCLK_DIV 76
+#define AUD_CLKID_PDM_SYSCLK_SEL 77
+#define AUD_CLKID_PDM_SYSCLK_DIV 78
#define AUD_CLKID_MST_A_SCLK 79
#define AUD_CLKID_MST_B_SCLK 80
#define AUD_CLKID_MST_C_SCLK 81
@@ -49,6 +69,30 @@
#define AUD_CLKID_MST_D_LRCLK 89
#define AUD_CLKID_MST_E_LRCLK 90
#define AUD_CLKID_MST_F_LRCLK 91
+#define AUD_CLKID_MST_A_SCLK_PRE_EN 92
+#define AUD_CLKID_MST_B_SCLK_PRE_EN 93
+#define AUD_CLKID_MST_C_SCLK_PRE_EN 94
+#define AUD_CLKID_MST_D_SCLK_PRE_EN 95
+#define AUD_CLKID_MST_E_SCLK_PRE_EN 96
+#define AUD_CLKID_MST_F_SCLK_PRE_EN 97
+#define AUD_CLKID_MST_A_SCLK_DIV 98
+#define AUD_CLKID_MST_B_SCLK_DIV 99
+#define AUD_CLKID_MST_C_SCLK_DIV 100
+#define AUD_CLKID_MST_D_SCLK_DIV 101
+#define AUD_CLKID_MST_E_SCLK_DIV 102
+#define AUD_CLKID_MST_F_SCLK_DIV 103
+#define AUD_CLKID_MST_A_SCLK_POST_EN 104
+#define AUD_CLKID_MST_B_SCLK_POST_EN 105
+#define AUD_CLKID_MST_C_SCLK_POST_EN 106
+#define AUD_CLKID_MST_D_SCLK_POST_EN 107
+#define AUD_CLKID_MST_E_SCLK_POST_EN 108
+#define AUD_CLKID_MST_F_SCLK_POST_EN 109
+#define AUD_CLKID_MST_A_LRCLK_DIV 110
+#define AUD_CLKID_MST_B_LRCLK_DIV 111
+#define AUD_CLKID_MST_C_LRCLK_DIV 112
+#define AUD_CLKID_MST_D_LRCLK_DIV 113
+#define AUD_CLKID_MST_E_LRCLK_DIV 114
+#define AUD_CLKID_MST_F_LRCLK_DIV 115
#define AUD_CLKID_TDMIN_A_SCLK_SEL 116
#define AUD_CLKID_TDMIN_B_SCLK_SEL 117
#define AUD_CLKID_TDMIN_C_SCLK_SEL 118
@@ -70,8 +114,24 @@
#define AUD_CLKID_TDMOUT_A_LRCLK 134
#define AUD_CLKID_TDMOUT_B_LRCLK 135
#define AUD_CLKID_TDMOUT_C_LRCLK 136
+#define AUD_CLKID_TDMIN_A_SCLK_PRE_EN 137
+#define AUD_CLKID_TDMIN_B_SCLK_PRE_EN 138
+#define AUD_CLKID_TDMIN_C_SCLK_PRE_EN 139
+#define AUD_CLKID_TDMIN_LB_SCLK_PRE_EN 140
+#define AUD_CLKID_TDMOUT_A_SCLK_PRE_EN 141
+#define AUD_CLKID_TDMOUT_B_SCLK_PRE_EN 142
+#define AUD_CLKID_TDMOUT_C_SCLK_PRE_EN 143
+#define AUD_CLKID_TDMIN_A_SCLK_POST_EN 144
+#define AUD_CLKID_TDMIN_B_SCLK_POST_EN 145
+#define AUD_CLKID_TDMIN_C_SCLK_POST_EN 146
+#define AUD_CLKID_TDMIN_LB_SCLK_POST_EN 147
+#define AUD_CLKID_TDMOUT_A_SCLK_POST_EN 148
+#define AUD_CLKID_TDMOUT_B_SCLK_POST_EN 149
+#define AUD_CLKID_TDMOUT_C_SCLK_POST_EN 150
#define AUD_CLKID_SPDIFOUT_B 151
#define AUD_CLKID_SPDIFOUT_B_CLK 152
+#define AUD_CLKID_SPDIFOUT_B_CLK_SEL 153
+#define AUD_CLKID_SPDIFOUT_B_CLK_DIV 154
#define AUD_CLKID_TDM_MCLK_PAD0 155
#define AUD_CLKID_TDM_MCLK_PAD1 156
#define AUD_CLKID_TDM_LRCLK_PAD0 157
@@ -90,5 +150,10 @@
#define AUD_CLKID_FRDDR_D 170
#define AUD_CLKID_TODDR_D 171
#define AUD_CLKID_LOOPBACK_B 172
+#define AUD_CLKID_CLK81_EN 173
+#define AUD_CLKID_SYSCLK_A_DIV 174
+#define AUD_CLKID_SYSCLK_B_DIV 175
+#define AUD_CLKID_SYSCLK_A_EN 176
+#define AUD_CLKID_SYSCLK_B_EN 177
#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 14/18] clk: meson: aoclk: move bindings include to main driver
2023-06-07 10:56 [PATCH 00/18] clk: meson: move all private clk IDs to public dt-bindings headers Neil Armstrong
` (11 preceding siblings ...)
2023-06-07 10:56 ` [PATCH 13/18] dt-bindings: clk: axg-audio-clkc: " Neil Armstrong
@ 2023-06-07 10:56 ` Neil Armstrong
2023-06-07 10:56 ` [PATCH 15/18] clk: meson: eeclk: " Neil Armstrong
` (3 subsequent siblings)
16 siblings, 0 replies; 35+ messages in thread
From: Neil Armstrong @ 2023-06-07 10:56 UTC (permalink / raw)
To: Jerome Brunet, Michael Turquette, Stephen Boyd, Kevin Hilman,
Martin Blumenstingl, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-amlogic, linux-clk, linux-arm-kernel, linux-kernel,
devicetree, Neil Armstrong
Now the clock ids are no more defined in private headers,
cleanup and include the dt-bindings headers from the main
driver file.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
drivers/clk/meson/axg-aoclk.c | 4 +++-
drivers/clk/meson/axg-aoclk.h | 16 ----------------
drivers/clk/meson/g12a-aoclk.c | 4 +++-
drivers/clk/meson/g12a-aoclk.h | 13 -------------
drivers/clk/meson/gxbb-aoclk.c | 4 +++-
drivers/clk/meson/gxbb-aoclk.h | 13 -------------
6 files changed, 9 insertions(+), 45 deletions(-)
diff --git a/drivers/clk/meson/axg-aoclk.c b/drivers/clk/meson/axg-aoclk.c
index db5b53146bcc..fb470459aaf8 100644
--- a/drivers/clk/meson/axg-aoclk.c
+++ b/drivers/clk/meson/axg-aoclk.c
@@ -14,11 +14,13 @@
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include "meson-aoclk.h"
-#include "axg-aoclk.h"
#include "clk-regmap.h"
#include "clk-dualdiv.h"
+#include <dt-bindings/clock/axg-aoclkc.h>
+#include <dt-bindings/reset/axg-aoclkc.h>
+
/*
* AO Configuration Clock registers offsets
* Register offsets from the data sheet must be multiplied by 4.
diff --git a/drivers/clk/meson/axg-aoclk.h b/drivers/clk/meson/axg-aoclk.h
deleted file mode 100644
index fe23dc53aa73..000000000000
--- a/drivers/clk/meson/axg-aoclk.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
-/*
- * Copyright (c) 2017 BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- *
- * Copyright (c) 2018 Amlogic, inc.
- * Author: Qiufang Dai <qiufang.dai@amlogic.com>
- */
-
-#ifndef __AXG_AOCLKC_H
-#define __AXG_AOCLKC_H
-
-#include <dt-bindings/clock/axg-aoclkc.h>
-#include <dt-bindings/reset/axg-aoclkc.h>
-
-#endif /* __AXG_AOCLKC_H */
diff --git a/drivers/clk/meson/g12a-aoclk.c b/drivers/clk/meson/g12a-aoclk.c
index 52501ec709f7..392e1805f1c8 100644
--- a/drivers/clk/meson/g12a-aoclk.c
+++ b/drivers/clk/meson/g12a-aoclk.c
@@ -14,11 +14,13 @@
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include "meson-aoclk.h"
-#include "g12a-aoclk.h"
#include "clk-regmap.h"
#include "clk-dualdiv.h"
+#include <dt-bindings/clock/g12a-aoclkc.h>
+#include <dt-bindings/reset/g12a-aoclkc.h>
+
/*
* AO Configuration Clock registers offsets
* Register offsets from the data sheet must be multiplied by 4.
diff --git a/drivers/clk/meson/g12a-aoclk.h b/drivers/clk/meson/g12a-aoclk.h
deleted file mode 100644
index 9d6eeb24ae0c..000000000000
--- a/drivers/clk/meson/g12a-aoclk.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
-/*
- * Copyright (c) 2019 BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#ifndef __G12A_AOCLKC_H
-#define __G12A_AOCLKC_H
-
-#include <dt-bindings/clock/g12a-aoclkc.h>
-#include <dt-bindings/reset/g12a-aoclkc.h>
-
-#endif /* __G12A_AOCLKC_H */
diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c
index b08f60f5a73d..f3723c0d6a01 100644
--- a/drivers/clk/meson/gxbb-aoclk.c
+++ b/drivers/clk/meson/gxbb-aoclk.c
@@ -7,11 +7,13 @@
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include "meson-aoclk.h"
-#include "gxbb-aoclk.h"
#include "clk-regmap.h"
#include "clk-dualdiv.h"
+#include <dt-bindings/clock/gxbb-aoclkc.h>
+#include <dt-bindings/reset/gxbb-aoclkc.h>
+
/* AO Configuration Clock registers offsets */
#define AO_RTI_PWR_CNTL_REG1 0x0c
#define AO_RTI_PWR_CNTL_REG0 0x10
diff --git a/drivers/clk/meson/gxbb-aoclk.h b/drivers/clk/meson/gxbb-aoclk.h
deleted file mode 100644
index 94197b957512..000000000000
--- a/drivers/clk/meson/gxbb-aoclk.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2017 BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#ifndef __GXBB_AOCLKC_H
-#define __GXBB_AOCLKC_H
-
-#include <dt-bindings/clock/gxbb-aoclkc.h>
-#include <dt-bindings/reset/gxbb-aoclkc.h>
-
-#endif /* __GXBB_AOCLKC_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 15/18] clk: meson: eeclk: move bindings include to main driver
2023-06-07 10:56 [PATCH 00/18] clk: meson: move all private clk IDs to public dt-bindings headers Neil Armstrong
` (12 preceding siblings ...)
2023-06-07 10:56 ` [PATCH 14/18] clk: meson: aoclk: move bindings include to main driver Neil Armstrong
@ 2023-06-07 10:56 ` Neil Armstrong
2023-06-07 10:56 ` [PATCH 16/18] clk: meson: a1: " Neil Armstrong
` (2 subsequent siblings)
16 siblings, 0 replies; 35+ messages in thread
From: Neil Armstrong @ 2023-06-07 10:56 UTC (permalink / raw)
To: Jerome Brunet, Michael Turquette, Stephen Boyd, Kevin Hilman,
Martin Blumenstingl, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-amlogic, linux-clk, linux-arm-kernel, linux-kernel,
devicetree, Neil Armstrong
Now the clock ids are no more defined in private headers,
cleanup and include the dt-bindings headers from the main
driver file.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
drivers/clk/meson/axg.c | 2 ++
drivers/clk/meson/axg.h | 3 ---
drivers/clk/meson/g12a.c | 2 ++
drivers/clk/meson/g12a.h | 3 ---
drivers/clk/meson/gxbb.c | 2 ++
drivers/clk/meson/gxbb.h | 3 ---
6 files changed, 6 insertions(+), 9 deletions(-)
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index d159b47c7579..ddac23a5d535 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -21,6 +21,8 @@
#include "axg.h"
#include "meson-eeclk.h"
+#include <dt-bindings/clock/axg-clkc.h>
+
static DEFINE_SPINLOCK(meson_clk_lock);
static struct clk_regmap axg_fixed_pll_dco = {
diff --git a/drivers/clk/meson/axg.h b/drivers/clk/meson/axg.h
index ed157532b4d7..624d8d3ce7c4 100644
--- a/drivers/clk/meson/axg.h
+++ b/drivers/clk/meson/axg.h
@@ -102,7 +102,4 @@
#define HHI_DPLL_TOP_I 0x318
#define HHI_DPLL_TOP2_I 0x31C
-/* include the CLKIDs that have been made part of the DT binding */
-#include <dt-bindings/clock/axg-clkc.h>
-
#endif /* __AXG_H */
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index ee1ac3542ff4..4e218cbc457f 100644
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
@@ -25,6 +25,8 @@
#include "meson-eeclk.h"
#include "g12a.h"
+#include <dt-bindings/clock/g12a-clkc.h>
+
static DEFINE_SPINLOCK(meson_clk_lock);
static struct clk_regmap g12a_fixed_pll_dco = {
diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h
index 8e08af3c1476..f11ee3c59849 100644
--- a/drivers/clk/meson/g12a.h
+++ b/drivers/clk/meson/g12a.h
@@ -126,7 +126,4 @@
#define HHI_SYS1_PLL_CNTL5 0x394
#define HHI_SYS1_PLL_CNTL6 0x398
-/* include the CLKIDs that have been made part of the DT binding */
-#include <dt-bindings/clock/g12a-clkc.h>
-
#endif /* __G12A_H */
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 4849189cefbc..15b6c6c3114e 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -17,6 +17,8 @@
#include "meson-eeclk.h"
#include "vid-pll-div.h"
+#include <dt-bindings/clock/gxbb-clkc.h>
+
static DEFINE_SPINLOCK(meson_clk_lock);
static const struct pll_params_table gxbb_gp0_pll_params_table[] = {
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index 798ffb911103..ba5f39a8d746 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -112,7 +112,4 @@
#define HHI_BT656_CLK_CNTL 0x3D4 /* 0xf5 offset in data sheet */
#define HHI_SAR_CLK_CNTL 0x3D8 /* 0xf6 offset in data sheet */
-/* include the CLKIDs that have been made part of the DT binding */
-#include <dt-bindings/clock/gxbb-clkc.h>
-
#endif /* __GXBB_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 16/18] clk: meson: a1: move bindings include to main driver
2023-06-07 10:56 [PATCH 00/18] clk: meson: move all private clk IDs to public dt-bindings headers Neil Armstrong
` (13 preceding siblings ...)
2023-06-07 10:56 ` [PATCH 15/18] clk: meson: eeclk: " Neil Armstrong
@ 2023-06-07 10:56 ` Neil Armstrong
2023-06-07 10:56 ` [PATCH 17/18] clk: meson: meson8b: " Neil Armstrong
2023-06-07 10:56 ` [PATCH 18/18] clk: meson: axg-audio: " Neil Armstrong
16 siblings, 0 replies; 35+ messages in thread
From: Neil Armstrong @ 2023-06-07 10:56 UTC (permalink / raw)
To: Jerome Brunet, Michael Turquette, Stephen Boyd, Kevin Hilman,
Martin Blumenstingl, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-amlogic, linux-clk, linux-arm-kernel, linux-kernel,
devicetree, Neil Armstrong
Now the clock ids are no more defined in private headers,
cleanup and include the dt-bindings headers from the main
driver file.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
drivers/clk/meson/a1-peripherals.c | 2 ++
drivers/clk/meson/a1-peripherals.h | 3 ---
drivers/clk/meson/a1-pll.c | 2 ++
drivers/clk/meson/a1-pll.h | 3 ---
4 files changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/meson/a1-peripherals.c b/drivers/clk/meson/a1-peripherals.c
index 094246cb5f6c..ef0881b8ee07 100644
--- a/drivers/clk/meson/a1-peripherals.c
+++ b/drivers/clk/meson/a1-peripherals.c
@@ -14,6 +14,8 @@
#include "clk-dualdiv.h"
#include "clk-regmap.h"
+#include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
+
static struct clk_regmap xtal_in = {
.data = &(struct clk_regmap_gate_data){
.offset = SYS_OSCIN_CTRL,
diff --git a/drivers/clk/meson/a1-peripherals.h b/drivers/clk/meson/a1-peripherals.h
index 842b52634ed0..26de8530184a 100644
--- a/drivers/clk/meson/a1-peripherals.h
+++ b/drivers/clk/meson/a1-peripherals.h
@@ -43,7 +43,4 @@
#define PSRAM_CLK_CTRL 0xf4
#define DMC_CLK_CTRL 0xf8
-/* include the CLKIDs that have been made part of the DT binding */
-#include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
-
#endif /* __A1_PERIPHERALS_H */
diff --git a/drivers/clk/meson/a1-pll.c b/drivers/clk/meson/a1-pll.c
index 25d102dc8a5d..9a757862abab 100644
--- a/drivers/clk/meson/a1-pll.c
+++ b/drivers/clk/meson/a1-pll.c
@@ -13,6 +13,8 @@
#include "a1-pll.h"
#include "clk-regmap.h"
+#include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
+
static struct clk_regmap fixed_pll_dco = {
.data = &(struct meson_clk_pll_data){
.en = {
diff --git a/drivers/clk/meson/a1-pll.h b/drivers/clk/meson/a1-pll.h
index 0add1c7ea9f5..4be17b2bf383 100644
--- a/drivers/clk/meson/a1-pll.h
+++ b/drivers/clk/meson/a1-pll.h
@@ -25,7 +25,4 @@
#define ANACTRL_HIFIPLL_CTRL4 0xd0
#define ANACTRL_HIFIPLL_STS 0xd4
-/* include the CLKIDs that have been made part of the DT binding */
-#include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
-
#endif /* __A1_PLL_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 17/18] clk: meson: meson8b: move bindings include to main driver
2023-06-07 10:56 [PATCH 00/18] clk: meson: move all private clk IDs to public dt-bindings headers Neil Armstrong
` (14 preceding siblings ...)
2023-06-07 10:56 ` [PATCH 16/18] clk: meson: a1: " Neil Armstrong
@ 2023-06-07 10:56 ` Neil Armstrong
2023-06-07 10:56 ` [PATCH 18/18] clk: meson: axg-audio: " Neil Armstrong
16 siblings, 0 replies; 35+ messages in thread
From: Neil Armstrong @ 2023-06-07 10:56 UTC (permalink / raw)
To: Jerome Brunet, Michael Turquette, Stephen Boyd, Kevin Hilman,
Martin Blumenstingl, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-amlogic, linux-clk, linux-arm-kernel, linux-kernel,
devicetree, Neil Armstrong
Now the clock ids are no more defined in private headers,
cleanup and include the dt-bindings headers from the main
driver file.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
drivers/clk/meson/meson8b.c | 3 +++
drivers/clk/meson/meson8b.h | 7 -------
2 files changed, 3 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index 1e1313991a68..f8fad1118472 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -21,6 +21,9 @@
#include "clk-pll.h"
#include "clk-mpll.h"
+#include <dt-bindings/clock/meson8b-clkc.h>
+#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
+
static DEFINE_SPINLOCK(meson_clk_lock);
struct meson8b_clk_reset {
diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index 2a9c4fe29ca2..a5b6e67eeefb 100644
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -77,11 +77,4 @@
#define HHI_MPLL_CNTL9 0x2A0 /* 0xa8 offset in data sheet */
#define HHI_MPLL_CNTL10 0x2A4 /* 0xa9 offset in data sheet */
-/*
- * include the CLKID and RESETID that have
- * been made part of the stable DT binding
- */
-#include <dt-bindings/clock/meson8b-clkc.h>
-#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
-
#endif /* __MESON8B_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 18/18] clk: meson: axg-audio: move bindings include to main driver
2023-06-07 10:56 [PATCH 00/18] clk: meson: move all private clk IDs to public dt-bindings headers Neil Armstrong
` (15 preceding siblings ...)
2023-06-07 10:56 ` [PATCH 17/18] clk: meson: meson8b: " Neil Armstrong
@ 2023-06-07 10:56 ` Neil Armstrong
16 siblings, 0 replies; 35+ messages in thread
From: Neil Armstrong @ 2023-06-07 10:56 UTC (permalink / raw)
To: Jerome Brunet, Michael Turquette, Stephen Boyd, Kevin Hilman,
Martin Blumenstingl, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-amlogic, linux-clk, linux-arm-kernel, linux-kernel,
devicetree, Neil Armstrong
Now the clock ids are no more defined in private headers,
cleanup and include the dt-bindings headers from the main
driver file.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
drivers/clk/meson/axg-audio.c | 2 ++
drivers/clk/meson/axg-audio.h | 3 ---
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c
index ef4e0552f77c..025cb4efce36 100644
--- a/drivers/clk/meson/axg-audio.c
+++ b/drivers/clk/meson/axg-audio.c
@@ -20,6 +20,8 @@
#include "clk-phase.h"
#include "sclk-div.h"
+#include <dt-bindings/clock/axg-audio-clkc.h>
+
#define AUD_GATE(_name, _reg, _bit, _pname, _iflags) { \
.data = &(struct clk_regmap_gate_data){ \
.offset = (_reg), \
diff --git a/drivers/clk/meson/axg-audio.h b/drivers/clk/meson/axg-audio.h
index faf08748b205..01a3da19933e 100644
--- a/drivers/clk/meson/axg-audio.h
+++ b/drivers/clk/meson/axg-audio.h
@@ -65,7 +65,4 @@
#define AUDIO_CLK81_CTRL 0x030
#define AUDIO_CLK81_EN 0x034
-/* include the CLKIDs which are part of the DT bindings */
-#include <dt-bindings/clock/axg-audio-clkc.h>
-
#endif /*__AXG_AUDIO_CLKC_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 35+ messages in thread
* Re: [PATCH 03/18] clk: meson: migrate a1 clock drivers out of hw_onecell_data to drop NR_CLKS
2023-06-07 10:56 ` [PATCH 03/18] clk: meson: migrate a1 clock drivers " Neil Armstrong
@ 2023-06-08 12:45 ` Jerome Brunet
2023-06-08 12:53 ` Neil Armstrong
0 siblings, 1 reply; 35+ messages in thread
From: Jerome Brunet @ 2023-06-08 12:45 UTC (permalink / raw)
To: Neil Armstrong, Michael Turquette, Stephen Boyd, Kevin Hilman,
Martin Blumenstingl, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-amlogic, linux-clk, linux-arm-kernel, linux-kernel, devicetree
>
> +struct meson_a1_pll_clks {
> + struct clk_hw **hw_clks;
> + unsigned int hw_clk_num;
> +};
> +
> +static struct meson_a1_pll_clks a1_pll_clks = {
> + .hw_clks = a1_pll_hw_clks,
> + .hw_clk_num = ARRAY_SIZE(a1_pll_hw_clks),
> +};
> +
> +static struct clk_hw *meson_a1_pll_hw_get(struct of_phandle_args *clkspec, void *clk_data)
> +{
> + const struct meson_a1_pll_clks *data = clk_data;
> + unsigned int idx = clkspec->args[0];
> +
> + if (idx >= data->hw_clk_num) {
> + pr_err("%s: invalid index %u\n", __func__, idx);
> + return ERR_PTR(-EINVAL);
> + }
> +
> + return data->hw_clks[idx];
> +}
I'd prefer to have a single struct type and and single custom
callback for the different SoC please.
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 03/18] clk: meson: migrate a1 clock drivers out of hw_onecell_data to drop NR_CLKS
2023-06-08 12:45 ` Jerome Brunet
@ 2023-06-08 12:53 ` Neil Armstrong
2023-06-09 11:48 ` Dmitry Rokosov
2023-06-09 14:30 ` Jerome Brunet
0 siblings, 2 replies; 35+ messages in thread
From: Neil Armstrong @ 2023-06-08 12:53 UTC (permalink / raw)
To: Jerome Brunet, Michael Turquette, Stephen Boyd, Kevin Hilman,
Martin Blumenstingl, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-amlogic, linux-clk, linux-arm-kernel, linux-kernel, devicetree
On 08/06/2023 14:45, Jerome Brunet wrote:
>>
>> +struct meson_a1_pll_clks {
>> + struct clk_hw **hw_clks;
>> + unsigned int hw_clk_num;
>> +};
>> +
>> +static struct meson_a1_pll_clks a1_pll_clks = {
>> + .hw_clks = a1_pll_hw_clks,
>> + .hw_clk_num = ARRAY_SIZE(a1_pll_hw_clks),
>> +};
>> +
>> +static struct clk_hw *meson_a1_pll_hw_get(struct of_phandle_args *clkspec, void *clk_data)
>> +{
>> + const struct meson_a1_pll_clks *data = clk_data;
>> + unsigned int idx = clkspec->args[0];
>> +
>> + if (idx >= data->hw_clk_num) {
>> + pr_err("%s: invalid index %u\n", __func__, idx);
>> + return ERR_PTR(-EINVAL);
>> + }
>> +
>> + return data->hw_clks[idx];
>> +}
>
> I'd prefer to have a single struct type and and single custom
> callback for the different SoC please.
Sure, I've written a common code for that, but I have a hard time finding
a proper naming for it... so I choosed meson-clkc since it could have
more common helper code for duplicated code over the clk driver:
===================================><============================================================================
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index 8ce846fdbe43..9070dcfd9e71 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -30,6 +30,9 @@ config COMMON_CLK_MESON_VID_PLL_DIV
tristate
select COMMON_CLK_MESON_REGMAP
+config COMMON_CLK_MESON_CLKC
+ tristate
+
config COMMON_CLK_MESON_AO_CLKC
tristate
select COMMON_CLK_MESON_REGMAP
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index d5288662881d..13c6db466986 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
# Amlogic clock drivers
+obj-$(CONFIG_COMMON_CLK_MESON_CLKC) += meson-clkc.o
obj-$(CONFIG_COMMON_CLK_MESON_AO_CLKC) += meson-aoclk.o
obj-$(CONFIG_COMMON_CLK_MESON_CPU_DYNDIV) += clk-cpu-dyndiv.o
obj-$(CONFIG_COMMON_CLK_MESON_DUALDIV) += clk-dualdiv.o
diff --git a/drivers/clk/meson/meson-clkc.c b/drivers/clk/meson/meson-clkc.c
new file mode 100644
index 000000000000..fa98b9d09011
--- /dev/null
+++ b/drivers/clk/meson/meson-clkc.c
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org>
+ */
+
+#include <linux/of_device.h>
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include "meson-clkc.h"
+
+struct clk_hw *meson_clk_hw_get(struct of_phandle_args *clkspec, void *clk_hw_data)
+{
+ const struct meson_clk_hw_data *data = clk_hw_data;
+ unsigned int idx = clkspec->args[0];
+
+ if (idx >= data->num) {
+ pr_err("%s: invalid index %u\n", __func__, idx);
+ return ERR_PTR(-EINVAL);
+ }
+
+ return data->hws[idx];
+}
+EXPORT_SYMBOL_GPL(meson_clk_hw_get);
+
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/meson/meson-clkc.h b/drivers/clk/meson/meson-clkc.h
new file mode 100644
index 000000000000..e3bad2aa17eb
--- /dev/null
+++ b/drivers/clk/meson/meson-clkc.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org>
+ */
+
+#ifndef __MESON_HW_CLKC_H__
+#define __MESON_HW_CLKC_H__
+
+#include <linux/of_device.h>
+#include <linux/clk-provider.h>
+
+struct meson_clk_hw_data {
+ struct clk_hw **hws;
+ unsigned int num;
+};
+
+struct clk_hw *meson_clk_hw_get(struct of_phandle_args *clkspec, void *clk_hw_data);
+
+#endif
===================================><============================================================================
If it's ok I'll send a v2 using this.
Thanks,
Neil
^ permalink raw reply related [flat|nested] 35+ messages in thread
* Re: [PATCH 03/18] clk: meson: migrate a1 clock drivers out of hw_onecell_data to drop NR_CLKS
2023-06-08 12:53 ` Neil Armstrong
@ 2023-06-09 11:48 ` Dmitry Rokosov
2023-06-09 12:47 ` Neil Armstrong
2023-06-09 14:30 ` Jerome Brunet
1 sibling, 1 reply; 35+ messages in thread
From: Dmitry Rokosov @ 2023-06-09 11:48 UTC (permalink / raw)
To: Neil Armstrong
Cc: Jerome Brunet, Michael Turquette, Stephen Boyd, Kevin Hilman,
Martin Blumenstingl, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-amlogic, linux-clk, linux-arm-kernel,
linux-kernel, devicetree
Hello Neil,
On Thu, Jun 08, 2023 at 02:53:50PM +0200, Neil Armstrong wrote:
> On 08/06/2023 14:45, Jerome Brunet wrote:
> > > +struct meson_a1_pll_clks {
> > > + struct clk_hw **hw_clks;
> > > + unsigned int hw_clk_num;
> > > +};
> > > +
> > > +static struct meson_a1_pll_clks a1_pll_clks = {
> > > + .hw_clks = a1_pll_hw_clks,
> > > + .hw_clk_num = ARRAY_SIZE(a1_pll_hw_clks),
> > > +};
> > > +
> > > +static struct clk_hw *meson_a1_pll_hw_get(struct of_phandle_args *clkspec, void *clk_data)
> > > +{
> > > + const struct meson_a1_pll_clks *data = clk_data;
> > > + unsigned int idx = clkspec->args[0];
> > > +
> > > + if (idx >= data->hw_clk_num) {
> > > + pr_err("%s: invalid index %u\n", __func__, idx);
> > > + return ERR_PTR(-EINVAL);
> > > + }
> > > +
> > > + return data->hw_clks[idx];
> > > +}
> >
> > I'd prefer to have a single struct type and and single custom
> > callback for the different SoC please.
>
> Sure, I've written a common code for that, but I have a hard time finding
> a proper naming for it... so I choosed meson-clkc since it could have
> more common helper code for duplicated code over the clk driver:
>
> ===================================><============================================================================
> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
> index 8ce846fdbe43..9070dcfd9e71 100644
> --- a/drivers/clk/meson/Kconfig
> +++ b/drivers/clk/meson/Kconfig
> @@ -30,6 +30,9 @@ config COMMON_CLK_MESON_VID_PLL_DIV
> tristate
> select COMMON_CLK_MESON_REGMAP
>
> +config COMMON_CLK_MESON_CLKC
> + tristate
> +
> config COMMON_CLK_MESON_AO_CLKC
> tristate
> select COMMON_CLK_MESON_REGMAP
> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
> index d5288662881d..13c6db466986 100644
> --- a/drivers/clk/meson/Makefile
> +++ b/drivers/clk/meson/Makefile
> @@ -1,6 +1,7 @@
> # SPDX-License-Identifier: GPL-2.0-only
> # Amlogic clock drivers
>
> +obj-$(CONFIG_COMMON_CLK_MESON_CLKC) += meson-clkc.o
> obj-$(CONFIG_COMMON_CLK_MESON_AO_CLKC) += meson-aoclk.o
> obj-$(CONFIG_COMMON_CLK_MESON_CPU_DYNDIV) += clk-cpu-dyndiv.o
> obj-$(CONFIG_COMMON_CLK_MESON_DUALDIV) += clk-dualdiv.o
> diff --git a/drivers/clk/meson/meson-clkc.c b/drivers/clk/meson/meson-clkc.c
> new file mode 100644
> index 000000000000..fa98b9d09011
> --- /dev/null
> +++ b/drivers/clk/meson/meson-clkc.c
> @@ -0,0 +1,25 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org>
> + */
> +
> +#include <linux/of_device.h>
> +#include <linux/clk-provider.h>
> +#include <linux/module.h>
> +#include "meson-clkc.h"
> +
> +struct clk_hw *meson_clk_hw_get(struct of_phandle_args *clkspec, void *clk_hw_data)
> +{
> + const struct meson_clk_hw_data *data = clk_hw_data;
> + unsigned int idx = clkspec->args[0];
> +
> + if (idx >= data->num) {
> + pr_err("%s: invalid index %u\n", __func__, idx);
> + return ERR_PTR(-EINVAL);
> + }
> +
> + return data->hws[idx];
> +}
> +EXPORT_SYMBOL_GPL(meson_clk_hw_get);
> +
> +MODULE_LICENSE("GPL v2");
> diff --git a/drivers/clk/meson/meson-clkc.h b/drivers/clk/meson/meson-clkc.h
> new file mode 100644
> index 000000000000..e3bad2aa17eb
> --- /dev/null
> +++ b/drivers/clk/meson/meson-clkc.h
> @@ -0,0 +1,19 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/*
> + * Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org>
> + */
> +
> +#ifndef __MESON_HW_CLKC_H__
> +#define __MESON_HW_CLKC_H__
> +
> +#include <linux/of_device.h>
> +#include <linux/clk-provider.h>
> +
> +struct meson_clk_hw_data {
> + struct clk_hw **hws;
> + unsigned int num;
> +};
> +
> +struct clk_hw *meson_clk_hw_get(struct of_phandle_args *clkspec, void *clk_hw_data);
> +
> +#endif
> ===================================><============================================================================
>
> If it's ok I'll send a v2 using this.
>
> Thanks,
> Neil
In addition, I propose consolidating the probe() routine of the a1
clocks into a common part, which can be utilized for s4 and other
similar clocks. This solution was presented in the early a1 review
stages of this patch set.
https://lore.kernel.org/linux-amlogic/20221201225703.6507-7-ddrokosov@sberdevices.ru/
Maybe, it can be generalized for the all meson clock controller drivers.
--
Thank you,
Dmitry
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 11/18] dt-bindings: clk: amlogic,a1-peripherals-clkc: expose all clock ids
2023-06-07 10:56 ` [PATCH 11/18] dt-bindings: clk: amlogic,a1-peripherals-clkc: " Neil Armstrong
@ 2023-06-09 12:04 ` Dmitry Rokosov
2023-06-10 16:38 ` Krzysztof Kozlowski
1 sibling, 0 replies; 35+ messages in thread
From: Dmitry Rokosov @ 2023-06-09 12:04 UTC (permalink / raw)
To: Neil Armstrong
Cc: Jerome Brunet, Michael Turquette, Stephen Boyd, Kevin Hilman,
Martin Blumenstingl, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-amlogic, linux-clk, linux-arm-kernel,
linux-kernel, kernel, devicetree
Hello Neil,
On Wed, Jun 07, 2023 at 12:56:22PM +0200, Neil Armstrong wrote:
> Due to a policy change in clock ID bindings handling, expose
> all the "private" clock IDs to the public clock dt-bindings
> to move out of the previous maintenance scheme.
>
> This refers to a discussion at [1] & [2] with Krzysztof about
> the issue with the current maintenance.
>
> It was decided to move every A1 peripherals ID to the public clock
> dt-bindings headers to be merged in a single tree so we
> can safely add new clocks without having merge issues.
>
> [1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/
> [2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/
>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
> drivers/clk/meson/a1-peripherals.h | 63 ----------------------
> .../clock/amlogic,a1-peripherals-clkc.h | 53 ++++++++++++++++++
> 2 files changed, 53 insertions(+), 63 deletions(-)
>
> diff --git a/drivers/clk/meson/a1-peripherals.h b/drivers/clk/meson/a1-peripherals.h
> index 4d60456a95a9..842b52634ed0 100644
> --- a/drivers/clk/meson/a1-peripherals.h
> +++ b/drivers/clk/meson/a1-peripherals.h
> @@ -46,67 +46,4 @@
> /* include the CLKIDs that have been made part of the DT binding */
> #include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
>
> -/*
> - * CLKID index values for internal clocks
> - *
> - * These indices are entirely contrived and do not map onto the hardware.
> - * It has now been decided to expose everything by default in the DT header:
> - * include/dt-bindings/clock/a1-peripherals-clkc.h.
> - * Only the clocks ids we don't want to expose, such as the internal muxes and
> - * dividers of composite clocks, will remain defined here.
> - */
> -#define CLKID_XTAL_IN 0
> -#define CLKID_DSPA_SEL 61
> -#define CLKID_DSPB_SEL 62
> -#define CLKID_SARADC_SEL 74
> -#define CLKID_SYS_A_SEL 89
> -#define CLKID_SYS_A_DIV 90
> -#define CLKID_SYS_A 91
> -#define CLKID_SYS_B_SEL 92
> -#define CLKID_SYS_B_DIV 93
> -#define CLKID_SYS_B 94
> -#define CLKID_DSPA_A_DIV 96
> -#define CLKID_DSPA_A 97
> -#define CLKID_DSPA_B_DIV 99
> -#define CLKID_DSPA_B 100
> -#define CLKID_DSPB_A_DIV 102
> -#define CLKID_DSPB_A 103
> -#define CLKID_DSPB_B_DIV 105
> -#define CLKID_DSPB_B 106
> -#define CLKID_RTC_32K_IN 107
> -#define CLKID_RTC_32K_DIV 108
> -#define CLKID_RTC_32K_XTAL 109
> -#define CLKID_RTC_32K_SEL 110
> -#define CLKID_CECB_32K_IN 111
> -#define CLKID_CECB_32K_DIV 112
> -#define CLKID_CECA_32K_IN 115
> -#define CLKID_CECA_32K_DIV 116
> -#define CLKID_DIV2_PRE 119
> -#define CLKID_24M_DIV2 120
> -#define CLKID_GEN_DIV 122
> -#define CLKID_SARADC_DIV 123
> -#define CLKID_PWM_A_DIV 125
> -#define CLKID_PWM_B_DIV 127
> -#define CLKID_PWM_C_DIV 129
> -#define CLKID_PWM_D_DIV 131
> -#define CLKID_PWM_E_DIV 133
> -#define CLKID_PWM_F_DIV 135
> -#define CLKID_SPICC_SEL 136
> -#define CLKID_SPICC_DIV 137
> -#define CLKID_SPICC_SEL2 138
> -#define CLKID_TS_DIV 139
> -#define CLKID_SPIFC_SEL 140
> -#define CLKID_SPIFC_DIV 141
> -#define CLKID_SPIFC_SEL2 142
> -#define CLKID_USB_BUS_SEL 143
> -#define CLKID_USB_BUS_DIV 144
> -#define CLKID_SD_EMMC_SEL 145
> -#define CLKID_SD_EMMC_DIV 146
> -#define CLKID_PSRAM_SEL 148
> -#define CLKID_PSRAM_DIV 149
> -#define CLKID_PSRAM_SEL2 150
> -#define CLKID_DMC_SEL 151
> -#define CLKID_DMC_DIV 152
> -#define CLKID_DMC_SEL2 153
> -
> #endif /* __A1_PERIPHERALS_H */
> diff --git a/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h b/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h
> index ff2730f398a6..06f198ee7623 100644
> --- a/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h
> +++ b/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h
> @@ -10,6 +10,7 @@
> #ifndef __A1_PERIPHERALS_CLKC_H
> #define __A1_PERIPHERALS_CLKC_H
>
> +#define CLKID_XTAL_IN 0
> #define CLKID_FIXPLL_IN 1
> #define CLKID_USB_PHY_IN 2
> #define CLKID_USB_CTRL_IN 3
> @@ -70,6 +71,8 @@
> #define CLKID_CPU_CTRL 58
> #define CLKID_ROM 59
> #define CLKID_PROC_I2C 60
> +#define CLKID_DSPA_SEL 61
> +#define CLKID_DSPB_SEL 62
> #define CLKID_DSPA_EN 63
> #define CLKID_DSPA_EN_NIC 64
> #define CLKID_DSPB_EN 65
> @@ -81,6 +84,7 @@
> #define CLKID_12M 71
> #define CLKID_FCLK_DIV2_DIVN 72
> #define CLKID_GEN 73
> +#define CLKID_SARADC_SEL 74
> #define CLKID_SARADC 75
> #define CLKID_PWM_A 76
> #define CLKID_PWM_B 77
> @@ -95,21 +99,70 @@
> #define CLKID_SD_EMMC 86
> #define CLKID_PSRAM 87
> #define CLKID_DMC 88
> +#define CLKID_SYS_A_SEL 89
> +#define CLKID_SYS_A_DIV 90
> +#define CLKID_SYS_A 91
> +#define CLKID_SYS_B_SEL 92
> +#define CLKID_SYS_B_DIV 93
> +#define CLKID_SYS_B 94
> #define CLKID_DSPA_A_SEL 95
> +#define CLKID_DSPA_A_DIV 96
> +#define CLKID_DSPA_A 97
> #define CLKID_DSPA_B_SEL 98
> +#define CLKID_DSPA_B_DIV 99
> +#define CLKID_DSPA_B 100
> #define CLKID_DSPB_A_SEL 101
> +#define CLKID_DSPB_A_DIV 102
> +#define CLKID_DSPB_A 103
> #define CLKID_DSPB_B_SEL 104
> +#define CLKID_DSPB_B_DIV 105
> +#define CLKID_DSPB_B 106
> +#define CLKID_RTC_32K_IN 107
> +#define CLKID_RTC_32K_DIV 108
> +#define CLKID_RTC_32K_XTAL 109
> +#define CLKID_RTC_32K_SEL 110
> +#define CLKID_CECB_32K_IN 111
> +#define CLKID_CECB_32K_DIV 112
> #define CLKID_CECB_32K_SEL_PRE 113
> #define CLKID_CECB_32K_SEL 114
> +#define CLKID_CECA_32K_IN 115
> +#define CLKID_CECA_32K_DIV 116
> #define CLKID_CECA_32K_SEL_PRE 117
> #define CLKID_CECA_32K_SEL 118
> +#define CLKID_DIV2_PRE 119
> +#define CLKID_24M_DIV2 120
> #define CLKID_GEN_SEL 121
> +#define CLKID_GEN_DIV 122
> +#define CLKID_SARADC_DIV 123
> #define CLKID_PWM_A_SEL 124
> +#define CLKID_PWM_A_DIV 125
> #define CLKID_PWM_B_SEL 126
> +#define CLKID_PWM_B_DIV 127
> #define CLKID_PWM_C_SEL 128
> +#define CLKID_PWM_C_DIV 129
> #define CLKID_PWM_D_SEL 130
> +#define CLKID_PWM_D_DIV 131
> #define CLKID_PWM_E_SEL 132
> +#define CLKID_PWM_E_DIV 133
> #define CLKID_PWM_F_SEL 134
> +#define CLKID_PWM_F_DIV 135
> +#define CLKID_SPICC_SEL 136
> +#define CLKID_SPICC_DIV 137
> +#define CLKID_SPICC_SEL2 138
> +#define CLKID_TS_DIV 139
> +#define CLKID_SPIFC_SEL 140
> +#define CLKID_SPIFC_DIV 141
> +#define CLKID_SPIFC_SEL2 142
> +#define CLKID_USB_BUS_SEL 143
> +#define CLKID_USB_BUS_DIV 144
> +#define CLKID_SD_EMMC_SEL 145
> +#define CLKID_SD_EMMC_DIV 146
> #define CLKID_SD_EMMC_SEL2 147
> +#define CLKID_PSRAM_SEL 148
> +#define CLKID_PSRAM_DIV 149
> +#define CLKID_PSRAM_SEL2 150
> +#define CLKID_DMC_SEL 151
> +#define CLKID_DMC_DIV 152
> +#define CLKID_DMC_SEL2 153
>
> #endif /* __A1_PERIPHERALS_CLKC_H */
>
> --
> 2.34.1
>
Reviewed-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
By the way, I can share another approach for 'private' clock bindings.
Instead of registering 'private' clock objects on the hw_provider side,
they can be completely omitted and registered only as clock objects.
The such approach restricts internal clock usage by public device tree
at all.
I've already introduced this approach in one of the versions for a1
series (the approach was suggested by Krzysztof).
https://lore.kernel.org/all/20230321193014.26349-6-ddrokosov@sberdevices.ru/
---
+/* Array of all clocks provided by this provider */
+static struct clk_hw_onecell_data a1_periphs_public_clks = {
+ .hws = {
+ [CLKID_FIXPLL_IN] = &fixpll_in.hw,
+ [CLKID_USB_PHY_IN] = &usb_phy_in.hw,
+ [CLKID_USB_CTRL_IN] = &usb_ctrl_in.hw,
+ [CLKID_HIFIPLL_IN] = &hifipll_in.hw,
+ [CLKID_SYSPLL_IN] = &syspll_in.hw,
+ [CLKID_DDS_IN] = &dds_in.hw,
+ [CLKID_SYS] = &sys.hw,
+ [CLKID_CLKTREE] = &clktree.hw,
+ [CLKID_RESET_CTRL] = &reset_ctrl.hw,
+ [CLKID_ANALOG_CTRL] = &analog_ctrl.hw,
+ [CLKID_PWR_CTRL] = &pwr_ctrl.hw,
[...]
+/*
+ * These clocks are entirely contrived and do not map onto the hardware.
+ * It has now been decided to expose public clocks in the DT bindings.
+ * Only below clocks we don't want to expose, such as the internal muxes
+ * and dividers of composite clocks, will remain defined here.
+ */
+static struct clk_hw_onecell_data a1_periphs_private_clks = {
+ .hws = {
+ &xtal_in.hw,
+ &dspa_sel.hw,
+ &dspb_sel.hw,
+ &saradc_sel.hw,
+ &sys_a_sel.hw,
+ &sys_a_div.hw,
+ &sys_a.hw,
+ &sys_b_sel.hw,
+ &sys_b_div.hw,
[...]
---
--
Thank you,
Dmitry
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 12/18] dt-bindings: clk: amlogic,a1-pll-clkc: expose all clock ids
2023-06-07 10:56 ` [PATCH 12/18] dt-bindings: clk: amlogic,a1-pll-clkc: " Neil Armstrong
@ 2023-06-09 12:10 ` Dmitry Rokosov
2023-06-10 16:39 ` Krzysztof Kozlowski
1 sibling, 0 replies; 35+ messages in thread
From: Dmitry Rokosov @ 2023-06-09 12:10 UTC (permalink / raw)
To: Neil Armstrong
Cc: Jerome Brunet, Michael Turquette, Stephen Boyd, Kevin Hilman,
Martin Blumenstingl, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-amlogic, linux-clk, linux-arm-kernel,
linux-kernel, devicetree
On Wed, Jun 07, 2023 at 12:56:23PM +0200, Neil Armstrong wrote:
> Due to a policy change in clock ID bindings handling, expose
> all the "private" clock IDs to the public clock dt-bindings
> to move out of the previous maintenance scheme.
>
> This refers to a discussion at [1] & [2] with Krzysztof about
> the issue with the current maintenance.
>
> It was decided to move every A1 pll ID to the public clock
> dt-bindings headers to be merged in a single tree so we
> can safely add new clocks without having merge issues.
>
> [1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/
> [2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/
>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
> drivers/clk/meson/a1-pll.h | 15 ---------------
> include/dt-bindings/clock/amlogic,a1-pll-clkc.h | 5 +++++
> 2 files changed, 5 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/clk/meson/a1-pll.h b/drivers/clk/meson/a1-pll.h
> index 82570759e6a2..0add1c7ea9f5 100644
> --- a/drivers/clk/meson/a1-pll.h
> +++ b/drivers/clk/meson/a1-pll.h
> @@ -28,19 +28,4 @@
> /* include the CLKIDs that have been made part of the DT binding */
> #include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
>
> -/*
> - * CLKID index values for internal clocks
> - *
> - * These indices are entirely contrived and do not map onto the hardware.
> - * It has now been decided to expose everything by default in the DT header:
> - * include/dt-bindings/clock/a1-pll-clkc.h. Only the clocks ids we don't want
> - * to expose, such as the internal muxes and dividers of composite clocks,
> - * will remain defined here.
> - */
> -#define CLKID_FIXED_PLL_DCO 0
> -#define CLKID_FCLK_DIV2_DIV 2
> -#define CLKID_FCLK_DIV3_DIV 3
> -#define CLKID_FCLK_DIV5_DIV 4
> -#define CLKID_FCLK_DIV7_DIV 5
> -
> #endif /* __A1_PLL_H */
> diff --git a/include/dt-bindings/clock/amlogic,a1-pll-clkc.h b/include/dt-bindings/clock/amlogic,a1-pll-clkc.h
> index 01fb8164ac29..2b660c0f2c9f 100644
> --- a/include/dt-bindings/clock/amlogic,a1-pll-clkc.h
> +++ b/include/dt-bindings/clock/amlogic,a1-pll-clkc.h
> @@ -10,7 +10,12 @@
> #ifndef __A1_PLL_CLKC_H
> #define __A1_PLL_CLKC_H
>
> +#define CLKID_FIXED_PLL_DCO 0
> #define CLKID_FIXED_PLL 1
> +#define CLKID_FCLK_DIV2_DIV 2
> +#define CLKID_FCLK_DIV3_DIV 3
> +#define CLKID_FCLK_DIV5_DIV 4
> +#define CLKID_FCLK_DIV7_DIV 5
> #define CLKID_FCLK_DIV2 6
> #define CLKID_FCLK_DIV3 7
> #define CLKID_FCLK_DIV5 8
>
> --
> 2.34.1
>
Reviewed-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
--
Thank you,
Dmitry
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 03/18] clk: meson: migrate a1 clock drivers out of hw_onecell_data to drop NR_CLKS
2023-06-09 11:48 ` Dmitry Rokosov
@ 2023-06-09 12:47 ` Neil Armstrong
2023-06-09 12:57 ` Dmitry Rokosov
0 siblings, 1 reply; 35+ messages in thread
From: Neil Armstrong @ 2023-06-09 12:47 UTC (permalink / raw)
To: Dmitry Rokosov
Cc: Jerome Brunet, Michael Turquette, Stephen Boyd, Kevin Hilman,
Martin Blumenstingl, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-amlogic, linux-clk, linux-arm-kernel,
linux-kernel, devicetree
Hi,
On 09/06/2023 13:48, Dmitry Rokosov wrote:
> Hello Neil,
>
> On Thu, Jun 08, 2023 at 02:53:50PM +0200, Neil Armstrong wrote:
>> On 08/06/2023 14:45, Jerome Brunet wrote:
>>>> +struct meson_a1_pll_clks {
>>>> + struct clk_hw **hw_clks;
>>>> + unsigned int hw_clk_num;
>>>> +};
>>>> +
>>>> +static struct meson_a1_pll_clks a1_pll_clks = {
>>>> + .hw_clks = a1_pll_hw_clks,
>>>> + .hw_clk_num = ARRAY_SIZE(a1_pll_hw_clks),
>>>> +};
>>>> +
>>>> +static struct clk_hw *meson_a1_pll_hw_get(struct of_phandle_args *clkspec, void *clk_data)
>>>> +{
>>>> + const struct meson_a1_pll_clks *data = clk_data;
>>>> + unsigned int idx = clkspec->args[0];
>>>> +
>>>> + if (idx >= data->hw_clk_num) {
>>>> + pr_err("%s: invalid index %u\n", __func__, idx);
>>>> + return ERR_PTR(-EINVAL);
>>>> + }
>>>> +
>>>> + return data->hw_clks[idx];
>>>> +}
>>>
>>> I'd prefer to have a single struct type and and single custom
>>> callback for the different SoC please.
>>
>> Sure, I've written a common code for that, but I have a hard time finding
>> a proper naming for it... so I choosed meson-clkc since it could have
>> more common helper code for duplicated code over the clk driver:
>>
>> ===================================><============================================================================
>> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
>> index 8ce846fdbe43..9070dcfd9e71 100644
>> --- a/drivers/clk/meson/Kconfig
>> +++ b/drivers/clk/meson/Kconfig
>> @@ -30,6 +30,9 @@ config COMMON_CLK_MESON_VID_PLL_DIV
>> tristate
>> select COMMON_CLK_MESON_REGMAP
>>
>> +config COMMON_CLK_MESON_CLKC
>> + tristate
>> +
>> config COMMON_CLK_MESON_AO_CLKC
>> tristate
>> select COMMON_CLK_MESON_REGMAP
>> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
>> index d5288662881d..13c6db466986 100644
>> --- a/drivers/clk/meson/Makefile
>> +++ b/drivers/clk/meson/Makefile
>> @@ -1,6 +1,7 @@
>> # SPDX-License-Identifier: GPL-2.0-only
>> # Amlogic clock drivers
>>
>> +obj-$(CONFIG_COMMON_CLK_MESON_CLKC) += meson-clkc.o
>> obj-$(CONFIG_COMMON_CLK_MESON_AO_CLKC) += meson-aoclk.o
>> obj-$(CONFIG_COMMON_CLK_MESON_CPU_DYNDIV) += clk-cpu-dyndiv.o
>> obj-$(CONFIG_COMMON_CLK_MESON_DUALDIV) += clk-dualdiv.o
>> diff --git a/drivers/clk/meson/meson-clkc.c b/drivers/clk/meson/meson-clkc.c
>> new file mode 100644
>> index 000000000000..fa98b9d09011
>> --- /dev/null
>> +++ b/drivers/clk/meson/meson-clkc.c
>> @@ -0,0 +1,25 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org>
>> + */
>> +
>> +#include <linux/of_device.h>
>> +#include <linux/clk-provider.h>
>> +#include <linux/module.h>
>> +#include "meson-clkc.h"
>> +
>> +struct clk_hw *meson_clk_hw_get(struct of_phandle_args *clkspec, void *clk_hw_data)
>> +{
>> + const struct meson_clk_hw_data *data = clk_hw_data;
>> + unsigned int idx = clkspec->args[0];
>> +
>> + if (idx >= data->num) {
>> + pr_err("%s: invalid index %u\n", __func__, idx);
>> + return ERR_PTR(-EINVAL);
>> + }
>> +
>> + return data->hws[idx];
>> +}
>> +EXPORT_SYMBOL_GPL(meson_clk_hw_get);
>> +
>> +MODULE_LICENSE("GPL v2");
>> diff --git a/drivers/clk/meson/meson-clkc.h b/drivers/clk/meson/meson-clkc.h
>> new file mode 100644
>> index 000000000000..e3bad2aa17eb
>> --- /dev/null
>> +++ b/drivers/clk/meson/meson-clkc.h
>> @@ -0,0 +1,19 @@
>> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
>> +/*
>> + * Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org>
>> + */
>> +
>> +#ifndef __MESON_HW_CLKC_H__
>> +#define __MESON_HW_CLKC_H__
>> +
>> +#include <linux/of_device.h>
>> +#include <linux/clk-provider.h>
>> +
>> +struct meson_clk_hw_data {
>> + struct clk_hw **hws;
>> + unsigned int num;
>> +};
>> +
>> +struct clk_hw *meson_clk_hw_get(struct of_phandle_args *clkspec, void *clk_hw_data);
>> +
>> +#endif
>> ===================================><============================================================================
>>
>> If it's ok I'll send a v2 using this.
>>
>> Thanks,
>> Neil
>
> In addition, I propose consolidating the probe() routine of the a1
> clocks into a common part, which can be utilized for s4 and other
> similar clocks. This solution was presented in the early a1 review
> stages of this patch set.
>
> https://lore.kernel.org/linux-amlogic/20221201225703.6507-7-ddrokosov@sberdevices.ru/
>
> Maybe, it can be generalized for the all meson clock controller drivers.
>
Sure, the goal of that is to get rid of NR_CLKS & private IDS only,
then yes afterwards any common clkc function will be welcome !
Neil
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 03/18] clk: meson: migrate a1 clock drivers out of hw_onecell_data to drop NR_CLKS
2023-06-09 12:47 ` Neil Armstrong
@ 2023-06-09 12:57 ` Dmitry Rokosov
0 siblings, 0 replies; 35+ messages in thread
From: Dmitry Rokosov @ 2023-06-09 12:57 UTC (permalink / raw)
To: Neil Armstrong
Cc: Jerome Brunet, Michael Turquette, Stephen Boyd, Kevin Hilman,
Martin Blumenstingl, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-amlogic, linux-clk, linux-arm-kernel,
linux-kernel, devicetree
On Fri, Jun 09, 2023 at 02:47:04PM +0200, Neil Armstrong wrote:
> Hi,
>
> On 09/06/2023 13:48, Dmitry Rokosov wrote:
> > Hello Neil,
> >
> > On Thu, Jun 08, 2023 at 02:53:50PM +0200, Neil Armstrong wrote:
> > > On 08/06/2023 14:45, Jerome Brunet wrote:
> > > > > +struct meson_a1_pll_clks {
> > > > > + struct clk_hw **hw_clks;
> > > > > + unsigned int hw_clk_num;
> > > > > +};
> > > > > +
> > > > > +static struct meson_a1_pll_clks a1_pll_clks = {
> > > > > + .hw_clks = a1_pll_hw_clks,
> > > > > + .hw_clk_num = ARRAY_SIZE(a1_pll_hw_clks),
> > > > > +};
> > > > > +
> > > > > +static struct clk_hw *meson_a1_pll_hw_get(struct of_phandle_args *clkspec, void *clk_data)
> > > > > +{
> > > > > + const struct meson_a1_pll_clks *data = clk_data;
> > > > > + unsigned int idx = clkspec->args[0];
> > > > > +
> > > > > + if (idx >= data->hw_clk_num) {
> > > > > + pr_err("%s: invalid index %u\n", __func__, idx);
> > > > > + return ERR_PTR(-EINVAL);
> > > > > + }
> > > > > +
> > > > > + return data->hw_clks[idx];
> > > > > +}
> > > >
> > > > I'd prefer to have a single struct type and and single custom
> > > > callback for the different SoC please.
> > >
> > > Sure, I've written a common code for that, but I have a hard time finding
> > > a proper naming for it... so I choosed meson-clkc since it could have
> > > more common helper code for duplicated code over the clk driver:
> > >
> > > ===================================><============================================================================
> > > diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
> > > index 8ce846fdbe43..9070dcfd9e71 100644
> > > --- a/drivers/clk/meson/Kconfig
> > > +++ b/drivers/clk/meson/Kconfig
> > > @@ -30,6 +30,9 @@ config COMMON_CLK_MESON_VID_PLL_DIV
> > > tristate
> > > select COMMON_CLK_MESON_REGMAP
> > >
> > > +config COMMON_CLK_MESON_CLKC
> > > + tristate
> > > +
> > > config COMMON_CLK_MESON_AO_CLKC
> > > tristate
> > > select COMMON_CLK_MESON_REGMAP
> > > diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
> > > index d5288662881d..13c6db466986 100644
> > > --- a/drivers/clk/meson/Makefile
> > > +++ b/drivers/clk/meson/Makefile
> > > @@ -1,6 +1,7 @@
> > > # SPDX-License-Identifier: GPL-2.0-only
> > > # Amlogic clock drivers
> > >
> > > +obj-$(CONFIG_COMMON_CLK_MESON_CLKC) += meson-clkc.o
> > > obj-$(CONFIG_COMMON_CLK_MESON_AO_CLKC) += meson-aoclk.o
> > > obj-$(CONFIG_COMMON_CLK_MESON_CPU_DYNDIV) += clk-cpu-dyndiv.o
> > > obj-$(CONFIG_COMMON_CLK_MESON_DUALDIV) += clk-dualdiv.o
> > > diff --git a/drivers/clk/meson/meson-clkc.c b/drivers/clk/meson/meson-clkc.c
> > > new file mode 100644
> > > index 000000000000..fa98b9d09011
> > > --- /dev/null
> > > +++ b/drivers/clk/meson/meson-clkc.c
> > > @@ -0,0 +1,25 @@
> > > +// SPDX-License-Identifier: GPL-2.0+
> > > +/*
> > > + * Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org>
> > > + */
> > > +
> > > +#include <linux/of_device.h>
> > > +#include <linux/clk-provider.h>
> > > +#include <linux/module.h>
> > > +#include "meson-clkc.h"
> > > +
> > > +struct clk_hw *meson_clk_hw_get(struct of_phandle_args *clkspec, void *clk_hw_data)
> > > +{
> > > + const struct meson_clk_hw_data *data = clk_hw_data;
> > > + unsigned int idx = clkspec->args[0];
> > > +
> > > + if (idx >= data->num) {
> > > + pr_err("%s: invalid index %u\n", __func__, idx);
> > > + return ERR_PTR(-EINVAL);
> > > + }
> > > +
> > > + return data->hws[idx];
> > > +}
> > > +EXPORT_SYMBOL_GPL(meson_clk_hw_get);
> > > +
> > > +MODULE_LICENSE("GPL v2");
> > > diff --git a/drivers/clk/meson/meson-clkc.h b/drivers/clk/meson/meson-clkc.h
> > > new file mode 100644
> > > index 000000000000..e3bad2aa17eb
> > > --- /dev/null
> > > +++ b/drivers/clk/meson/meson-clkc.h
> > > @@ -0,0 +1,19 @@
> > > +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> > > +/*
> > > + * Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org>
> > > + */
> > > +
> > > +#ifndef __MESON_HW_CLKC_H__
> > > +#define __MESON_HW_CLKC_H__
> > > +
> > > +#include <linux/of_device.h>
> > > +#include <linux/clk-provider.h>
> > > +
> > > +struct meson_clk_hw_data {
> > > + struct clk_hw **hws;
> > > + unsigned int num;
> > > +};
> > > +
> > > +struct clk_hw *meson_clk_hw_get(struct of_phandle_args *clkspec, void *clk_hw_data);
> > > +
> > > +#endif
> > > ===================================><============================================================================
> > >
> > > If it's ok I'll send a v2 using this.
> > >
> > > Thanks,
> > > Neil
> >
> > In addition, I propose consolidating the probe() routine of the a1
> > clocks into a common part, which can be utilized for s4 and other
> > similar clocks. This solution was presented in the early a1 review
> > stages of this patch set.
> >
> > https://lore.kernel.org/linux-amlogic/20221201225703.6507-7-ddrokosov@sberdevices.ru/
> >
> > Maybe, it can be generalized for the all meson clock controller drivers.
> >
>
> Sure, the goal of that is to get rid of NR_CLKS & private IDS only,
> then yes afterwards any common clkc function will be welcome !
>
> Neil
>
Understood, I fully endorse and support this approach!
--
Thank you,
Dmitry
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 03/18] clk: meson: migrate a1 clock drivers out of hw_onecell_data to drop NR_CLKS
2023-06-08 12:53 ` Neil Armstrong
2023-06-09 11:48 ` Dmitry Rokosov
@ 2023-06-09 14:30 ` Jerome Brunet
2023-06-09 15:32 ` Neil Armstrong
1 sibling, 1 reply; 35+ messages in thread
From: Jerome Brunet @ 2023-06-09 14:30 UTC (permalink / raw)
To: Neil Armstrong, Michael Turquette, Stephen Boyd, Kevin Hilman,
Martin Blumenstingl, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-amlogic, linux-clk, linux-arm-kernel, linux-kernel, devicetree
On Thu 08 Jun 2023 at 14:53, Neil Armstrong <neil.armstrong@linaro.org> wrote:
> On 08/06/2023 14:45, Jerome Brunet wrote:
>>> +struct meson_a1_pll_clks {
>>> + struct clk_hw **hw_clks;
>>> + unsigned int hw_clk_num;
>>> +};
>>> +
>>> +static struct meson_a1_pll_clks a1_pll_clks = {
>>> + .hw_clks = a1_pll_hw_clks,
>>> + .hw_clk_num = ARRAY_SIZE(a1_pll_hw_clks),
>>> +};
>>> +
>>> +static struct clk_hw *meson_a1_pll_hw_get(struct of_phandle_args *clkspec, void *clk_data)
>>> +{
>>> + const struct meson_a1_pll_clks *data = clk_data;
>>> + unsigned int idx = clkspec->args[0];
>>> +
>>> + if (idx >= data->hw_clk_num) {
>>> + pr_err("%s: invalid index %u\n", __func__, idx);
>>> + return ERR_PTR(-EINVAL);
>>> + }
>>> +
>>> + return data->hw_clks[idx];
>>> +}
>> I'd prefer to have a single struct type and and single custom
>> callback for the different SoC please.
>
> Sure, I've written a common code for that, but I have a hard time finding
> a proper naming for it... so I choosed meson-clkc since it could have
> more common helper code for duplicated code over the clk driver:
Agreed. meson-clkc-utils maybe ?
>
> ===================================><============================================================================
> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
> index 8ce846fdbe43..9070dcfd9e71 100644
> --- a/drivers/clk/meson/Kconfig
> +++ b/drivers/clk/meson/Kconfig
> @@ -30,6 +30,9 @@ config COMMON_CLK_MESON_VID_PLL_DIV
> tristate
> select COMMON_CLK_MESON_REGMAP
>
> +config COMMON_CLK_MESON_CLKC
> + tristate
> +
> config COMMON_CLK_MESON_AO_CLKC
> tristate
> select COMMON_CLK_MESON_REGMAP
> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
> index d5288662881d..13c6db466986 100644
> --- a/drivers/clk/meson/Makefile
> +++ b/drivers/clk/meson/Makefile
> @@ -1,6 +1,7 @@
> # SPDX-License-Identifier: GPL-2.0-only
> # Amlogic clock drivers
>
> +obj-$(CONFIG_COMMON_CLK_MESON_CLKC) += meson-clkc.o
> obj-$(CONFIG_COMMON_CLK_MESON_AO_CLKC) += meson-aoclk.o
> obj-$(CONFIG_COMMON_CLK_MESON_CPU_DYNDIV) += clk-cpu-dyndiv.o
> obj-$(CONFIG_COMMON_CLK_MESON_DUALDIV) += clk-dualdiv.o
> diff --git a/drivers/clk/meson/meson-clkc.c b/drivers/clk/meson/meson-clkc.c
> new file mode 100644
> index 000000000000..fa98b9d09011
> --- /dev/null
> +++ b/drivers/clk/meson/meson-clkc.c
> @@ -0,0 +1,25 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org>
> + */
> +
> +#include <linux/of_device.h>
> +#include <linux/clk-provider.h>
> +#include <linux/module.h>
> +#include "meson-clkc.h"
> +
> +struct clk_hw *meson_clk_hw_get(struct of_phandle_args *clkspec, void *clk_hw_data)
> +{
> + const struct meson_clk_hw_data *data = clk_hw_data;
> + unsigned int idx = clkspec->args[0];
> +
> + if (idx >= data->num) {
> + pr_err("%s: invalid index %u\n", __func__, idx);
> + return ERR_PTR(-EINVAL);
> + }
> +
> + return data->hws[idx];
> +}
> +EXPORT_SYMBOL_GPL(meson_clk_hw_get);
> +
> +MODULE_LICENSE("GPL v2");
> diff --git a/drivers/clk/meson/meson-clkc.h b/drivers/clk/meson/meson-clkc.h
> new file mode 100644
> index 000000000000..e3bad2aa17eb
> --- /dev/null
> +++ b/drivers/clk/meson/meson-clkc.h
> @@ -0,0 +1,19 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/*
> + * Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org>
> + */
> +
> +#ifndef __MESON_HW_CLKC_H__
> +#define __MESON_HW_CLKC_H__
> +
> +#include <linux/of_device.h>
> +#include <linux/clk-provider.h>
> +
> +struct meson_clk_hw_data {
> + struct clk_hw **hws;
> + unsigned int num;
> +};
> +
> +struct clk_hw *meson_clk_hw_get(struct of_phandle_args *clkspec, void *clk_hw_data);
> +
> +#endif
> ===================================><============================================================================
>
> If it's ok I'll send a v2 using this.
>
> Thanks,
> Neil
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 03/18] clk: meson: migrate a1 clock drivers out of hw_onecell_data to drop NR_CLKS
2023-06-09 14:30 ` Jerome Brunet
@ 2023-06-09 15:32 ` Neil Armstrong
0 siblings, 0 replies; 35+ messages in thread
From: Neil Armstrong @ 2023-06-09 15:32 UTC (permalink / raw)
To: Jerome Brunet, Michael Turquette, Stephen Boyd, Kevin Hilman,
Martin Blumenstingl, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-amlogic, linux-clk, linux-arm-kernel, linux-kernel, devicetree
On 09/06/2023 16:30, Jerome Brunet wrote:
>
> On Thu 08 Jun 2023 at 14:53, Neil Armstrong <neil.armstrong@linaro.org> wrote:
>
>> On 08/06/2023 14:45, Jerome Brunet wrote:
>>>> +struct meson_a1_pll_clks {
>>>> + struct clk_hw **hw_clks;
>>>> + unsigned int hw_clk_num;
>>>> +};
>>>> +
>>>> +static struct meson_a1_pll_clks a1_pll_clks = {
>>>> + .hw_clks = a1_pll_hw_clks,
>>>> + .hw_clk_num = ARRAY_SIZE(a1_pll_hw_clks),
>>>> +};
>>>> +
>>>> +static struct clk_hw *meson_a1_pll_hw_get(struct of_phandle_args *clkspec, void *clk_data)
>>>> +{
>>>> + const struct meson_a1_pll_clks *data = clk_data;
>>>> + unsigned int idx = clkspec->args[0];
>>>> +
>>>> + if (idx >= data->hw_clk_num) {
>>>> + pr_err("%s: invalid index %u\n", __func__, idx);
>>>> + return ERR_PTR(-EINVAL);
>>>> + }
>>>> +
>>>> + return data->hw_clks[idx];
>>>> +}
>>> I'd prefer to have a single struct type and and single custom
>>> callback for the different SoC please.
>>
>> Sure, I've written a common code for that, but I have a hard time finding
>> a proper naming for it... so I choosed meson-clkc since it could have
>> more common helper code for duplicated code over the clk driver:
>
> Agreed. meson-clkc-utils maybe ?
Ack seems better
Thanks
Neil
>
>>
>> ===================================><============================================================================
>> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
>> index 8ce846fdbe43..9070dcfd9e71 100644
>> --- a/drivers/clk/meson/Kconfig
>> +++ b/drivers/clk/meson/Kconfig
>> @@ -30,6 +30,9 @@ config COMMON_CLK_MESON_VID_PLL_DIV
>> tristate
>> select COMMON_CLK_MESON_REGMAP
>>
>> +config COMMON_CLK_MESON_CLKC
>> + tristate
>> +
>> config COMMON_CLK_MESON_AO_CLKC
>> tristate
>> select COMMON_CLK_MESON_REGMAP
>> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
>> index d5288662881d..13c6db466986 100644
>> --- a/drivers/clk/meson/Makefile
>> +++ b/drivers/clk/meson/Makefile
>> @@ -1,6 +1,7 @@
>> # SPDX-License-Identifier: GPL-2.0-only
>> # Amlogic clock drivers
>>
>> +obj-$(CONFIG_COMMON_CLK_MESON_CLKC) += meson-clkc.o
>> obj-$(CONFIG_COMMON_CLK_MESON_AO_CLKC) += meson-aoclk.o
>> obj-$(CONFIG_COMMON_CLK_MESON_CPU_DYNDIV) += clk-cpu-dyndiv.o
>> obj-$(CONFIG_COMMON_CLK_MESON_DUALDIV) += clk-dualdiv.o
>> diff --git a/drivers/clk/meson/meson-clkc.c b/drivers/clk/meson/meson-clkc.c
>> new file mode 100644
>> index 000000000000..fa98b9d09011
>> --- /dev/null
>> +++ b/drivers/clk/meson/meson-clkc.c
>> @@ -0,0 +1,25 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org>
>> + */
>> +
>> +#include <linux/of_device.h>
>> +#include <linux/clk-provider.h>
>> +#include <linux/module.h>
>> +#include "meson-clkc.h"
>> +
>> +struct clk_hw *meson_clk_hw_get(struct of_phandle_args *clkspec, void *clk_hw_data)
>> +{
>> + const struct meson_clk_hw_data *data = clk_hw_data;
>> + unsigned int idx = clkspec->args[0];
>> +
>> + if (idx >= data->num) {
>> + pr_err("%s: invalid index %u\n", __func__, idx);
>> + return ERR_PTR(-EINVAL);
>> + }
>> +
>> + return data->hws[idx];
>> +}
>> +EXPORT_SYMBOL_GPL(meson_clk_hw_get);
>> +
>> +MODULE_LICENSE("GPL v2");
>> diff --git a/drivers/clk/meson/meson-clkc.h b/drivers/clk/meson/meson-clkc.h
>> new file mode 100644
>> index 000000000000..e3bad2aa17eb
>> --- /dev/null
>> +++ b/drivers/clk/meson/meson-clkc.h
>> @@ -0,0 +1,19 @@
>> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
>> +/*
>> + * Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org>
>> + */
>> +
>> +#ifndef __MESON_HW_CLKC_H__
>> +#define __MESON_HW_CLKC_H__
>> +
>> +#include <linux/of_device.h>
>> +#include <linux/clk-provider.h>
>> +
>> +struct meson_clk_hw_data {
>> + struct clk_hw **hws;
>> + unsigned int num;
>> +};
>> +
>> +struct clk_hw *meson_clk_hw_get(struct of_phandle_args *clkspec, void *clk_hw_data);
>> +
>> +#endif
>> ===================================><============================================================================
>>
>> If it's ok I'll send a v2 using this.
>>
>> Thanks,
>> Neil
>
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 06/18] dt-bindings: clk: gxbb-clkc: expose all clock ids
2023-06-07 10:56 ` [PATCH 06/18] dt-bindings: clk: gxbb-clkc: expose all clock ids Neil Armstrong
@ 2023-06-10 16:38 ` Krzysztof Kozlowski
0 siblings, 0 replies; 35+ messages in thread
From: Krzysztof Kozlowski @ 2023-06-10 16:38 UTC (permalink / raw)
To: Neil Armstrong, Jerome Brunet, Michael Turquette, Stephen Boyd,
Kevin Hilman, Martin Blumenstingl, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-amlogic, linux-clk, linux-arm-kernel, linux-kernel, devicetree
On 07/06/2023 12:56, Neil Armstrong wrote:
> Due to a policy change in clock ID bindings handling, expose
> all the "private" clock IDs to the public clock dt-bindings
> to move out of the previous maintenance scheme.
>
> This refers to a discussion at [1] & [2] with Krzysztof about
> the issue with the current maintenance.
>
> It was decided to move every gxbb-clkc ID to the public clock
> dt-bindings headers to be merged in a single tree so we
> can safely add new clocks without having merge issues.
>
> [1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/
> [2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/
>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 07/18] dt-bindings: clk: axg-clkc: expose all clock ids
2023-06-07 10:56 ` [PATCH 07/18] dt-bindings: clk: axg-clkc: " Neil Armstrong
@ 2023-06-10 16:38 ` Krzysztof Kozlowski
0 siblings, 0 replies; 35+ messages in thread
From: Krzysztof Kozlowski @ 2023-06-10 16:38 UTC (permalink / raw)
To: Neil Armstrong, Jerome Brunet, Michael Turquette, Stephen Boyd,
Kevin Hilman, Martin Blumenstingl, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-amlogic, linux-clk, linux-arm-kernel, linux-kernel, devicetree
On 07/06/2023 12:56, Neil Armstrong wrote:
> Due to a policy change in clock ID bindings handling, expose
> all the "private" clock IDs to the public clock dt-bindings
> to move out of the previous maintenance scheme.
>
> This refers to a discussion at [1] & [2] with Krzysztof about
> the issue with the current maintenance.
>
> It was decided to move every axg-clkc ID to the public clock
> dt-bindings headers to be merged in a single tree so we
> can safely add new clocks without having merge issues.
>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 08/18] dt-bindings: clk: g12a-clks: expose all clock ids
2023-06-07 10:56 ` [PATCH 08/18] dt-bindings: clk: g12a-clks: " Neil Armstrong
@ 2023-06-10 16:38 ` Krzysztof Kozlowski
0 siblings, 0 replies; 35+ messages in thread
From: Krzysztof Kozlowski @ 2023-06-10 16:38 UTC (permalink / raw)
To: Neil Armstrong, Jerome Brunet, Michael Turquette, Stephen Boyd,
Kevin Hilman, Martin Blumenstingl, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-amlogic, linux-clk, linux-arm-kernel, linux-kernel, devicetree
On 07/06/2023 12:56, Neil Armstrong wrote:
> Due to a policy change in clock ID bindings handling, expose
> all the "private" clock IDs to the public clock dt-bindings
> to move out of the previous maintenance scheme.
>
> This refers to a discussion at [1] & [2] with Krzysztof about
> the issue with the current maintenance.
>
> It was decided to move every g12a-clkc ID to the public clock
> dt-bindings headers to be merged in a single tree so we
> can safely add new clocks without having merge issues.
>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 09/18] dt-bindings: clk: g12a-aoclkc: expose all clock ids
2023-06-07 10:56 ` [PATCH 09/18] dt-bindings: clk: g12a-aoclkc: " Neil Armstrong
@ 2023-06-10 16:38 ` Krzysztof Kozlowski
0 siblings, 0 replies; 35+ messages in thread
From: Krzysztof Kozlowski @ 2023-06-10 16:38 UTC (permalink / raw)
To: Neil Armstrong, Jerome Brunet, Michael Turquette, Stephen Boyd,
Kevin Hilman, Martin Blumenstingl, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-amlogic, linux-clk, linux-arm-kernel, linux-kernel, devicetree
On 07/06/2023 12:56, Neil Armstrong wrote:
> Due to a policy change in clock ID bindings handling, expose
> all the "private" clock IDs to the public clock dt-bindings
> to move out of the previous maintenance scheme.
>
> This refers to a discussion at [1] & [2] with Krzysztof about
> the issue with the current maintenance.
>
> It was decided to move every g12a-aoclkc ID to the public clock
> dt-bindings headers to be merged in a single tree so we
> can safely add new clocks without having merge issues.
>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 10/18] dt-bindings: clk: meson8b-clkc: expose all clock ids
2023-06-07 10:56 ` [PATCH 10/18] dt-bindings: clk: meson8b-clkc: " Neil Armstrong
@ 2023-06-10 16:38 ` Krzysztof Kozlowski
0 siblings, 0 replies; 35+ messages in thread
From: Krzysztof Kozlowski @ 2023-06-10 16:38 UTC (permalink / raw)
To: Neil Armstrong, Jerome Brunet, Michael Turquette, Stephen Boyd,
Kevin Hilman, Martin Blumenstingl, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-amlogic, linux-clk, linux-arm-kernel, linux-kernel, devicetree
On 07/06/2023 12:56, Neil Armstrong wrote:
> Due to a policy change in clock ID bindings handling, expose
> all the "private" clock IDs to the public clock dt-bindings
> to move out of the previous maintenance scheme.
>
> This refers to a discussion at [1] & [2] with Krzysztof about
> the issue with the current maintenance.
>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 11/18] dt-bindings: clk: amlogic,a1-peripherals-clkc: expose all clock ids
2023-06-07 10:56 ` [PATCH 11/18] dt-bindings: clk: amlogic,a1-peripherals-clkc: " Neil Armstrong
2023-06-09 12:04 ` Dmitry Rokosov
@ 2023-06-10 16:38 ` Krzysztof Kozlowski
1 sibling, 0 replies; 35+ messages in thread
From: Krzysztof Kozlowski @ 2023-06-10 16:38 UTC (permalink / raw)
To: Neil Armstrong, Jerome Brunet, Michael Turquette, Stephen Boyd,
Kevin Hilman, Martin Blumenstingl, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-amlogic, linux-clk, linux-arm-kernel, linux-kernel, devicetree
On 07/06/2023 12:56, Neil Armstrong wrote:
> Due to a policy change in clock ID bindings handling, expose
> all the "private" clock IDs to the public clock dt-bindings
> to move out of the previous maintenance scheme.
>
> This refers to a discussion at [1] & [2] with Krzysztof about
> the issue with the current maintenance.
>
> It was decided to move every A1 peripherals ID to the public clock
> dt-bindings headers to be merged in a single tree so we
> can safely add new clocks without having merge issues.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 12/18] dt-bindings: clk: amlogic,a1-pll-clkc: expose all clock ids
2023-06-07 10:56 ` [PATCH 12/18] dt-bindings: clk: amlogic,a1-pll-clkc: " Neil Armstrong
2023-06-09 12:10 ` Dmitry Rokosov
@ 2023-06-10 16:39 ` Krzysztof Kozlowski
1 sibling, 0 replies; 35+ messages in thread
From: Krzysztof Kozlowski @ 2023-06-10 16:39 UTC (permalink / raw)
To: Neil Armstrong, Jerome Brunet, Michael Turquette, Stephen Boyd,
Kevin Hilman, Martin Blumenstingl, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-amlogic, linux-clk, linux-arm-kernel, linux-kernel, devicetree
On 07/06/2023 12:56, Neil Armstrong wrote:
> Due to a policy change in clock ID bindings handling, expose
> all the "private" clock IDs to the public clock dt-bindings
> to move out of the previous maintenance scheme.
>
> This refers to a discussion at [1] & [2] with Krzysztof about
> the issue with the current maintenance.
>
> It was decided to move every A1 pll ID to the public clock
> dt-bindings headers to be merged in a single tree so we
> can safely add new clocks without having merge issues.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 13/18] dt-bindings: clk: axg-audio-clkc: expose all clock ids
2023-06-07 10:56 ` [PATCH 13/18] dt-bindings: clk: axg-audio-clkc: " Neil Armstrong
@ 2023-06-10 16:39 ` Krzysztof Kozlowski
0 siblings, 0 replies; 35+ messages in thread
From: Krzysztof Kozlowski @ 2023-06-10 16:39 UTC (permalink / raw)
To: Neil Armstrong, Jerome Brunet, Michael Turquette, Stephen Boyd,
Kevin Hilman, Martin Blumenstingl, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-amlogic, linux-clk, linux-arm-kernel, linux-kernel, devicetree
On 07/06/2023 12:56, Neil Armstrong wrote:
> Due to a policy change in clock ID bindings handling, expose
> all the "private" clock IDs to the public clock dt-bindings
> to move out of the previous maintenance scheme.
>
> This refers to a discussion at [1] & [2] with Krzysztof about
> the issue with the current maintenance.
>
> It was decided to move every axg-audio-clkc ID to the public clock
> dt-bindings headers to be merged in a single tree so we
> can safely add new clocks without having merge issues.
>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 35+ messages in thread
end of thread, other threads:[~2023-06-10 16:40 UTC | newest]
Thread overview: 35+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-06-07 10:56 [PATCH 00/18] clk: meson: move all private clk IDs to public dt-bindings headers Neil Armstrong
2023-06-07 10:56 ` [PATCH 02/18] clk: meson: migrate meson-aoclk out of hw_onecell_data to drop NR_CLKS Neil Armstrong
2023-06-07 10:56 ` [PATCH 03/18] clk: meson: migrate a1 clock drivers " Neil Armstrong
2023-06-08 12:45 ` Jerome Brunet
2023-06-08 12:53 ` Neil Armstrong
2023-06-09 11:48 ` Dmitry Rokosov
2023-06-09 12:47 ` Neil Armstrong
2023-06-09 12:57 ` Dmitry Rokosov
2023-06-09 14:30 ` Jerome Brunet
2023-06-09 15:32 ` Neil Armstrong
2023-06-07 10:56 ` [PATCH 04/18] clk: meson: migrate meson8b " Neil Armstrong
2023-06-07 10:56 ` [PATCH 05/18] clk: meson: migrate axg-audio " Neil Armstrong
2023-06-07 10:56 ` [PATCH 06/18] dt-bindings: clk: gxbb-clkc: expose all clock ids Neil Armstrong
2023-06-10 16:38 ` Krzysztof Kozlowski
2023-06-07 10:56 ` [PATCH 07/18] dt-bindings: clk: axg-clkc: " Neil Armstrong
2023-06-10 16:38 ` Krzysztof Kozlowski
2023-06-07 10:56 ` [PATCH 08/18] dt-bindings: clk: g12a-clks: " Neil Armstrong
2023-06-10 16:38 ` Krzysztof Kozlowski
2023-06-07 10:56 ` [PATCH 09/18] dt-bindings: clk: g12a-aoclkc: " Neil Armstrong
2023-06-10 16:38 ` Krzysztof Kozlowski
2023-06-07 10:56 ` [PATCH 10/18] dt-bindings: clk: meson8b-clkc: " Neil Armstrong
2023-06-10 16:38 ` Krzysztof Kozlowski
2023-06-07 10:56 ` [PATCH 11/18] dt-bindings: clk: amlogic,a1-peripherals-clkc: " Neil Armstrong
2023-06-09 12:04 ` Dmitry Rokosov
2023-06-10 16:38 ` Krzysztof Kozlowski
2023-06-07 10:56 ` [PATCH 12/18] dt-bindings: clk: amlogic,a1-pll-clkc: " Neil Armstrong
2023-06-09 12:10 ` Dmitry Rokosov
2023-06-10 16:39 ` Krzysztof Kozlowski
2023-06-07 10:56 ` [PATCH 13/18] dt-bindings: clk: axg-audio-clkc: " Neil Armstrong
2023-06-10 16:39 ` Krzysztof Kozlowski
2023-06-07 10:56 ` [PATCH 14/18] clk: meson: aoclk: move bindings include to main driver Neil Armstrong
2023-06-07 10:56 ` [PATCH 15/18] clk: meson: eeclk: " Neil Armstrong
2023-06-07 10:56 ` [PATCH 16/18] clk: meson: a1: " Neil Armstrong
2023-06-07 10:56 ` [PATCH 17/18] clk: meson: meson8b: " Neil Armstrong
2023-06-07 10:56 ` [PATCH 18/18] clk: meson: axg-audio: " Neil Armstrong
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