From: Grygorii Strashko <grygorii.strashko@ti.com>
To: Dario Binacchi <dariobin@libero.it>,
<linux-kernel@vger.kernel.org>,
"Vutla, Lokesh" <lokeshvutla@ti.com>,
"Menon, Nishanth" <nm@ti.com>
Cc: "Benoît Cousson" <bcousson@baylibre.com>,
"Lee Jones" <lee.jones@linaro.org>,
"Michael Turquette" <mturquette@baylibre.com>,
"Rob Herring" <robh+dt@kernel.org>,
"Stephen Boyd" <sboyd@kernel.org>,
"Tero Kristo" <kristo@kernel.org>,
"Tony Lindgren" <tony@atomide.com>,
devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
linux-omap@vger.kernel.org
Subject: Re: [PATCH 4/4] clk: ti: add am33xx spread spectrum clock support
Date: Thu, 18 Mar 2021 14:08:07 +0200 [thread overview]
Message-ID: <64771168-1222-cfb5-f79c-31a945b713a5@ti.com> (raw)
In-Reply-To: <2069482516.552063.1616053134087@mail1.libero.it>
On 18/03/2021 09:38, Dario Binacchi wrote:
> Hi Grygorii,
>
>> Il 16/03/2021 12:52 Grygorii Strashko <grygorii.strashko@ti.com> ha scritto:
>>
>>
>> On 14/03/2021 17:12, Dario Binacchi wrote:
>>> The patch enables spread spectrum clocking (SSC) for MPU and LCD PLLs.
>>> As reported by the TI spruh73x RM, SSC is only supported for the
>>> DISP/LCD and MPU PLLs on am33xx device. SSC is not supported for DDR,
>>> PER, and CORE PLLs.
>>>
>>> Calculating the required values and setting the registers accordingly
>>> was taken from the set_mpu_spreadspectrum routine contained in the
>>> arch/arm/mach-omap2/am33xx/clock_am33xx.c file of the u-boot project.
>>>
>>> In locked condition, DPLL output clock = CLKINP *[M/N]. In case of
>>> SSC enabled, the AM335x reference manual explains that there is a
>>> restriction of range of M values. Since the omap2_dpll_round_rate
>>> routine attempts to select the minimum possible N, the value of M
>>> obtained is not guaranteed to be within the range required. With the new
>>> "ti,min-div" parameter it is possible to increase N and consequently M
>>> to satisfy the constraint imposed by SSC.
>>>
>>> Signed-off-by: Dario Binacchi <dariobin@libero.it>
>>>
>>> ---
>>>
>>> arch/arm/boot/dts/am33xx-clocks.dtsi | 4 +-
>>> drivers/clk/ti/dpll.c | 41 ++++++++++++++
>>> drivers/clk/ti/dpll3xxx.c | 85 ++++++++++++++++++++++++++++
>>> include/linux/clk/ti.h | 24 ++++++++
>>> 4 files changed, 152 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi
>>> index e7bbbf536a8c..a02e0b1229a4 100644
>>> --- a/arch/arm/boot/dts/am33xx-clocks.dtsi
>>> +++ b/arch/arm/boot/dts/am33xx-clocks.dtsi
>>> @@ -164,7 +164,7 @@
>>> #clock-cells = <0>;
>>> compatible = "ti,am3-dpll-core-clock";
>>> clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
>>> - reg = <0x0490>, <0x045c>, <0x0468>, <0x0460>, <0x0464>;
>>> + reg = <0x0490>, <0x045c>, <0x0468>;
>>> };
>>>
>>> dpll_core_x2_ck: dpll_core_x2_ck {
>>> @@ -204,7 +204,7 @@
>>> #clock-cells = <0>;
>>> compatible = "ti,am3-dpll-clock";
>>> clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
>>> - reg = <0x0488>, <0x0420>, <0x042c>;
>>> + reg = <0x0488>, <0x0420>, <0x042c>, <0x0424>, <0x0428>;
>>> };
>>
>> You can't mix DT vs code.
>
> Right, I forgot to remove it during a rebase of the series.
>
>>
>>>
>>> dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 {
>>> diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c
>>> index d6f1ac5b53e1..2738417a47b7 100644
>>> --- a/drivers/clk/ti/dpll.c
>>> +++ b/drivers/clk/ti/dpll.c
>>> @@ -290,7 +290,9 @@ static void __init of_ti_dpll_setup(struct device_node *node,
>>> struct clk_init_data *init = NULL;
>>> const char **parent_names = NULL;
>>> struct dpll_data *dd = NULL;
>>> + int ssc_clk_index;
>>> u8 dpll_mode = 0;
>>> + u32 min_div;
>>>
>>> dd = kmemdup(ddt, sizeof(*dd), GFP_KERNEL);
>>> clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
>>> @@ -345,6 +347,27 @@ static void __init of_ti_dpll_setup(struct device_node *node,
>>> if (dd->autoidle_mask) {
>>> if (ti_clk_get_reg_addr(node, 3, &dd->autoidle_reg))
>>> goto cleanup;
>>> +
>>> + ssc_clk_index = 4;
>>> + } else {
>>> + ssc_clk_index = 3;
>>> + }
>>> +
>>> + if (dd->ssc_deltam_int_mask && dd->ssc_deltam_frac_mask &&
>>> + dd->ssc_modfreq_mant_mask && dd->ssc_modfreq_exp_mask) {
>>> + if (ti_clk_get_reg_addr(node, ssc_clk_index++,
>>> + &dd->ssc_deltam_reg))
>>> + goto cleanup;
>>> +
>>> + if (ti_clk_get_reg_addr(node, ssc_clk_index++,
>>> + &dd->ssc_modfreq_reg))
>>> + goto cleanup;
>>> +
>>> + of_property_read_u32(node, "ti,ssc-modfreq", &dd->ssc_modfreq);
>>> + of_property_read_u32(node, "ti,ssc-deltam", &dd->ssc_deltam);
>>> + if (of_property_read_bool(node, "ti,ssc-downspread"))
>>> + dd->ssc_downspread = 1;
>>
>> New bindings.
>
> I added the bindings documentation in another patch of the series.
>
oh. sorry I've not received it for some reasons :(
--
Best regards,
grygorii
prev parent reply other threads:[~2021-03-18 12:10 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-14 15:12 [PATCH 0/4] clk: ti: add am33xx spread spectrum clock support Dario Binacchi
2021-03-14 15:12 ` [PATCH 1/4] clk: ti: fix typo in routine description Dario Binacchi
2021-03-14 15:12 ` [PATCH 2/4] dt-bindings: ti: dpll: add spread spectrum support Dario Binacchi
2021-03-14 15:12 ` [PATCH 4/4] clk: ti: add am33xx spread spectrum clock support Dario Binacchi
2021-03-16 11:52 ` Grygorii Strashko
2021-03-18 7:38 ` Dario Binacchi
2021-03-18 12:08 ` Grygorii Strashko [this message]
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