[PATCH v2 0/3] clk: zynqmp: Add firmware specific clock flags

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* [PATCH v2 0/3] clk: zynqmp: Add firmware specific clock flags
@ 2020-07-22  6:55 Amit Sunil Dhamne
  2020-07-22  6:55 ` [PATCH v2 1/3] clk: zynqmp: Use firmware specific common " Amit Sunil Dhamne
                   ` (3 more replies)
  0 siblings, 4 replies; 10+ messages in thread
From: Amit Sunil Dhamne @ 2020-07-22  6:55 UTC (permalink / raw)
  To: mturquette, m.tretter, sboyd, sboyd, michal.simek, mark.rutland,
	linux-clk
  Cc: rajanv, jollys, tejasp, linux-arm-kernel, linux-kernel,
	Amit Sunil Dhamne

This series adds supports for firmware specific flags. These include
- Common Flags
- Divider Flags
- Mux Flags

The intent is to remove firmware's dependency on CCF flag values by having
firmware specific flags with independent values.

Currently firmware is maintaining CCF specific flags and provides to
CCF as it is. But CCF flag numbers may change and that shouldn't mean
that the firmware needs to change. The firmware should have its own
'flag number space' that is distinct from the common clk framework's
'flag number space'. So use firmware specific clock flags in ZynqMP
clock driver instead of CCF flags.

Changes in v2:
 - Add helper function to map zynqmp flags with CCF flags.
 - Mapped zynqmp clock flags with CCF flags from
   zynqmp_clk_register_*() functions instead of
   __zynqmp_clock_get_topology() which is changing the flags to struct
   clk_init_data instead of the struct clock_topology.

Rajan Vaja (3):
  clk: zynqmp: Use firmware specific common clock flags
  clk: zynqmp: Use firmware specific divider clock flags
  clk: zynqmp: Use firmware specific mux clock flags

 drivers/clk/zynqmp/clk-gate-zynqmp.c |  4 +++-
 drivers/clk/zynqmp/clk-mux-zynqmp.c  | 18 ++++++++++++++--
 drivers/clk/zynqmp/clk-zynqmp.h      | 42 ++++++++++++++++++++++++++++++++++++
 drivers/clk/zynqmp/clkc.c            | 31 +++++++++++++++++++++++++-
 drivers/clk/zynqmp/divider.c         | 21 +++++++++++++++---
 drivers/clk/zynqmp/pll.c             |  4 +++-
 6 files changed, 112 insertions(+), 8 deletions(-)

--
2.7.4

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* [PATCH v2 1/3] clk: zynqmp: Use firmware specific common clock flags
  2020-07-22  6:55 [PATCH v2 0/3] clk: zynqmp: Add firmware specific clock flags Amit Sunil Dhamne
@ 2020-07-22  6:55 ` Amit Sunil Dhamne
  2020-07-22 13:22   ` Michael Tretter
  2020-07-22  6:55 ` [PATCH v2 2/3] clk: zynqmp: Use firmware specific divider " Amit Sunil Dhamne
                   ` (2 subsequent siblings)
  3 siblings, 1 reply; 10+ messages in thread
From: Amit Sunil Dhamne @ 2020-07-22  6:55 UTC (permalink / raw)
  To: mturquette, m.tretter, sboyd, sboyd, michal.simek, mark.rutland,
	linux-clk
  Cc: rajanv, jollys, tejasp, linux-arm-kernel, linux-kernel,
	Rajan Vaja, Tejas Patel, Amit Sunil Dhamne

From: Rajan Vaja <rajan.vaja@xilinx.com>

Currently firmware passes CCF specific flags to ZynqMP clock driver.
So firmware needs to be updated if CCF flags are changed. The firmware
should have its own 'flag number space' that is distinct from the
common clk framework's 'flag number space'. So define and use ZynqMP
specific common clock flags instead of using CCF flags.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Amit Sunil Dhamne <amit.sunil.dhamne@xilinx.com>
---
 drivers/clk/zynqmp/clk-gate-zynqmp.c |  4 +++-
 drivers/clk/zynqmp/clk-mux-zynqmp.c  |  4 +++-
 drivers/clk/zynqmp/clk-zynqmp.h      | 25 +++++++++++++++++++++++++
 drivers/clk/zynqmp/clkc.c            | 31 ++++++++++++++++++++++++++++++-
 drivers/clk/zynqmp/divider.c         |  5 +++--
 drivers/clk/zynqmp/pll.c             |  4 +++-
 6 files changed, 67 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/zynqmp/clk-gate-zynqmp.c b/drivers/clk/zynqmp/clk-gate-zynqmp.c
index 10c9b88..bcabebf 100644
--- a/drivers/clk/zynqmp/clk-gate-zynqmp.c
+++ b/drivers/clk/zynqmp/clk-gate-zynqmp.c
@@ -121,7 +121,9 @@ struct clk_hw *zynqmp_clk_register_gate(const char *name, u32 clk_id,

        init.name = name;
        init.ops = &zynqmp_clk_gate_ops;
-       init.flags = nodes->flag;
+
+       zynqmp_clk_map_common_ccf_flags(nodes->flag, &init.flags);
+
        init.parent_names = parents;
        init.num_parents = 1;

diff --git a/drivers/clk/zynqmp/clk-mux-zynqmp.c b/drivers/clk/zynqmp/clk-mux-zynqmp.c
index 0619414..1dc17a0 100644
--- a/drivers/clk/zynqmp/clk-mux-zynqmp.c
+++ b/drivers/clk/zynqmp/clk-mux-zynqmp.c
@@ -120,7 +120,9 @@ struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id,
                init.ops = &zynqmp_clk_mux_ro_ops;
        else
                init.ops = &zynqmp_clk_mux_ops;
-       init.flags = nodes->flag;
+
+       zynqmp_clk_map_common_ccf_flags(nodes->flag, &init.flags);
+
        init.parent_names = parents;
        init.num_parents = num_parents;
        mux->flags = nodes->type_flag;
diff --git a/drivers/clk/zynqmp/clk-zynqmp.h b/drivers/clk/zynqmp/clk-zynqmp.h
index 5beeb41..3cb6149 100644
--- a/drivers/clk/zynqmp/clk-zynqmp.h
+++ b/drivers/clk/zynqmp/clk-zynqmp.h
@@ -10,6 +10,28 @@

 #include <linux/firmware/xlnx-zynqmp.h>

+/* Common Flags */
+/* must be gated across rate change */
+#define ZYNQMP_CLK_SET_RATE_GATE       BIT(0)
+/* must be gated across re-parent */
+#define ZYNQMP_CLK_SET_PARENT_GATE     BIT(1)
+/* propagate rate change up one level */
+#define ZYNQMP_CLK_SET_RATE_PARENT     BIT(2)
+/* do not gate even if unused */
+#define ZYNQMP_CLK_IGNORE_UNUSED       BIT(3)
+/* do not use the cached clk rate */
+#define ZYNQMP_CLK_GET_RATE_NOCACHE    BIT(6)
+/* don't re-parent on rate change */
+#define ZYNQMP_CLK_SET_RATE_NO_REPARENT        BIT(7)
+/* do not use the cached clk accuracy */
+#define ZYNQMP_CLK_GET_ACCURACY_NOCACHE        BIT(8)
+/* recalc rates after notifications */
+#define ZYNQMP_CLK_RECALC_NEW_RATES    BIT(9)
+/* clock needs to run to set rate */
+#define ZYNQMP_CLK_SET_RATE_UNGATE     BIT(10)
+/* do not gate, ever */
+#define ZYNQMP_CLK_IS_CRITICAL         BIT(11)
+
 enum topology_type {
        TYPE_INVALID,
        TYPE_MUX,
@@ -33,6 +55,9 @@ struct clock_topology {
        u8 custom_type_flag;
 };

+void zynqmp_clk_map_common_ccf_flags(const u32 zynqmp_flag,
+                                    unsigned long *ccf_flag);
+
 struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id,
                                       const char * const *parents,
                                       u8 num_parents,
diff --git a/drivers/clk/zynqmp/clkc.c b/drivers/clk/zynqmp/clkc.c
index db8d0d7..11351f6 100644
--- a/drivers/clk/zynqmp/clkc.c
+++ b/drivers/clk/zynqmp/clkc.c
@@ -271,6 +271,32 @@ static int zynqmp_pm_clock_get_topology(u32 clock_id, u32 index,
        return ret;
 }

+void zynqmp_clk_map_common_ccf_flags(const u32 zynqmp_flag,
+                                    unsigned long *ccf_flag)
+{
+       *ccf_flag = 0;
+       *ccf_flag |= (zynqmp_flag & ZYNQMP_CLK_SET_RATE_GATE) ?
+                     CLK_SET_RATE_GATE : 0;
+       *ccf_flag |= (zynqmp_flag & ZYNQMP_CLK_SET_PARENT_GATE) ?
+                     CLK_SET_PARENT_GATE : 0;
+       *ccf_flag |= (zynqmp_flag & ZYNQMP_CLK_SET_RATE_PARENT) ?
+                     CLK_SET_RATE_PARENT : 0;
+       *ccf_flag |= (zynqmp_flag & ZYNQMP_CLK_IGNORE_UNUSED) ?
+                     CLK_IGNORE_UNUSED : 0;
+       *ccf_flag |= (zynqmp_flag & ZYNQMP_CLK_GET_RATE_NOCACHE) ?
+                     CLK_GET_RATE_NOCACHE : 0;
+       *ccf_flag |= (zynqmp_flag & ZYNQMP_CLK_SET_RATE_NO_REPARENT) ?
+                     CLK_SET_RATE_NO_REPARENT : 0;
+       *ccf_flag |= (zynqmp_flag & ZYNQMP_CLK_GET_ACCURACY_NOCACHE) ?
+                     CLK_GET_ACCURACY_NOCACHE : 0;
+       *ccf_flag |= (zynqmp_flag & ZYNQMP_CLK_RECALC_NEW_RATES) ?
+                     CLK_RECALC_NEW_RATES : 0;
+       *ccf_flag |= (zynqmp_flag & ZYNQMP_CLK_SET_RATE_UNGATE) ?
+                     CLK_SET_RATE_UNGATE : 0;
+       *ccf_flag |= (zynqmp_flag & ZYNQMP_CLK_IS_CRITICAL) ?
+                     CLK_IS_CRITICAL : 0;
+}
+
 /**
  * zynqmp_clk_register_fixed_factor() - Register fixed factor with the
  *                                     clock framework
@@ -292,6 +318,7 @@ struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name, u32 clk_id,
        struct zynqmp_pm_query_data qdata = {0};
        u32 ret_payload[PAYLOAD_ARG_CNT];
        int ret;
+       unsigned long flag;

        qdata.qid = PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS;
        qdata.arg1 = clk_id;
@@ -303,9 +330,11 @@ struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name, u32 clk_id,
        mult = ret_payload[1];
        div = ret_payload[2];

+       zynqmp_clk_map_common_ccf_flags(nodes->flag, &flag);
+
        hw = clk_hw_register_fixed_factor(NULL, name,
                                          parents[0],
-                                         nodes->flag, mult,
+                                         flag, mult,
                                          div);

        return hw;
diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c
index 66da02b..3ab57d9 100644
--- a/drivers/clk/zynqmp/divider.c
+++ b/drivers/clk/zynqmp/divider.c
@@ -311,8 +311,9 @@ struct clk_hw *zynqmp_clk_register_divider(const char *name,

        init.name = name;
        init.ops = &zynqmp_clk_divider_ops;
-       /* CLK_FRAC is not defined in the common clk framework */
-       init.flags = nodes->flag & ~CLK_FRAC;
+
+       zynqmp_clk_map_common_ccf_flags(nodes->flag, &init.flags);
+
        init.parent_names = parents;
        init.num_parents = 1;

diff --git a/drivers/clk/zynqmp/pll.c b/drivers/clk/zynqmp/pll.c
index 92f449e..1b7e231 100644
--- a/drivers/clk/zynqmp/pll.c
+++ b/drivers/clk/zynqmp/pll.c
@@ -302,7 +302,9 @@ struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id,

        init.name = name;
        init.ops = &zynqmp_pll_ops;
-       init.flags = nodes->flag;
+
+       zynqmp_clk_map_common_ccf_flags(nodes->flag, &init.flags);
+
        init.parent_names = parents;
        init.num_parents = 1;

--
2.7.4

This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.

^ permalink raw reply related	[flat|nested] 10+ messages in thread

* Re: [PATCH v2 1/3] clk: zynqmp: Use firmware specific common clock flags
  2020-07-22  6:55 ` [PATCH v2 1/3] clk: zynqmp: Use firmware specific common " Amit Sunil Dhamne
@ 2020-07-22 13:22   ` Michael Tretter
  2020-07-23 23:46     ` Amit Sunil Dhamne
  0 siblings, 1 reply; 10+ messages in thread
From: Michael Tretter @ 2020-07-22 13:22 UTC (permalink / raw)
  To: Amit Sunil Dhamne
  Cc: mturquette, sboyd, sboyd, michal.simek, mark.rutland, linux-clk,
	rajanv, jollys, tejasp, linux-arm-kernel, linux-kernel,
	Rajan Vaja, Tejas Patel

On Tue, 21 Jul 2020 23:55:30 -0700, Amit Sunil Dhamne wrote:
> From: Rajan Vaja <rajan.vaja@xilinx.com>
> 
> Currently firmware passes CCF specific flags to ZynqMP clock driver.
> So firmware needs to be updated if CCF flags are changed. The firmware
> should have its own 'flag number space' that is distinct from the
> common clk framework's 'flag number space'. So define and use ZynqMP
> specific common clock flags instead of using CCF flags.
> 
> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
> Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
> Signed-off-by: Amit Sunil Dhamne <amit.sunil.dhamne@xilinx.com>
> ---
>  drivers/clk/zynqmp/clk-gate-zynqmp.c |  4 +++-
>  drivers/clk/zynqmp/clk-mux-zynqmp.c  |  4 +++-
>  drivers/clk/zynqmp/clk-zynqmp.h      | 25 +++++++++++++++++++++++++
>  drivers/clk/zynqmp/clkc.c            | 31 ++++++++++++++++++++++++++++++-
>  drivers/clk/zynqmp/divider.c         |  5 +++--
>  drivers/clk/zynqmp/pll.c             |  4 +++-
>  6 files changed, 67 insertions(+), 6 deletions(-)
> 
[snip]
> diff --git a/drivers/clk/zynqmp/clkc.c b/drivers/clk/zynqmp/clkc.c
> index db8d0d7..11351f6 100644
> --- a/drivers/clk/zynqmp/clkc.c
> +++ b/drivers/clk/zynqmp/clkc.c
> @@ -271,6 +271,32 @@ static int zynqmp_pm_clock_get_topology(u32 clock_id, u32 index,
>         return ret;
>  }
> 
> +void zynqmp_clk_map_common_ccf_flags(const u32 zynqmp_flag,
> +                                    unsigned long *ccf_flag)
> +{
> +       *ccf_flag = 0;
> +       *ccf_flag |= (zynqmp_flag & ZYNQMP_CLK_SET_RATE_GATE) ?
> +                     CLK_SET_RATE_GATE : 0;
> +       *ccf_flag |= (zynqmp_flag & ZYNQMP_CLK_SET_PARENT_GATE) ?
> +                     CLK_SET_PARENT_GATE : 0;
> +       *ccf_flag |= (zynqmp_flag & ZYNQMP_CLK_SET_RATE_PARENT) ?
> +                     CLK_SET_RATE_PARENT : 0;
> +       *ccf_flag |= (zynqmp_flag & ZYNQMP_CLK_IGNORE_UNUSED) ?
> +                     CLK_IGNORE_UNUSED : 0;
> +       *ccf_flag |= (zynqmp_flag & ZYNQMP_CLK_GET_RATE_NOCACHE) ?
> +                     CLK_GET_RATE_NOCACHE : 0;
> +       *ccf_flag |= (zynqmp_flag & ZYNQMP_CLK_SET_RATE_NO_REPARENT) ?
> +                     CLK_SET_RATE_NO_REPARENT : 0;
> +       *ccf_flag |= (zynqmp_flag & ZYNQMP_CLK_GET_ACCURACY_NOCACHE) ?
> +                     CLK_GET_ACCURACY_NOCACHE : 0;
> +       *ccf_flag |= (zynqmp_flag & ZYNQMP_CLK_RECALC_NEW_RATES) ?
> +                     CLK_RECALC_NEW_RATES : 0;
> +       *ccf_flag |= (zynqmp_flag & ZYNQMP_CLK_SET_RATE_UNGATE) ?
> +                     CLK_SET_RATE_UNGATE : 0;
> +       *ccf_flag |= (zynqmp_flag & ZYNQMP_CLK_IS_CRITICAL) ?
> +                     CLK_IS_CRITICAL : 0;
> +}

What is the reason for returning the resulting flags via pointer? I would have
expected something like the following function:

unsigned long zynqmp_clk_flags_to_clk_flags(const u32 zyqnmp_flags)
{
	unsigned long flags = 0;

	if (zynqmp_flag & ZYNQMP_CLK_SET_RATE_GATE)
		flags |= CLK_SET_RATE_GATE;
	/* ... */

	return flags;
}

Michael

> +
>  /**
>   * zynqmp_clk_register_fixed_factor() - Register fixed factor with the
>   *                                     clock framework
> @@ -292,6 +318,7 @@ struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name, u32 clk_id,
>         struct zynqmp_pm_query_data qdata = {0};
>         u32 ret_payload[PAYLOAD_ARG_CNT];
>         int ret;
> +       unsigned long flag;
> 
>         qdata.qid = PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS;
>         qdata.arg1 = clk_id;
> @@ -303,9 +330,11 @@ struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name, u32 clk_id,
>         mult = ret_payload[1];
>         div = ret_payload[2];
> 
> +       zynqmp_clk_map_common_ccf_flags(nodes->flag, &flag);
> +
>         hw = clk_hw_register_fixed_factor(NULL, name,
>                                           parents[0],
> -                                         nodes->flag, mult,
> +                                         flag, mult,
>                                           div);
> 
>         return hw;
> diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c
> index 66da02b..3ab57d9 100644
> --- a/drivers/clk/zynqmp/divider.c
> +++ b/drivers/clk/zynqmp/divider.c
> @@ -311,8 +311,9 @@ struct clk_hw *zynqmp_clk_register_divider(const char *name,
> 
>         init.name = name;
>         init.ops = &zynqmp_clk_divider_ops;
> -       /* CLK_FRAC is not defined in the common clk framework */
> -       init.flags = nodes->flag & ~CLK_FRAC;
> +
> +       zynqmp_clk_map_common_ccf_flags(nodes->flag, &init.flags);
> +
>         init.parent_names = parents;
>         init.num_parents = 1;
> 
> diff --git a/drivers/clk/zynqmp/pll.c b/drivers/clk/zynqmp/pll.c
> index 92f449e..1b7e231 100644
> --- a/drivers/clk/zynqmp/pll.c
> +++ b/drivers/clk/zynqmp/pll.c
> @@ -302,7 +302,9 @@ struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id,
> 
>         init.name = name;
>         init.ops = &zynqmp_pll_ops;
> -       init.flags = nodes->flag;
> +
> +       zynqmp_clk_map_common_ccf_flags(nodes->flag, &init.flags);
> +
>         init.parent_names = parents;
>         init.num_parents = 1;
> 
> --
> 2.7.4
> 
> This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.
> 

^ permalink raw reply	[flat|nested] 10+ messages in thread

* RE: [PATCH v2 1/3] clk: zynqmp: Use firmware specific common clock flags
  2020-07-22 13:22   ` Michael Tretter
@ 2020-07-23 23:46     ` Amit Sunil Dhamne
  0 siblings, 0 replies; 10+ messages in thread
From: Amit Sunil Dhamne @ 2020-07-23 23:46 UTC (permalink / raw)
  To: Michael Tretter
  Cc: mturquette, sboyd, sboyd, Michal Simek, mark.rutland, linux-clk,
	Rajan Vaja, Jolly Shah, Tejas Patel, linux-arm-kernel,
	linux-kernel, Rajan Vaja, Tejas Patel

Hi Michael,
Thanks for the review. Replies inline.

Thanks,
Amit

> -----Original Message-----
> From: Michael Tretter <m.tretter@pengutronix.de>
> Sent: Wednesday, July 22, 2020 6:23 AM
> To: Amit Sunil Dhamne <amitsuni@xilinx.com>
> Cc: mturquette@baylibre.com; sboyd@codeaurora.org; sboyd@kernel.org;
> Michal Simek <michals@xilinx.com>; mark.rutland@arm.com; linux-
> clk@vger.kernel.org; Rajan Vaja <RAJANV@xilinx.com>; Jolly Shah
> <JOLLYS@xilinx.com>; Tejas Patel <TEJASP@xilinx.com>; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org; Rajan Vaja
> <RAJANV@xilinx.com>; Tejas Patel <TEJASP@xilinx.com>
> Subject: Re: [PATCH v2 1/3] clk: zynqmp: Use firmware specific common clock
> flags
> 
> On Tue, 21 Jul 2020 23:55:30 -0700, Amit Sunil Dhamne wrote:
> > From: Rajan Vaja <rajan.vaja@xilinx.com>
> >
> > Currently firmware passes CCF specific flags to ZynqMP clock driver.
> > So firmware needs to be updated if CCF flags are changed. The firmware
> > should have its own 'flag number space' that is distinct from the
> > common clk framework's 'flag number space'. So define and use ZynqMP
> > specific common clock flags instead of using CCF flags.
> >
> > Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
> > Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
> > Signed-off-by: Amit Sunil Dhamne <amit.sunil.dhamne@xilinx.com>
> > ---
> >  drivers/clk/zynqmp/clk-gate-zynqmp.c |  4 +++-
> >  drivers/clk/zynqmp/clk-mux-zynqmp.c  |  4 +++-
> >  drivers/clk/zynqmp/clk-zynqmp.h      | 25 +++++++++++++++++++++++++
> >  drivers/clk/zynqmp/clkc.c            | 31 ++++++++++++++++++++++++++++++-
> >  drivers/clk/zynqmp/divider.c         |  5 +++--
> >  drivers/clk/zynqmp/pll.c             |  4 +++-
> >  6 files changed, 67 insertions(+), 6 deletions(-)
> >
> [snip]
> > diff --git a/drivers/clk/zynqmp/clkc.c b/drivers/clk/zynqmp/clkc.c
> > index db8d0d7..11351f6 100644
> > --- a/drivers/clk/zynqmp/clkc.c
> > +++ b/drivers/clk/zynqmp/clkc.c
> > @@ -271,6 +271,32 @@ static int zynqmp_pm_clock_get_topology(u32
> clock_id, u32 index,
> >         return ret;
> >  }
> >
> > +void zynqmp_clk_map_common_ccf_flags(const u32 zynqmp_flag,
> > +                                    unsigned long *ccf_flag)
> > +{
> > +       *ccf_flag = 0;
> > +       *ccf_flag |= (zynqmp_flag & ZYNQMP_CLK_SET_RATE_GATE) ?
> > +                     CLK_SET_RATE_GATE : 0;
> > +       *ccf_flag |= (zynqmp_flag & ZYNQMP_CLK_SET_PARENT_GATE) ?
> > +                     CLK_SET_PARENT_GATE : 0;
> > +       *ccf_flag |= (zynqmp_flag & ZYNQMP_CLK_SET_RATE_PARENT) ?
> > +                     CLK_SET_RATE_PARENT : 0;
> > +       *ccf_flag |= (zynqmp_flag & ZYNQMP_CLK_IGNORE_UNUSED) ?
> > +                     CLK_IGNORE_UNUSED : 0;
> > +       *ccf_flag |= (zynqmp_flag & ZYNQMP_CLK_GET_RATE_NOCACHE) ?
> > +                     CLK_GET_RATE_NOCACHE : 0;
> > +       *ccf_flag |= (zynqmp_flag & ZYNQMP_CLK_SET_RATE_NO_REPARENT)
> ?
> > +                     CLK_SET_RATE_NO_REPARENT : 0;
> > +       *ccf_flag |= (zynqmp_flag &
> ZYNQMP_CLK_GET_ACCURACY_NOCACHE) ?
> > +                     CLK_GET_ACCURACY_NOCACHE : 0;
> > +       *ccf_flag |= (zynqmp_flag & ZYNQMP_CLK_RECALC_NEW_RATES) ?
> > +                     CLK_RECALC_NEW_RATES : 0;
> > +       *ccf_flag |= (zynqmp_flag & ZYNQMP_CLK_SET_RATE_UNGATE) ?
> > +                     CLK_SET_RATE_UNGATE : 0;
> > +       *ccf_flag |= (zynqmp_flag & ZYNQMP_CLK_IS_CRITICAL) ?
> > +                     CLK_IS_CRITICAL : 0;
> > +}
> 
> What is the reason for returning the resulting flags via pointer? I would have
> expected something like the following function:
> 
> unsigned long zynqmp_clk_flags_to_clk_flags(const u32 zyqnmp_flags)
> {
> 	unsigned long flags = 0;
> 
> 	if (zynqmp_flag & ZYNQMP_CLK_SET_RATE_GATE)
> 		flags |= CLK_SET_RATE_GATE;
> 	/* ... */
> 
> 	return flags;
> }
> 
> Michael
> 
[Amit] There's no particular reason for returning values through pointer. I will send a next version of patch with the format you suggested.
> > +
> >  /**
> >   * zynqmp_clk_register_fixed_factor() - Register fixed factor with the
> >   *                                     clock framework
> > @@ -292,6 +318,7 @@ struct clk_hw
> *zynqmp_clk_register_fixed_factor(const char *name, u32 clk_id,
> >         struct zynqmp_pm_query_data qdata = {0};
> >         u32 ret_payload[PAYLOAD_ARG_CNT];
> >         int ret;
> > +       unsigned long flag;
> >
> >         qdata.qid = PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS;
> >         qdata.arg1 = clk_id;
> > @@ -303,9 +330,11 @@ struct clk_hw
> *zynqmp_clk_register_fixed_factor(const char *name, u32 clk_id,
> >         mult = ret_payload[1];
> >         div = ret_payload[2];
> >
> > +       zynqmp_clk_map_common_ccf_flags(nodes->flag, &flag);
> > +
> >         hw = clk_hw_register_fixed_factor(NULL, name,
> >                                           parents[0],
> > -                                         nodes->flag, mult,
> > +                                         flag, mult,
> >                                           div);
> >
> >         return hw;
> > diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c
> > index 66da02b..3ab57d9 100644
> > --- a/drivers/clk/zynqmp/divider.c
> > +++ b/drivers/clk/zynqmp/divider.c
> > @@ -311,8 +311,9 @@ struct clk_hw *zynqmp_clk_register_divider(const
> char *name,
> >
> >         init.name = name;
> >         init.ops = &zynqmp_clk_divider_ops;
> > -       /* CLK_FRAC is not defined in the common clk framework */
> > -       init.flags = nodes->flag & ~CLK_FRAC;
> > +
> > +       zynqmp_clk_map_common_ccf_flags(nodes->flag, &init.flags);
> > +
> >         init.parent_names = parents;
> >         init.num_parents = 1;
> >
> > diff --git a/drivers/clk/zynqmp/pll.c b/drivers/clk/zynqmp/pll.c
> > index 92f449e..1b7e231 100644
> > --- a/drivers/clk/zynqmp/pll.c
> > +++ b/drivers/clk/zynqmp/pll.c
> > @@ -302,7 +302,9 @@ struct clk_hw *zynqmp_clk_register_pll(const char
> *name, u32 clk_id,
> >
> >         init.name = name;
> >         init.ops = &zynqmp_pll_ops;
> > -       init.flags = nodes->flag;
> > +
> > +       zynqmp_clk_map_common_ccf_flags(nodes->flag, &init.flags);
> > +
> >         init.parent_names = parents;
> >         init.num_parents = 1;
> >
> > --
> > 2.7.4
> >
> > This email and any attachments are intended for the sole use of the named
> recipient(s) and contain(s) confidential information that may be proprietary,
> privileged or copyrighted under applicable law. If you are not the intended
> recipient, do not read, copy, or forward this email message or any
> attachments. Delete this email message and any attachments immediately.
> >

^ permalink raw reply	[flat|nested] 10+ messages in thread

* [PATCH v2 2/3] clk: zynqmp: Use firmware specific divider clock flags
  2020-07-22  6:55 [PATCH v2 0/3] clk: zynqmp: Add firmware specific clock flags Amit Sunil Dhamne
  2020-07-22  6:55 ` [PATCH v2 1/3] clk: zynqmp: Use firmware specific common " Amit Sunil Dhamne
@ 2020-07-22  6:55 ` Amit Sunil Dhamne
  2020-07-22 13:27   ` Michael Tretter
  2020-07-22  6:55 ` [PATCH v2 3/3] clk: zynqmp: Use firmware specific mux " Amit Sunil Dhamne
  2020-07-23 22:35 ` [PATCH v2 0/3] clk: zynqmp: Add firmware specific " Stephen Boyd
  3 siblings, 1 reply; 10+ messages in thread
From: Amit Sunil Dhamne @ 2020-07-22  6:55 UTC (permalink / raw)
  To: mturquette, m.tretter, sboyd, sboyd, michal.simek, mark.rutland,
	linux-clk
  Cc: rajanv, jollys, tejasp, linux-arm-kernel, linux-kernel,
	Rajan Vaja, Tejas Patel, Amit Sunil Dhamne

From: Rajan Vaja <rajan.vaja@xilinx.com>

Use ZynqMP specific divider clock flags instead of using CCF flags.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Amit Sunil Dhamne <amit.sunil.dhamne@xilinx.com>
---
 drivers/clk/zynqmp/clk-zynqmp.h |  9 +++++++++
 drivers/clk/zynqmp/divider.c    | 16 +++++++++++++++-
 2 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/zynqmp/clk-zynqmp.h b/drivers/clk/zynqmp/clk-zynqmp.h
index 3cb6149..ec33525 100644
--- a/drivers/clk/zynqmp/clk-zynqmp.h
+++ b/drivers/clk/zynqmp/clk-zynqmp.h
@@ -32,6 +32,15 @@
 /* do not gate, ever */
 #define ZYNQMP_CLK_IS_CRITICAL         BIT(11)

+/* Type Flags for divider clock */
+#define ZYNQMP_CLK_DIVIDER_ONE_BASED           BIT(0)
+#define ZYNQMP_CLK_DIVIDER_POWER_OF_TWO                BIT(1)
+#define ZYNQMP_CLK_DIVIDER_ALLOW_ZERO          BIT(2)
+#define ZYNQMP_CLK_DIVIDER_HIWORD_MASK         BIT(3)
+#define ZYNQMP_CLK_DIVIDER_ROUND_CLOSEST       BIT(4)
+#define ZYNQMP_CLK_DIVIDER_READ_ONLY           BIT(5)
+#define ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO         BIT(6)
+
 enum topology_type {
        TYPE_INVALID,
        TYPE_MUX,
diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c
index 3ab57d9..86cb785 100644
--- a/drivers/clk/zynqmp/divider.c
+++ b/drivers/clk/zynqmp/divider.c
@@ -320,7 +320,21 @@ struct clk_hw *zynqmp_clk_register_divider(const char *name,
        /* struct clk_divider assignments */
        div->is_frac = !!((nodes->flag & CLK_FRAC) |
                          (nodes->custom_type_flag & CUSTOM_FLAG_CLK_FRAC));
-       div->flags = nodes->type_flag;
+       div->flags = 0;
+       div->flags |= (nodes->type_flag & ZYNQMP_CLK_DIVIDER_ONE_BASED) ?
+                     CLK_DIVIDER_ONE_BASED : 0;
+       div->flags |= (nodes->type_flag & ZYNQMP_CLK_DIVIDER_POWER_OF_TWO) ?
+                     CLK_DIVIDER_POWER_OF_TWO : 0;
+       div->flags |= (nodes->type_flag & ZYNQMP_CLK_DIVIDER_ALLOW_ZERO) ?
+                     CLK_DIVIDER_ALLOW_ZERO : 0;
+       div->flags |= (nodes->type_flag & ZYNQMP_CLK_DIVIDER_POWER_OF_TWO) ?
+                     CLK_DIVIDER_HIWORD_MASK : 0;
+       div->flags |= (nodes->type_flag & ZYNQMP_CLK_DIVIDER_ROUND_CLOSEST) ?
+                     CLK_DIVIDER_ROUND_CLOSEST : 0;
+       div->flags |= (nodes->type_flag & ZYNQMP_CLK_DIVIDER_READ_ONLY) ?
+                     CLK_DIVIDER_READ_ONLY : 0;
+       div->flags |= (nodes->type_flag & ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO) ?
+                     CLK_DIVIDER_MAX_AT_ZERO : 0;
        div->hw.init = &init;
        div->clk_id = clk_id;
        div->div_type = nodes->type;
--
2.7.4

This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.

^ permalink raw reply related	[flat|nested] 10+ messages in thread

* Re: [PATCH v2 2/3] clk: zynqmp: Use firmware specific divider clock flags
  2020-07-22  6:55 ` [PATCH v2 2/3] clk: zynqmp: Use firmware specific divider " Amit Sunil Dhamne
@ 2020-07-22 13:27   ` Michael Tretter
  2020-07-23 23:59     ` Amit Sunil Dhamne
  0 siblings, 1 reply; 10+ messages in thread
From: Michael Tretter @ 2020-07-22 13:27 UTC (permalink / raw)
  To: Amit Sunil Dhamne
  Cc: mturquette, sboyd, sboyd, michal.simek, mark.rutland, linux-clk,
	rajanv, jollys, tejasp, linux-arm-kernel, linux-kernel,
	Rajan Vaja, Tejas Patel

On Tue, 21 Jul 2020 23:55:31 -0700, Amit Sunil Dhamne wrote:
> From: Rajan Vaja <rajan.vaja@xilinx.com>
> 
> Use ZynqMP specific divider clock flags instead of using CCF flags.
> 
> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
> Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
> Signed-off-by: Amit Sunil Dhamne <amit.sunil.dhamne@xilinx.com>
> ---
>  drivers/clk/zynqmp/clk-zynqmp.h |  9 +++++++++
>  drivers/clk/zynqmp/divider.c    | 16 +++++++++++++++-
>  2 files changed, 24 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/zynqmp/clk-zynqmp.h b/drivers/clk/zynqmp/clk-zynqmp.h
> index 3cb6149..ec33525 100644
> --- a/drivers/clk/zynqmp/clk-zynqmp.h
> +++ b/drivers/clk/zynqmp/clk-zynqmp.h
> @@ -32,6 +32,15 @@
>  /* do not gate, ever */
>  #define ZYNQMP_CLK_IS_CRITICAL         BIT(11)
> 
> +/* Type Flags for divider clock */
> +#define ZYNQMP_CLK_DIVIDER_ONE_BASED           BIT(0)
> +#define ZYNQMP_CLK_DIVIDER_POWER_OF_TWO                BIT(1)
> +#define ZYNQMP_CLK_DIVIDER_ALLOW_ZERO          BIT(2)
> +#define ZYNQMP_CLK_DIVIDER_HIWORD_MASK         BIT(3)
> +#define ZYNQMP_CLK_DIVIDER_ROUND_CLOSEST       BIT(4)
> +#define ZYNQMP_CLK_DIVIDER_READ_ONLY           BIT(5)
> +#define ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO         BIT(6)
> +
>  enum topology_type {
>         TYPE_INVALID,
>         TYPE_MUX,
> diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c
> index 3ab57d9..86cb785 100644
> --- a/drivers/clk/zynqmp/divider.c
> +++ b/drivers/clk/zynqmp/divider.c
> @@ -320,7 +320,21 @@ struct clk_hw *zynqmp_clk_register_divider(const char *name,
>         /* struct clk_divider assignments */
>         div->is_frac = !!((nodes->flag & CLK_FRAC) |
>                           (nodes->custom_type_flag & CUSTOM_FLAG_CLK_FRAC));
> -       div->flags = nodes->type_flag;
> +       div->flags = 0;
> +       div->flags |= (nodes->type_flag & ZYNQMP_CLK_DIVIDER_ONE_BASED) ?
> +                     CLK_DIVIDER_ONE_BASED : 0;
> +       div->flags |= (nodes->type_flag & ZYNQMP_CLK_DIVIDER_POWER_OF_TWO) ?
> +                     CLK_DIVIDER_POWER_OF_TWO : 0;
> +       div->flags |= (nodes->type_flag & ZYNQMP_CLK_DIVIDER_ALLOW_ZERO) ?
> +                     CLK_DIVIDER_ALLOW_ZERO : 0;
> +       div->flags |= (nodes->type_flag & ZYNQMP_CLK_DIVIDER_POWER_OF_TWO) ?
> +                     CLK_DIVIDER_HIWORD_MASK : 0;
> +       div->flags |= (nodes->type_flag & ZYNQMP_CLK_DIVIDER_ROUND_CLOSEST) ?
> +                     CLK_DIVIDER_ROUND_CLOSEST : 0;
> +       div->flags |= (nodes->type_flag & ZYNQMP_CLK_DIVIDER_READ_ONLY) ?
> +                     CLK_DIVIDER_READ_ONLY : 0;
> +       div->flags |= (nodes->type_flag & ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO) ?
> +                     CLK_DIVIDER_MAX_AT_ZERO : 0;

Add a helper function for converting the flags.

Michael

>         div->hw.init = &init;
>         div->clk_id = clk_id;
>         div->div_type = nodes->type;
> --
> 2.7.4
> 
> This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.
> 

^ permalink raw reply	[flat|nested] 10+ messages in thread

* RE: [PATCH v2 2/3] clk: zynqmp: Use firmware specific divider clock flags
  2020-07-22 13:27   ` Michael Tretter
@ 2020-07-23 23:59     ` Amit Sunil Dhamne
  0 siblings, 0 replies; 10+ messages in thread
From: Amit Sunil Dhamne @ 2020-07-23 23:59 UTC (permalink / raw)
  To: Michael Tretter
  Cc: mturquette, sboyd, sboyd, Michal Simek, mark.rutland, linux-clk,
	Rajan Vaja, Jolly Shah, Tejas Patel, linux-arm-kernel,
	linux-kernel, Rajan Vaja, Tejas Patel

Hi Michael,
Thanks for the review. Will push the Flag conversion to a new function.

Thanks,
Amit

> -----Original Message-----
> From: Michael Tretter <m.tretter@pengutronix.de>
> Sent: Wednesday, July 22, 2020 6:27 AM
> To: Amit Sunil Dhamne <amitsuni@xilinx.com>
> Cc: mturquette@baylibre.com; sboyd@codeaurora.org; sboyd@kernel.org;
> Michal Simek <michals@xilinx.com>; mark.rutland@arm.com; linux-
> clk@vger.kernel.org; Rajan Vaja <RAJANV@xilinx.com>; Jolly Shah
> <JOLLYS@xilinx.com>; Tejas Patel <TEJASP@xilinx.com>; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org; Rajan Vaja
> <RAJANV@xilinx.com>; Tejas Patel <TEJASP@xilinx.com>
> Subject: Re: [PATCH v2 2/3] clk: zynqmp: Use firmware specific divider clock
> flags
> 
> On Tue, 21 Jul 2020 23:55:31 -0700, Amit Sunil Dhamne wrote:
> > From: Rajan Vaja <rajan.vaja@xilinx.com>
> >
> > Use ZynqMP specific divider clock flags instead of using CCF flags.
> >
> > Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
> > Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
> > Signed-off-by: Amit Sunil Dhamne <amit.sunil.dhamne@xilinx.com>
> > ---
> >  drivers/clk/zynqmp/clk-zynqmp.h |  9 +++++++++
> >  drivers/clk/zynqmp/divider.c    | 16 +++++++++++++++-
> >  2 files changed, 24 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/zynqmp/clk-zynqmp.h
> > b/drivers/clk/zynqmp/clk-zynqmp.h index 3cb6149..ec33525 100644
> > --- a/drivers/clk/zynqmp/clk-zynqmp.h
> > +++ b/drivers/clk/zynqmp/clk-zynqmp.h
> > @@ -32,6 +32,15 @@
> >  /* do not gate, ever */
> >  #define ZYNQMP_CLK_IS_CRITICAL         BIT(11)
> >
> > +/* Type Flags for divider clock */
> > +#define ZYNQMP_CLK_DIVIDER_ONE_BASED           BIT(0)
> > +#define ZYNQMP_CLK_DIVIDER_POWER_OF_TWO                BIT(1)
> > +#define ZYNQMP_CLK_DIVIDER_ALLOW_ZERO          BIT(2)
> > +#define ZYNQMP_CLK_DIVIDER_HIWORD_MASK         BIT(3)
> > +#define ZYNQMP_CLK_DIVIDER_ROUND_CLOSEST       BIT(4)
> > +#define ZYNQMP_CLK_DIVIDER_READ_ONLY           BIT(5)
> > +#define ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO         BIT(6)
> > +
> >  enum topology_type {
> >         TYPE_INVALID,
> >         TYPE_MUX,
> > diff --git a/drivers/clk/zynqmp/divider.c
> > b/drivers/clk/zynqmp/divider.c index 3ab57d9..86cb785 100644
> > --- a/drivers/clk/zynqmp/divider.c
> > +++ b/drivers/clk/zynqmp/divider.c
> > @@ -320,7 +320,21 @@ struct clk_hw *zynqmp_clk_register_divider(const
> char *name,
> >         /* struct clk_divider assignments */
> >         div->is_frac = !!((nodes->flag & CLK_FRAC) |
> >                           (nodes->custom_type_flag & CUSTOM_FLAG_CLK_FRAC));
> > -       div->flags = nodes->type_flag;
> > +       div->flags = 0;
> > +       div->flags |= (nodes->type_flag &
> ZYNQMP_CLK_DIVIDER_ONE_BASED) ?
> > +                     CLK_DIVIDER_ONE_BASED : 0;
> > +       div->flags |= (nodes->type_flag &
> ZYNQMP_CLK_DIVIDER_POWER_OF_TWO) ?
> > +                     CLK_DIVIDER_POWER_OF_TWO : 0;
> > +       div->flags |= (nodes->type_flag &
> ZYNQMP_CLK_DIVIDER_ALLOW_ZERO) ?
> > +                     CLK_DIVIDER_ALLOW_ZERO : 0;
> > +       div->flags |= (nodes->type_flag &
> ZYNQMP_CLK_DIVIDER_POWER_OF_TWO) ?
> > +                     CLK_DIVIDER_HIWORD_MASK : 0;
> > +       div->flags |= (nodes->type_flag &
> ZYNQMP_CLK_DIVIDER_ROUND_CLOSEST) ?
> > +                     CLK_DIVIDER_ROUND_CLOSEST : 0;
> > +       div->flags |= (nodes->type_flag &
> ZYNQMP_CLK_DIVIDER_READ_ONLY) ?
> > +                     CLK_DIVIDER_READ_ONLY : 0;
> > +       div->flags |= (nodes->type_flag &
> ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO) ?
> > +                     CLK_DIVIDER_MAX_AT_ZERO : 0;
> 
> Add a helper function for converting the flags.
> 
> Michael
> 
> >         div->hw.init = &init;
> >         div->clk_id = clk_id;
> >         div->div_type = nodes->type;
> > --
> > 2.7.4
> >
> > This email and any attachments are intended for the sole use of the named
> recipient(s) and contain(s) confidential information that may be proprietary,
> privileged or copyrighted under applicable law. If you are not the intended
> recipient, do not read, copy, or forward this email message or any
> attachments. Delete this email message and any attachments immediately.
> >

^ permalink raw reply	[flat|nested] 10+ messages in thread

* [PATCH v2 3/3] clk: zynqmp: Use firmware specific mux clock flags
  2020-07-22  6:55 [PATCH v2 0/3] clk: zynqmp: Add firmware specific clock flags Amit Sunil Dhamne
  2020-07-22  6:55 ` [PATCH v2 1/3] clk: zynqmp: Use firmware specific common " Amit Sunil Dhamne
  2020-07-22  6:55 ` [PATCH v2 2/3] clk: zynqmp: Use firmware specific divider " Amit Sunil Dhamne
@ 2020-07-22  6:55 ` Amit Sunil Dhamne
  2020-07-22 13:28   ` Michael Tretter
  2020-07-23 22:35 ` [PATCH v2 0/3] clk: zynqmp: Add firmware specific " Stephen Boyd
  3 siblings, 1 reply; 10+ messages in thread
From: Amit Sunil Dhamne @ 2020-07-22  6:55 UTC (permalink / raw)
  To: mturquette, m.tretter, sboyd, sboyd, michal.simek, mark.rutland,
	linux-clk
  Cc: rajanv, jollys, tejasp, linux-arm-kernel, linux-kernel,
	Rajan Vaja, Tejas Patel, Amit Sunil Dhamne

From: Rajan Vaja <rajan.vaja@xilinx.com>

Use ZynqMP specific mux clock flags instead of using CCF flags.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Amit Sunil Dhamne <amit.sunil.dhamne@xilinx.com>
---
 drivers/clk/zynqmp/clk-mux-zynqmp.c | 14 +++++++++++++-
 drivers/clk/zynqmp/clk-zynqmp.h     |  8 ++++++++
 2 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/zynqmp/clk-mux-zynqmp.c b/drivers/clk/zynqmp/clk-mux-zynqmp.c
index 1dc17a0..10cf021 100644
--- a/drivers/clk/zynqmp/clk-mux-zynqmp.c
+++ b/drivers/clk/zynqmp/clk-mux-zynqmp.c
@@ -125,7 +125,19 @@ struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id,

        init.parent_names = parents;
        init.num_parents = num_parents;
-       mux->flags = nodes->type_flag;
+       mux->flags = 0;
+       mux->flags |= (nodes->type_flag & ZYNQMP_CLK_MUX_INDEX_ONE) ?
+                     CLK_MUX_INDEX_ONE : 0;
+       mux->flags |= (nodes->type_flag & ZYNQMP_CLK_MUX_INDEX_BIT) ?
+                     CLK_MUX_INDEX_BIT : 0;
+       mux->flags |= (nodes->type_flag & ZYNQMP_CLK_MUX_HIWORD_MASK) ?
+                     CLK_MUX_HIWORD_MASK : 0;
+       mux->flags |= (nodes->type_flag & ZYNQMP_CLK_MUX_READ_ONLY) ?
+                     CLK_MUX_READ_ONLY : 0;
+       mux->flags |= (nodes->type_flag & ZYNQMP_CLK_MUX_ROUND_CLOSEST) ?
+                     CLK_MUX_ROUND_CLOSEST : 0;
+       mux->flags |= (nodes->type_flag & ZYNQMP_CLK_MUX_BIG_ENDIAN) ?
+                     CLK_MUX_BIG_ENDIAN : 0;
        mux->hw.init = &init;
        mux->clk_id = clk_id;

diff --git a/drivers/clk/zynqmp/clk-zynqmp.h b/drivers/clk/zynqmp/clk-zynqmp.h
index ec33525..b1ac7e8 100644
--- a/drivers/clk/zynqmp/clk-zynqmp.h
+++ b/drivers/clk/zynqmp/clk-zynqmp.h
@@ -41,6 +41,14 @@
 #define ZYNQMP_CLK_DIVIDER_READ_ONLY           BIT(5)
 #define ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO         BIT(6)

+/* Type Flags for mux clock */
+#define ZYNQMP_CLK_MUX_INDEX_ONE               BIT(0)
+#define ZYNQMP_CLK_MUX_INDEX_BIT               BIT(1)
+#define ZYNQMP_CLK_MUX_HIWORD_MASK             BIT(2)
+#define ZYNQMP_CLK_MUX_READ_ONLY               BIT(3)
+#define ZYNQMP_CLK_MUX_ROUND_CLOSEST           BIT(4)
+#define ZYNQMP_CLK_MUX_BIG_ENDIAN              BIT(5)
+
 enum topology_type {
        TYPE_INVALID,
        TYPE_MUX,
--
2.7.4

This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.

^ permalink raw reply related	[flat|nested] 10+ messages in thread

* Re: [PATCH v2 3/3] clk: zynqmp: Use firmware specific mux clock flags
  2020-07-22  6:55 ` [PATCH v2 3/3] clk: zynqmp: Use firmware specific mux " Amit Sunil Dhamne
@ 2020-07-22 13:28   ` Michael Tretter
  0 siblings, 0 replies; 10+ messages in thread
From: Michael Tretter @ 2020-07-22 13:28 UTC (permalink / raw)
  To: Amit Sunil Dhamne
  Cc: mturquette, sboyd, sboyd, michal.simek, mark.rutland, linux-clk,
	rajanv, jollys, tejasp, linux-arm-kernel, linux-kernel,
	Rajan Vaja, Tejas Patel

On Tue, 21 Jul 2020 23:55:32 -0700, Amit Sunil Dhamne wrote:
> From: Rajan Vaja <rajan.vaja@xilinx.com>
> 
> Use ZynqMP specific mux clock flags instead of using CCF flags.
> 
> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
> Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
> Signed-off-by: Amit Sunil Dhamne <amit.sunil.dhamne@xilinx.com>
> ---
>  drivers/clk/zynqmp/clk-mux-zynqmp.c | 14 +++++++++++++-
>  drivers/clk/zynqmp/clk-zynqmp.h     |  8 ++++++++
>  2 files changed, 21 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/zynqmp/clk-mux-zynqmp.c b/drivers/clk/zynqmp/clk-mux-zynqmp.c
> index 1dc17a0..10cf021 100644
> --- a/drivers/clk/zynqmp/clk-mux-zynqmp.c
> +++ b/drivers/clk/zynqmp/clk-mux-zynqmp.c
> @@ -125,7 +125,19 @@ struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id,
> 
>         init.parent_names = parents;
>         init.num_parents = num_parents;
> -       mux->flags = nodes->type_flag;
> +       mux->flags = 0;
> +       mux->flags |= (nodes->type_flag & ZYNQMP_CLK_MUX_INDEX_ONE) ?
> +                     CLK_MUX_INDEX_ONE : 0;
> +       mux->flags |= (nodes->type_flag & ZYNQMP_CLK_MUX_INDEX_BIT) ?
> +                     CLK_MUX_INDEX_BIT : 0;
> +       mux->flags |= (nodes->type_flag & ZYNQMP_CLK_MUX_HIWORD_MASK) ?
> +                     CLK_MUX_HIWORD_MASK : 0;
> +       mux->flags |= (nodes->type_flag & ZYNQMP_CLK_MUX_READ_ONLY) ?
> +                     CLK_MUX_READ_ONLY : 0;
> +       mux->flags |= (nodes->type_flag & ZYNQMP_CLK_MUX_ROUND_CLOSEST) ?
> +                     CLK_MUX_ROUND_CLOSEST : 0;
> +       mux->flags |= (nodes->type_flag & ZYNQMP_CLK_MUX_BIG_ENDIAN) ?
> +                     CLK_MUX_BIG_ENDIAN : 0;

Add a helper function for converting the flags.

Michael

>         mux->hw.init = &init;
>         mux->clk_id = clk_id;
> 
> diff --git a/drivers/clk/zynqmp/clk-zynqmp.h b/drivers/clk/zynqmp/clk-zynqmp.h
> index ec33525..b1ac7e8 100644
> --- a/drivers/clk/zynqmp/clk-zynqmp.h
> +++ b/drivers/clk/zynqmp/clk-zynqmp.h
> @@ -41,6 +41,14 @@
>  #define ZYNQMP_CLK_DIVIDER_READ_ONLY           BIT(5)
>  #define ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO         BIT(6)
> 
> +/* Type Flags for mux clock */
> +#define ZYNQMP_CLK_MUX_INDEX_ONE               BIT(0)
> +#define ZYNQMP_CLK_MUX_INDEX_BIT               BIT(1)
> +#define ZYNQMP_CLK_MUX_HIWORD_MASK             BIT(2)
> +#define ZYNQMP_CLK_MUX_READ_ONLY               BIT(3)
> +#define ZYNQMP_CLK_MUX_ROUND_CLOSEST           BIT(4)
> +#define ZYNQMP_CLK_MUX_BIG_ENDIAN              BIT(5)
> +
>  enum topology_type {
>         TYPE_INVALID,
>         TYPE_MUX,
> --
> 2.7.4
> 
> This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.
> 

-- 
Pengutronix e.K.                           | Michael Tretter             |
Steuerwalder Str. 21                       | https://www.pengutronix.de/ |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

^ permalink raw reply	[flat|nested] 10+ messages in thread

* Re: [PATCH v2 0/3] clk: zynqmp: Add firmware specific clock flags
  2020-07-22  6:55 [PATCH v2 0/3] clk: zynqmp: Add firmware specific clock flags Amit Sunil Dhamne
                   ` (2 preceding siblings ...)
  2020-07-22  6:55 ` [PATCH v2 3/3] clk: zynqmp: Use firmware specific mux " Amit Sunil Dhamne
@ 2020-07-23 22:35 ` Stephen Boyd
  3 siblings, 0 replies; 10+ messages in thread
From: Stephen Boyd @ 2020-07-23 22:35 UTC (permalink / raw)
  To: Amit Sunil Dhamne, linux-clk, m.tretter, mark.rutland,
	michal.simek, mturquette, sboyd
  Cc: rajanv, jollys, tejasp, linux-arm-kernel, linux-kernel,
	Amit Sunil Dhamne

Quoting Amit Sunil Dhamne (2020-07-21 23:55:29)
> This series adds supports for firmware specific flags. These include
> - Common Flags
> - Divider Flags
> - Mux Flags
> 
> The intent is to remove firmware's dependency on CCF flag values by having
> firmware specific flags with independent values.
> 
> Currently firmware is maintaining CCF specific flags and provides to
> CCF as it is. But CCF flag numbers may change and that shouldn't mean
> that the firmware needs to change. The firmware should have its own
> 'flag number space' that is distinct from the common clk framework's
> 'flag number space'. So use firmware specific clock flags in ZynqMP
> clock driver instead of CCF flags.
> 

Thanks for doing this work. Please resend with fixes.

^ permalink raw reply	[flat|nested] 10+ messages in thread

end of thread, other threads:[~2020-07-23 23:59 UTC | newest]

Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-07-22  6:55 [PATCH v2 0/3] clk: zynqmp: Add firmware specific clock flags Amit Sunil Dhamne
2020-07-22  6:55 ` [PATCH v2 1/3] clk: zynqmp: Use firmware specific common " Amit Sunil Dhamne
2020-07-22 13:22   ` Michael Tretter
2020-07-23 23:46     ` Amit Sunil Dhamne
2020-07-22  6:55 ` [PATCH v2 2/3] clk: zynqmp: Use firmware specific divider " Amit Sunil Dhamne
2020-07-22 13:27   ` Michael Tretter
2020-07-23 23:59     ` Amit Sunil Dhamne
2020-07-22  6:55 ` [PATCH v2 3/3] clk: zynqmp: Use firmware specific mux " Amit Sunil Dhamne
2020-07-22 13:28   ` Michael Tretter
2020-07-23 22:35 ` [PATCH v2 0/3] clk: zynqmp: Add firmware specific " Stephen Boyd

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