* [PATCH] clk: meson: meson8b: Don't use MPLL1 as parent of vclk_in_sel
@ 2021-05-24 10:45 Martin Blumenstingl
2021-05-24 10:57 ` Jerome Brunet
0 siblings, 1 reply; 3+ messages in thread
From: Martin Blumenstingl @ 2021-05-24 10:45 UTC (permalink / raw)
To: jbrunet, linux-amlogic
Cc: narmstrong, mturquette, sboyd, khilman, linux-clk,
linux-arm-kernel, linux-kernel, Martin Blumenstingl
MPLL1 is needed for audio output. Drop it from the vclk_in_sel parent
list so we only use the (mutable) vid_pll_final_div tree or one of the
(fixed) FCLK_DIV{3,4,5} clocks.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
drivers/clk/meson/meson8b.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index a844d35b553a..f8bd211db720 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -1154,6 +1154,10 @@ static struct clk_regmap meson8b_vid_pll_final_div = {
},
};
+/*
+ * parent 0x6 is meson8b_mpll1 but we don't use it here because it's reserved
+ * for the audio outputs.
+ */
static const struct clk_hw *meson8b_vclk_mux_parent_hws[] = {
&meson8b_vid_pll_final_div.hw,
&meson8b_fclk_div4.hw,
@@ -1161,7 +1165,6 @@ static const struct clk_hw *meson8b_vclk_mux_parent_hws[] = {
&meson8b_fclk_div5.hw,
&meson8b_vid_pll_final_div.hw,
&meson8b_fclk_div7.hw,
- &meson8b_mpll1.hw,
};
static struct clk_regmap meson8b_vclk_in_sel = {
--
2.31.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] clk: meson: meson8b: Don't use MPLL1 as parent of vclk_in_sel
2021-05-24 10:45 [PATCH] clk: meson: meson8b: Don't use MPLL1 as parent of vclk_in_sel Martin Blumenstingl
@ 2021-05-24 10:57 ` Jerome Brunet
2021-05-24 11:49 ` Martin Blumenstingl
0 siblings, 1 reply; 3+ messages in thread
From: Jerome Brunet @ 2021-05-24 10:57 UTC (permalink / raw)
To: Martin Blumenstingl, linux-amlogic
Cc: narmstrong, mturquette, sboyd, khilman, linux-clk,
linux-arm-kernel, linux-kernel
On Mon 24 May 2021 at 12:45, Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote:
> MPLL1 is needed for audio output. Drop it from the vclk_in_sel parent
> list so we only use the (mutable) vid_pll_final_div tree or one of the
> (fixed) FCLK_DIV{3,4,5} clocks.
Are the fixed ones actually needed ?
If the consumer actually lives on the vid_pll only, I'd prefer if you
could add CLK_SET_RATE_NOREPARENT and assign the proper parent in DT with
`assigned-clock-parents`
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
> drivers/clk/meson/meson8b.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
> index a844d35b553a..f8bd211db720 100644
> --- a/drivers/clk/meson/meson8b.c
> +++ b/drivers/clk/meson/meson8b.c
> @@ -1154,6 +1154,10 @@ static struct clk_regmap meson8b_vid_pll_final_div = {
> },
> };
>
> +/*
> + * parent 0x6 is meson8b_mpll1 but we don't use it here because it's reserved
> + * for the audio outputs.
> + */
> static const struct clk_hw *meson8b_vclk_mux_parent_hws[] = {
> &meson8b_vid_pll_final_div.hw,
> &meson8b_fclk_div4.hw,
> @@ -1161,7 +1165,6 @@ static const struct clk_hw *meson8b_vclk_mux_parent_hws[] = {
> &meson8b_fclk_div5.hw,
> &meson8b_vid_pll_final_div.hw,
> &meson8b_fclk_div7.hw,
> - &meson8b_mpll1.hw,
> };
>
> static struct clk_regmap meson8b_vclk_in_sel = {
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] clk: meson: meson8b: Don't use MPLL1 as parent of vclk_in_sel
2021-05-24 10:57 ` Jerome Brunet
@ 2021-05-24 11:49 ` Martin Blumenstingl
0 siblings, 0 replies; 3+ messages in thread
From: Martin Blumenstingl @ 2021-05-24 11:49 UTC (permalink / raw)
To: Jerome Brunet
Cc: linux-amlogic, Neil Armstrong, mturquette, sboyd, khilman,
linux-clk, linux-arm-kernel, linux-kernel
Hi Jerome,
On Mon, May 24, 2021 at 12:57 PM Jerome Brunet <jbrunet@baylibre.com> wrote:
>
>
> On Mon 24 May 2021 at 12:45, Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote:
>
> > MPLL1 is needed for audio output. Drop it from the vclk_in_sel parent
> > list so we only use the (mutable) vid_pll_final_div tree or one of the
> > (fixed) FCLK_DIV{3,4,5} clocks.
>
> Are the fixed ones actually needed ?
>
> If the consumer actually lives on the vid_pll only, I'd prefer if you
> could add CLK_SET_RATE_NOREPARENT and assign the proper parent in DT with
> `assigned-clock-parents`
you're right, only the vid_pll_final_div tree is used
I just tested it with assigned-clock-parents and
CLK_SET_RATE_NO_REPARENT and it's working fine. I'll send a v2 later
today
Thanks for this suggestion!
Best regards,
Martin
^ permalink raw reply [flat|nested] 3+ messages in thread
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2021-05-24 10:45 [PATCH] clk: meson: meson8b: Don't use MPLL1 as parent of vclk_in_sel Martin Blumenstingl
2021-05-24 10:57 ` Jerome Brunet
2021-05-24 11:49 ` Martin Blumenstingl
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