Clocking accuracy

* Clocking accuracy
@ 2021-08-13  7:03 Shubhrajyoti Datta
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From: Shubhrajyoti Datta @ 2021-08-13  7:03 UTC (permalink / raw)
  To: linux-clk; +Cc: Shubhrajyoti Datta

Hi ,

I have a clock tree as below.

D1 -> D0 -> output

here there are two divisors and output is (input/D0)/D1.

here  if the output of D1 is

Parent 0 0 0 24258309116 0 0 50000
D1_div 0 0 0 2695367679 0 0 50000
clk_out1 0 0 0 269536768 0 0 50000

D1 is 9  and D0 10

Now when i ask for  output as 148M

the D1 divisor is chosen as 18 and the output is  149.742648

i have set the set rate parent  here.

however if the divisors chosen would have been 1 and 164
the value would have been 147916519.

Is there a way to achieve that.

Thanks and Regards,
Shubhrajyoti

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