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* [PATCH v4 0/2] ARM: Add Rockchip rk3288w support
@ 2020-06-02  8:06 Mylène Josserand
  2020-06-02  8:06 ` [PATCH v4 1/2] clk: rockchip: rk3288: Handle clock tree for rk3288w Mylène Josserand
                   ` (2 more replies)
  0 siblings, 3 replies; 13+ messages in thread
From: Mylène Josserand @ 2020-06-02  8:06 UTC (permalink / raw)
  To: mturquette, sboyd, heiko, robh+dt
  Cc: linux-clk, linux-arm-kernel, linux-rockchip, linux-kernel,
	devicetree, mylene.josserand, kernel

Hello everyone,

Context
-------

Here is my V4 of my patches that add the support for the Rockchip
RK3288w which is a revision of the RK3288. It is mostly the same SOC
except for, at least, one clock tree which is different.
This difference is only known by looking at the BSP kernel [1].

Currently, the mainline kernel will not hang on rk3288w but it is
probably by "chance" because we got an issue on a lower kernel version.

According to Rockchip's U-Boot [2], the rk3288w can be detected using
the HDMI revision number (= 0x1A) in this version of the SOC.

Changelog
---------

This V4 is pretty much the same than the V3. Added the dt-bindings
documentation in clock-controller dt-bindings and fixed some typos
according to Heiko's reviews.

Changes since v3:
   - Updated clock-controller's dt-bindings
   - Fixed indentation

Best regards,
Mylène Josserand

[1] https://github.com/rockchip-linux/kernel/blob/develop-4.4/drivers/clk/rockchip/clk-rk3288.c#L960..L964
[2] https://github.com/rockchip-linux/u-boot/blob/next-dev/arch/arm/mach-rockchip/rk3288/rk3288.c#L378..L388

Mylène Josserand (2):
  clk: rockchip: rk3288: Handle clock tree for rk3288w
  dt-bindings: clocks: rk3288: add possible rk3288w

 .../bindings/clock/rockchip,rk3288-cru.txt    |  8 +++++++-
 drivers/clk/rockchip/clk-rk3288.c             | 20 +++++++++++++++++--
 2 files changed, 25 insertions(+), 3 deletions(-)

-- 
2.26.2


^ permalink raw reply	[flat|nested] 13+ messages in thread

* [PATCH v4 1/2] clk: rockchip: rk3288: Handle clock tree for rk3288w
  2020-06-02  8:06 [PATCH v4 0/2] ARM: Add Rockchip rk3288w support Mylène Josserand
@ 2020-06-02  8:06 ` Mylène Josserand
  2020-06-29 19:11   ` Jagan Teki
  2020-06-02  8:06 ` [PATCH v4 2/2] dt-bindings: clocks: rk3288: add rk3288w compatible Mylène Josserand
  2020-06-17  8:58 ` [PATCH v4 0/2] ARM: Add Rockchip rk3288w support Heiko Stuebner
  2 siblings, 1 reply; 13+ messages in thread
From: Mylène Josserand @ 2020-06-02  8:06 UTC (permalink / raw)
  To: mturquette, sboyd, heiko, robh+dt
  Cc: linux-clk, linux-arm-kernel, linux-rockchip, linux-kernel,
	devicetree, mylene.josserand, kernel

The revision rk3288w has a different clock tree about "hclk_vio"
clock, according to the BSP kernel code.

This patch handles this difference by detecting which device-tree
we are using. If it is a "rockchip,rk3288-cru", let's register
the clock tree as it was before. If the device-tree node is
"rockchip,rk3288w-cru", we will apply the difference with this
version of this SoC.

Noticed that this new device-tree compatible must be handled in
bootloader such as u-boot.

Signed-off-by: Mylène Josserand <mylene.josserand@collabora.com>
---
 drivers/clk/rockchip/clk-rk3288.c | 20 ++++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index cc2a177bbdbf..204976e2d0cb 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -425,8 +425,6 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
 	COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
 			RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS,
 			RK3288_CLKGATE_CON(3), 0, GFLAGS),
-	DIV(0, "hclk_vio", "aclk_vio0", 0,
-			RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
 	COMPOSITE(0, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
 			RK3288_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,
 			RK3288_CLKGATE_CON(3), 2, GFLAGS),
@@ -819,6 +817,16 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
 	INVERTER(0, "pclk_isp", "pclk_isp_in", RK3288_CLKSEL_CON(29), 3, IFLAGS),
 };
 
+static struct rockchip_clk_branch rk3288w_hclkvio_branch[] __initdata = {
+	DIV(0, "hclk_vio", "aclk_vio1", 0,
+			RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
+};
+
+static struct rockchip_clk_branch rk3288_hclkvio_branch[] __initdata = {
+	DIV(0, "hclk_vio", "aclk_vio0", 0,
+			RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
+};
+
 static const char *const rk3288_critical_clocks[] __initconst = {
 	"aclk_cpu",
 	"aclk_peri",
@@ -936,6 +944,14 @@ static void __init rk3288_clk_init(struct device_node *np)
 				   RK3288_GRF_SOC_STATUS1);
 	rockchip_clk_register_branches(ctx, rk3288_clk_branches,
 				  ARRAY_SIZE(rk3288_clk_branches));
+
+	if (of_device_is_compatible(np, "rockchip,rk3288w-cru"))
+		rockchip_clk_register_branches(ctx, rk3288w_hclkvio_branch,
+					       ARRAY_SIZE(rk3288w_hclkvio_branch));
+	else
+		rockchip_clk_register_branches(ctx, rk3288_hclkvio_branch,
+					       ARRAY_SIZE(rk3288_hclkvio_branch));
+
 	rockchip_clk_protect_critical(rk3288_critical_clocks,
 				      ARRAY_SIZE(rk3288_critical_clocks));
 
-- 
2.26.2


^ permalink raw reply	[flat|nested] 13+ messages in thread

* [PATCH v4 2/2] dt-bindings: clocks: rk3288: add rk3288w compatible
  2020-06-02  8:06 [PATCH v4 0/2] ARM: Add Rockchip rk3288w support Mylène Josserand
  2020-06-02  8:06 ` [PATCH v4 1/2] clk: rockchip: rk3288: Handle clock tree for rk3288w Mylène Josserand
@ 2020-06-02  8:06 ` Mylène Josserand
  2020-06-09 22:47   ` Rob Herring
  2020-06-17  8:58 ` [PATCH v4 0/2] ARM: Add Rockchip rk3288w support Heiko Stuebner
  2 siblings, 1 reply; 13+ messages in thread
From: Mylène Josserand @ 2020-06-02  8:06 UTC (permalink / raw)
  To: mturquette, sboyd, heiko, robh+dt
  Cc: linux-clk, linux-arm-kernel, linux-rockchip, linux-kernel,
	devicetree, mylene.josserand, kernel

Add the possible compatible "rockchip,rk3288w-cru" that handles
the difference between the rk3288 and the new revision rk3288w.

This compatible will be added by bootloaders.

Signed-off-by: Mylène Josserand <mylene.josserand@collabora.com>
---
 .../devicetree/bindings/clock/rockchip,rk3288-cru.txt     | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.txt
index 8cb47c39ba53..bf3a9ec19241 100644
--- a/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.txt
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.txt
@@ -4,9 +4,15 @@ The RK3288 clock controller generates and supplies clock to various
 controllers within the SoC and also implements a reset controller for SoC
 peripherals.
 
+A revision of this SoC is available: rk3288w. The clock tree is a bit
+different so another dt-compatible is available. Noticed that it is only
+setting the difference but there is no automatic revision detection. This
+should be performed by bootloaders.
+
 Required Properties:
 
-- compatible: should be "rockchip,rk3288-cru"
+- compatible: should be "rockchip,rk3288-cru" or "rockchip,rk3288w-cru" in
+  case of this revision of Rockchip rk3288.
 - reg: physical base address of the controller and length of memory mapped
   region.
 - #clock-cells: should be 1.
-- 
2.26.2


^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v4 2/2] dt-bindings: clocks: rk3288: add rk3288w compatible
  2020-06-02  8:06 ` [PATCH v4 2/2] dt-bindings: clocks: rk3288: add rk3288w compatible Mylène Josserand
@ 2020-06-09 22:47   ` Rob Herring
  0 siblings, 0 replies; 13+ messages in thread
From: Rob Herring @ 2020-06-09 22:47 UTC (permalink / raw)
  To: Mylène Josserand
  Cc: devicetree, linux-rockchip, linux-clk, kernel, heiko, mturquette,
	robh+dt, linux-arm-kernel, sboyd, linux-kernel

On Tue, 02 Jun 2020 10:06:44 +0200, Mylène Josserand wrote:
> Add the possible compatible "rockchip,rk3288w-cru" that handles
> the difference between the rk3288 and the new revision rk3288w.
> 
> This compatible will be added by bootloaders.
> 
> Signed-off-by: Mylène Josserand <mylene.josserand@collabora.com>
> ---
>  .../devicetree/bindings/clock/rockchip,rk3288-cru.txt     | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 

Acked-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v4 0/2] ARM: Add Rockchip rk3288w support
  2020-06-02  8:06 [PATCH v4 0/2] ARM: Add Rockchip rk3288w support Mylène Josserand
  2020-06-02  8:06 ` [PATCH v4 1/2] clk: rockchip: rk3288: Handle clock tree for rk3288w Mylène Josserand
  2020-06-02  8:06 ` [PATCH v4 2/2] dt-bindings: clocks: rk3288: add rk3288w compatible Mylène Josserand
@ 2020-06-17  8:58 ` Heiko Stuebner
  2020-06-29  7:59   ` Mylene Josserand
  2 siblings, 1 reply; 13+ messages in thread
From: Heiko Stuebner @ 2020-06-17  8:58 UTC (permalink / raw)
  To: robh+dt, Mylène Josserand, sboyd, mturquette
  Cc: Heiko Stuebner, linux-clk, kernel, linux-arm-kernel,
	linux-rockchip, linux-kernel, devicetree

On Tue, 2 Jun 2020 10:06:42 +0200, Mylène Josserand wrote:
> Context
> -------
> 
> Here is my V4 of my patches that add the support for the Rockchip
> RK3288w which is a revision of the RK3288. It is mostly the same SOC
> except for, at least, one clock tree which is different.
> This difference is only known by looking at the BSP kernel [1].
> 
> [...]

Applied, thanks!

[1/2] clk: rockchip: Handle clock tree for rk3288w variant
      commit: 1627f683636df70fb25358b0a7b39a24e8fce5bf
[2/2] dt-bindings: clocks: add rk3288w variant compatible
      commit: 00bd404144241155653bb0d0c15be51e4e6983aa

Best regards,
-- 
Heiko Stuebner <heiko@sntech.de>

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v4 0/2] ARM: Add Rockchip rk3288w support
  2020-06-17  8:58 ` [PATCH v4 0/2] ARM: Add Rockchip rk3288w support Heiko Stuebner
@ 2020-06-29  7:59   ` Mylene Josserand
  0 siblings, 0 replies; 13+ messages in thread
From: Mylene Josserand @ 2020-06-29  7:59 UTC (permalink / raw)
  To: Heiko Stuebner, robh+dt, sboyd, mturquette
  Cc: linux-clk, kernel, linux-arm-kernel, linux-rockchip,
	linux-kernel, devicetree

Hello Heiko,

On 6/17/20 10:58 AM, Heiko Stuebner wrote:
> On Tue, 2 Jun 2020 10:06:42 +0200, Mylène Josserand wrote:
>> Context
>> -------
>>
>> Here is my V4 of my patches that add the support for the Rockchip
>> RK3288w which is a revision of the RK3288. It is mostly the same SOC
>> except for, at least, one clock tree which is different.
>> This difference is only known by looking at the BSP kernel [1].
>>
>> [...]
> 
> Applied, thanks!

Thank you!

Best regards,
Mylène

> 
> [1/2] clk: rockchip: Handle clock tree for rk3288w variant
>        commit: 1627f683636df70fb25358b0a7b39a24e8fce5bf
> [2/2] dt-bindings: clocks: add rk3288w variant compatible
>        commit: 00bd404144241155653bb0d0c15be51e4e6983aa
> 
> Best regards,
> 


^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v4 1/2] clk: rockchip: rk3288: Handle clock tree for rk3288w
  2020-06-02  8:06 ` [PATCH v4 1/2] clk: rockchip: rk3288: Handle clock tree for rk3288w Mylène Josserand
@ 2020-06-29 19:11   ` Jagan Teki
  2020-07-03 14:11     ` Heiko Stuebner
  0 siblings, 1 reply; 13+ messages in thread
From: Jagan Teki @ 2020-06-29 19:11 UTC (permalink / raw)
  To: Mylène Josserand
  Cc: Michael Turquette, Stephen Boyd, Heiko Stübner, Rob Herring,
	devicetree, linux-kernel, open list:ARM/Rockchip SoC...,
	kernel, linux-clk, linux-arm-kernel

On Tue, Jun 2, 2020 at 1:37 PM Mylène Josserand
<mylene.josserand@collabora.com> wrote:
>
> The revision rk3288w has a different clock tree about "hclk_vio"
> clock, according to the BSP kernel code.
>
> This patch handles this difference by detecting which device-tree
> we are using. If it is a "rockchip,rk3288-cru", let's register
> the clock tree as it was before. If the device-tree node is
> "rockchip,rk3288w-cru", we will apply the difference with this
> version of this SoC.
>
> Noticed that this new device-tree compatible must be handled in
> bootloader such as u-boot.
>
> Signed-off-by: Mylène Josserand <mylene.josserand@collabora.com>
> ---
>  drivers/clk/rockchip/clk-rk3288.c | 20 ++++++++++++++++++--
>  1 file changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
> index cc2a177bbdbf..204976e2d0cb 100644
> --- a/drivers/clk/rockchip/clk-rk3288.c
> +++ b/drivers/clk/rockchip/clk-rk3288.c
> @@ -425,8 +425,6 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
>         COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
>                         RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS,
>                         RK3288_CLKGATE_CON(3), 0, GFLAGS),
> -       DIV(0, "hclk_vio", "aclk_vio0", 0,
> -                       RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
>         COMPOSITE(0, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
>                         RK3288_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,
>                         RK3288_CLKGATE_CON(3), 2, GFLAGS),
> @@ -819,6 +817,16 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
>         INVERTER(0, "pclk_isp", "pclk_isp_in", RK3288_CLKSEL_CON(29), 3, IFLAGS),
>  };
>
> +static struct rockchip_clk_branch rk3288w_hclkvio_branch[] __initdata = {
> +       DIV(0, "hclk_vio", "aclk_vio1", 0,
> +                       RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
> +};
> +
> +static struct rockchip_clk_branch rk3288_hclkvio_branch[] __initdata = {
> +       DIV(0, "hclk_vio", "aclk_vio0", 0,
> +                       RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
> +};
> +
>  static const char *const rk3288_critical_clocks[] __initconst = {
>         "aclk_cpu",
>         "aclk_peri",
> @@ -936,6 +944,14 @@ static void __init rk3288_clk_init(struct device_node *np)
>                                    RK3288_GRF_SOC_STATUS1);
>         rockchip_clk_register_branches(ctx, rk3288_clk_branches,
>                                   ARRAY_SIZE(rk3288_clk_branches));
> +
> +       if (of_device_is_compatible(np, "rockchip,rk3288w-cru"))
> +               rockchip_clk_register_branches(ctx, rk3288w_hclkvio_branch,
> +                                              ARRAY_SIZE(rk3288w_hclkvio_branch));
> +       else
> +               rockchip_clk_register_branches(ctx, rk3288_hclkvio_branch,
> +                                              ARRAY_SIZE(rk3288_hclkvio_branch));
> +

Sorry for the late query on this. I am a bit unclear about this
compatible change, does Linux expect to replace rockchip,rk3288-cru
with rockchip,rk3288w-cru in bootloader if the chip is RK3288w? or
append the existing cru compatible node with rockchip,rk3288w-cru?
because replace new cru node make clock never probe since the
CLK_OF_DECLARE checking rockchip,rk3288-cru

Jagan.

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v4 1/2] clk: rockchip: rk3288: Handle clock tree for rk3288w
  2020-06-29 19:11   ` Jagan Teki
@ 2020-07-03 14:11     ` Heiko Stuebner
  2020-07-03 14:23       ` Jagan Teki
  2020-07-03 15:02       ` Ezequiel Garcia
  0 siblings, 2 replies; 13+ messages in thread
From: Heiko Stuebner @ 2020-07-03 14:11 UTC (permalink / raw)
  To: Jagan Teki
  Cc: Mylène Josserand, Michael Turquette, Stephen Boyd,
	Rob Herring, devicetree, linux-kernel,
	open list:ARM/Rockchip SoC...,
	kernel, linux-clk, linux-arm-kernel

Hi Jagan,

Am Montag, 29. Juni 2020, 21:11:03 CEST schrieb Jagan Teki:
> On Tue, Jun 2, 2020 at 1:37 PM Mylène Josserand
> <mylene.josserand@collabora.com> wrote:
> >
> > The revision rk3288w has a different clock tree about "hclk_vio"
> > clock, according to the BSP kernel code.
> >
> > This patch handles this difference by detecting which device-tree
> > we are using. If it is a "rockchip,rk3288-cru", let's register
> > the clock tree as it was before. If the device-tree node is
> > "rockchip,rk3288w-cru", we will apply the difference with this
> > version of this SoC.
> >
> > Noticed that this new device-tree compatible must be handled in
> > bootloader such as u-boot.
> >
> > Signed-off-by: Mylène Josserand <mylene.josserand@collabora.com>
> > ---
> >  drivers/clk/rockchip/clk-rk3288.c | 20 ++++++++++++++++++--
> >  1 file changed, 18 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
> > index cc2a177bbdbf..204976e2d0cb 100644
> > --- a/drivers/clk/rockchip/clk-rk3288.c
> > +++ b/drivers/clk/rockchip/clk-rk3288.c
> > @@ -425,8 +425,6 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
> >         COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
> >                         RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS,
> >                         RK3288_CLKGATE_CON(3), 0, GFLAGS),
> > -       DIV(0, "hclk_vio", "aclk_vio0", 0,
> > -                       RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
> >         COMPOSITE(0, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
> >                         RK3288_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,
> >                         RK3288_CLKGATE_CON(3), 2, GFLAGS),
> > @@ -819,6 +817,16 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
> >         INVERTER(0, "pclk_isp", "pclk_isp_in", RK3288_CLKSEL_CON(29), 3, IFLAGS),
> >  };
> >
> > +static struct rockchip_clk_branch rk3288w_hclkvio_branch[] __initdata = {
> > +       DIV(0, "hclk_vio", "aclk_vio1", 0,
> > +                       RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
> > +};
> > +
> > +static struct rockchip_clk_branch rk3288_hclkvio_branch[] __initdata = {
> > +       DIV(0, "hclk_vio", "aclk_vio0", 0,
> > +                       RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
> > +};
> > +
> >  static const char *const rk3288_critical_clocks[] __initconst = {
> >         "aclk_cpu",
> >         "aclk_peri",
> > @@ -936,6 +944,14 @@ static void __init rk3288_clk_init(struct device_node *np)
> >                                    RK3288_GRF_SOC_STATUS1);
> >         rockchip_clk_register_branches(ctx, rk3288_clk_branches,
> >                                   ARRAY_SIZE(rk3288_clk_branches));
> > +
> > +       if (of_device_is_compatible(np, "rockchip,rk3288w-cru"))
> > +               rockchip_clk_register_branches(ctx, rk3288w_hclkvio_branch,
> > +                                              ARRAY_SIZE(rk3288w_hclkvio_branch));
> > +       else
> > +               rockchip_clk_register_branches(ctx, rk3288_hclkvio_branch,
> > +                                              ARRAY_SIZE(rk3288_hclkvio_branch));
> > +
> 
> Sorry for the late query on this. I am a bit unclear about this
> compatible change, does Linux expect to replace rockchip,rk3288-cru
> with rockchip,rk3288w-cru in bootloader if the chip is RK3288w? or
> append the existing cru compatible node with rockchip,rk3288w-cru?
> because replace new cru node make clock never probe since the
> CLK_OF_DECLARE checking rockchip,rk3288-cru

I guess right now we'd expect "rockchip,rk3288w-cru", "rockchip,rk3288-cru",

Thinking again about this, I'm wondering if we should switch to having
only one per variant ... like on the two rk3188 variants,
so declaring separate rk3288-cru and rk3288w-cru of-clks with shared
common code.




^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v4 1/2] clk: rockchip: rk3288: Handle clock tree for rk3288w
  2020-07-03 14:11     ` Heiko Stuebner
@ 2020-07-03 14:23       ` Jagan Teki
  2020-07-03 14:48         ` Heiko Stuebner
  2020-07-03 15:02       ` Ezequiel Garcia
  1 sibling, 1 reply; 13+ messages in thread
From: Jagan Teki @ 2020-07-03 14:23 UTC (permalink / raw)
  To: Heiko Stuebner
  Cc: Mylène Josserand, Michael Turquette, Stephen Boyd,
	Rob Herring, devicetree, linux-kernel,
	open list:ARM/Rockchip SoC...,
	kernel, linux-clk, linux-arm-kernel

On Fri, Jul 3, 2020 at 7:41 PM Heiko Stuebner <heiko@sntech.de> wrote:
>
> Hi Jagan,
>
> Am Montag, 29. Juni 2020, 21:11:03 CEST schrieb Jagan Teki:
> > On Tue, Jun 2, 2020 at 1:37 PM Mylène Josserand
> > <mylene.josserand@collabora.com> wrote:
> > >
> > > The revision rk3288w has a different clock tree about "hclk_vio"
> > > clock, according to the BSP kernel code.
> > >
> > > This patch handles this difference by detecting which device-tree
> > > we are using. If it is a "rockchip,rk3288-cru", let's register
> > > the clock tree as it was before. If the device-tree node is
> > > "rockchip,rk3288w-cru", we will apply the difference with this
> > > version of this SoC.
> > >
> > > Noticed that this new device-tree compatible must be handled in
> > > bootloader such as u-boot.
> > >
> > > Signed-off-by: Mylène Josserand <mylene.josserand@collabora.com>
> > > ---
> > >  drivers/clk/rockchip/clk-rk3288.c | 20 ++++++++++++++++++--
> > >  1 file changed, 18 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
> > > index cc2a177bbdbf..204976e2d0cb 100644
> > > --- a/drivers/clk/rockchip/clk-rk3288.c
> > > +++ b/drivers/clk/rockchip/clk-rk3288.c
> > > @@ -425,8 +425,6 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
> > >         COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
> > >                         RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS,
> > >                         RK3288_CLKGATE_CON(3), 0, GFLAGS),
> > > -       DIV(0, "hclk_vio", "aclk_vio0", 0,
> > > -                       RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
> > >         COMPOSITE(0, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
> > >                         RK3288_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,
> > >                         RK3288_CLKGATE_CON(3), 2, GFLAGS),
> > > @@ -819,6 +817,16 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
> > >         INVERTER(0, "pclk_isp", "pclk_isp_in", RK3288_CLKSEL_CON(29), 3, IFLAGS),
> > >  };
> > >
> > > +static struct rockchip_clk_branch rk3288w_hclkvio_branch[] __initdata = {
> > > +       DIV(0, "hclk_vio", "aclk_vio1", 0,
> > > +                       RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
> > > +};
> > > +
> > > +static struct rockchip_clk_branch rk3288_hclkvio_branch[] __initdata = {
> > > +       DIV(0, "hclk_vio", "aclk_vio0", 0,
> > > +                       RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
> > > +};
> > > +
> > >  static const char *const rk3288_critical_clocks[] __initconst = {
> > >         "aclk_cpu",
> > >         "aclk_peri",
> > > @@ -936,6 +944,14 @@ static void __init rk3288_clk_init(struct device_node *np)
> > >                                    RK3288_GRF_SOC_STATUS1);
> > >         rockchip_clk_register_branches(ctx, rk3288_clk_branches,
> > >                                   ARRAY_SIZE(rk3288_clk_branches));
> > > +
> > > +       if (of_device_is_compatible(np, "rockchip,rk3288w-cru"))
> > > +               rockchip_clk_register_branches(ctx, rk3288w_hclkvio_branch,
> > > +                                              ARRAY_SIZE(rk3288w_hclkvio_branch));
> > > +       else
> > > +               rockchip_clk_register_branches(ctx, rk3288_hclkvio_branch,
> > > +                                              ARRAY_SIZE(rk3288_hclkvio_branch));
> > > +
> >
> > Sorry for the late query on this. I am a bit unclear about this
> > compatible change, does Linux expect to replace rockchip,rk3288-cru
> > with rockchip,rk3288w-cru in bootloader if the chip is RK3288w? or
> > append the existing cru compatible node with rockchip,rk3288w-cru?
> > because replace new cru node make clock never probe since the
> > CLK_OF_DECLARE checking rockchip,rk3288-cru
>
> I guess right now we'd expect "rockchip,rk3288w-cru", "rockchip,rk3288-cru",
>
> Thinking again about this, I'm wondering if we should switch to having
> only one per variant ... like on the two rk3188 variants,
> so declaring separate rk3288-cru and rk3288w-cru of-clks with shared
> common code.

What if can check the root compatible instead cru compatible for revision W like

-  if (of_device_is_compatible(np, "rockchip,rk3288w-cru"))
+ if (of_device_is_compatible(np, "rockchip,rk3288w"))

This way we can have a single compatible update at bootloader that
makes Linux adjust revision W chips code.

Doesn't it make sense?

Jagan.

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v4 1/2] clk: rockchip: rk3288: Handle clock tree for rk3288w
  2020-07-03 14:23       ` Jagan Teki
@ 2020-07-03 14:48         ` Heiko Stuebner
  2020-07-03 15:43           ` Robin Murphy
  0 siblings, 1 reply; 13+ messages in thread
From: Heiko Stuebner @ 2020-07-03 14:48 UTC (permalink / raw)
  To: Jagan Teki
  Cc: Mylène Josserand, Michael Turquette, Stephen Boyd,
	Rob Herring, devicetree, linux-kernel,
	open list:ARM/Rockchip SoC...,
	kernel, linux-clk, linux-arm-kernel, robin.murphy

Am Freitag, 3. Juli 2020, 16:23:27 CEST schrieb Jagan Teki:
> On Fri, Jul 3, 2020 at 7:41 PM Heiko Stuebner <heiko@sntech.de> wrote:
> >
> > Hi Jagan,
> >
> > Am Montag, 29. Juni 2020, 21:11:03 CEST schrieb Jagan Teki:
> > > On Tue, Jun 2, 2020 at 1:37 PM Mylène Josserand
> > > <mylene.josserand@collabora.com> wrote:
> > > >
> > > > The revision rk3288w has a different clock tree about "hclk_vio"
> > > > clock, according to the BSP kernel code.
> > > >
> > > > This patch handles this difference by detecting which device-tree
> > > > we are using. If it is a "rockchip,rk3288-cru", let's register
> > > > the clock tree as it was before. If the device-tree node is
> > > > "rockchip,rk3288w-cru", we will apply the difference with this
> > > > version of this SoC.
> > > >
> > > > Noticed that this new device-tree compatible must be handled in
> > > > bootloader such as u-boot.
> > > >
> > > > Signed-off-by: Mylène Josserand <mylene.josserand@collabora.com>
> > > > ---
> > > >  drivers/clk/rockchip/clk-rk3288.c | 20 ++++++++++++++++++--
> > > >  1 file changed, 18 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
> > > > index cc2a177bbdbf..204976e2d0cb 100644
> > > > --- a/drivers/clk/rockchip/clk-rk3288.c
> > > > +++ b/drivers/clk/rockchip/clk-rk3288.c
> > > > @@ -425,8 +425,6 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
> > > >         COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
> > > >                         RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS,
> > > >                         RK3288_CLKGATE_CON(3), 0, GFLAGS),
> > > > -       DIV(0, "hclk_vio", "aclk_vio0", 0,
> > > > -                       RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
> > > >         COMPOSITE(0, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
> > > >                         RK3288_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,
> > > >                         RK3288_CLKGATE_CON(3), 2, GFLAGS),
> > > > @@ -819,6 +817,16 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
> > > >         INVERTER(0, "pclk_isp", "pclk_isp_in", RK3288_CLKSEL_CON(29), 3, IFLAGS),
> > > >  };
> > > >
> > > > +static struct rockchip_clk_branch rk3288w_hclkvio_branch[] __initdata = {
> > > > +       DIV(0, "hclk_vio", "aclk_vio1", 0,
> > > > +                       RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
> > > > +};
> > > > +
> > > > +static struct rockchip_clk_branch rk3288_hclkvio_branch[] __initdata = {
> > > > +       DIV(0, "hclk_vio", "aclk_vio0", 0,
> > > > +                       RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
> > > > +};
> > > > +
> > > >  static const char *const rk3288_critical_clocks[] __initconst = {
> > > >         "aclk_cpu",
> > > >         "aclk_peri",
> > > > @@ -936,6 +944,14 @@ static void __init rk3288_clk_init(struct device_node *np)
> > > >                                    RK3288_GRF_SOC_STATUS1);
> > > >         rockchip_clk_register_branches(ctx, rk3288_clk_branches,
> > > >                                   ARRAY_SIZE(rk3288_clk_branches));
> > > > +
> > > > +       if (of_device_is_compatible(np, "rockchip,rk3288w-cru"))
> > > > +               rockchip_clk_register_branches(ctx, rk3288w_hclkvio_branch,
> > > > +                                              ARRAY_SIZE(rk3288w_hclkvio_branch));
> > > > +       else
> > > > +               rockchip_clk_register_branches(ctx, rk3288_hclkvio_branch,
> > > > +                                              ARRAY_SIZE(rk3288_hclkvio_branch));
> > > > +
> > >
> > > Sorry for the late query on this. I am a bit unclear about this
> > > compatible change, does Linux expect to replace rockchip,rk3288-cru
> > > with rockchip,rk3288w-cru in bootloader if the chip is RK3288w? or
> > > append the existing cru compatible node with rockchip,rk3288w-cru?
> > > because replace new cru node make clock never probe since the
> > > CLK_OF_DECLARE checking rockchip,rk3288-cru
> >
> > I guess right now we'd expect "rockchip,rk3288w-cru", "rockchip,rk3288-cru",
> >
> > Thinking again about this, I'm wondering if we should switch to having
> > only one per variant ... like on the two rk3188 variants,
> > so declaring separate rk3288-cru and rk3288w-cru of-clks with shared
> > common code.
> 
> What if can check the root compatible instead cru compatible for revision W like
> 
> -  if (of_device_is_compatible(np, "rockchip,rk3288w-cru"))
> + if (of_device_is_compatible(np, "rockchip,rk3288w"))

you'd need to check against the root compatible.

> 
> This way we can have a single compatible update at bootloader that
> makes Linux adjust revision W chips code.
> 
> Doesn't it make sense?

The compatible describes the block and the rk3288w's cru isn't the same as
the rk3288's ... as the clock routing is different, so it should have a
different compatible value, I think.

As the DT sis supposed to be a _generic_ description of the hardware,
we don't want to cement hacks to other implementations would need to copy.


Heiko




^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v4 1/2] clk: rockchip: rk3288: Handle clock tree for rk3288w
  2020-07-03 14:11     ` Heiko Stuebner
  2020-07-03 14:23       ` Jagan Teki
@ 2020-07-03 15:02       ` Ezequiel Garcia
  2020-07-03 15:05         ` Heiko Stuebner
  1 sibling, 1 reply; 13+ messages in thread
From: Ezequiel Garcia @ 2020-07-03 15:02 UTC (permalink / raw)
  To: Heiko Stuebner, Jagan Teki
  Cc: Mylène Josserand, Michael Turquette, Stephen Boyd,
	Rob Herring, devicetree, linux-kernel,
	open list:ARM/Rockchip SoC...,
	kernel, linux-clk, linux-arm-kernel

On Fri, 2020-07-03 at 16:11 +0200, Heiko Stuebner wrote:
> Hi Jagan,
> 
> Am Montag, 29. Juni 2020, 21:11:03 CEST schrieb Jagan Teki:
> > On Tue, Jun 2, 2020 at 1:37 PM Mylène Josserand
> > <mylene.josserand@collabora.com> wrote:
> > > The revision rk3288w has a different clock tree about "hclk_vio"
> > > clock, according to the BSP kernel code.
> > > 
> > > This patch handles this difference by detecting which device-tree
> > > we are using. If it is a "rockchip,rk3288-cru", let's register
> > > the clock tree as it was before. If the device-tree node is
> > > "rockchip,rk3288w-cru", we will apply the difference with this
> > > version of this SoC.
> > > 
> > > Noticed that this new device-tree compatible must be handled in
> > > bootloader such as u-boot.
> > > 
> > > Signed-off-by: Mylène Josserand <mylene.josserand@collabora.com>
> > > ---
> > >  drivers/clk/rockchip/clk-rk3288.c | 20 ++++++++++++++++++--
> > >  1 file changed, 18 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
> > > index cc2a177bbdbf..204976e2d0cb 100644
> > > --- a/drivers/clk/rockchip/clk-rk3288.c
> > > +++ b/drivers/clk/rockchip/clk-rk3288.c
> > > @@ -425,8 +425,6 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
> > >         COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
> > >                         RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS,
> > >                         RK3288_CLKGATE_CON(3), 0, GFLAGS),
> > > -       DIV(0, "hclk_vio", "aclk_vio0", 0,
> > > -                       RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
> > >         COMPOSITE(0, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
> > >                         RK3288_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,
> > >                         RK3288_CLKGATE_CON(3), 2, GFLAGS),
> > > @@ -819,6 +817,16 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
> > >         INVERTER(0, "pclk_isp", "pclk_isp_in", RK3288_CLKSEL_CON(29), 3, IFLAGS),
> > >  };
> > > 
> > > +static struct rockchip_clk_branch rk3288w_hclkvio_branch[] __initdata = {
> > > +       DIV(0, "hclk_vio", "aclk_vio1", 0,
> > > +                       RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
> > > +};
> > > +
> > > +static struct rockchip_clk_branch rk3288_hclkvio_branch[] __initdata = {
> > > +       DIV(0, "hclk_vio", "aclk_vio0", 0,
> > > +                       RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
> > > +};
> > > +
> > >  static const char *const rk3288_critical_clocks[] __initconst = {
> > >         "aclk_cpu",
> > >         "aclk_peri",
> > > @@ -936,6 +944,14 @@ static void __init rk3288_clk_init(struct device_node *np)
> > >                                    RK3288_GRF_SOC_STATUS1);
> > >         rockchip_clk_register_branches(ctx, rk3288_clk_branches,
> > >                                   ARRAY_SIZE(rk3288_clk_branches));
> > > +
> > > +       if (of_device_is_compatible(np, "rockchip,rk3288w-cru"))
> > > +               rockchip_clk_register_branches(ctx, rk3288w_hclkvio_branch,
> > > +                                              ARRAY_SIZE(rk3288w_hclkvio_branch));
> > > +       else
> > > +               rockchip_clk_register_branches(ctx, rk3288_hclkvio_branch,
> > > +                                              ARRAY_SIZE(rk3288_hclkvio_branch));
> > > +
> > 
> > Sorry for the late query on this. I am a bit unclear about this
> > compatible change, does Linux expect to replace rockchip,rk3288-cru
> > with rockchip,rk3288w-cru in bootloader if the chip is RK3288w? or
> > append the existing cru compatible node with rockchip,rk3288w-cru?
> > because replace new cru node make clock never probe since the
> > CLK_OF_DECLARE checking rockchip,rk3288-cru
> 
> I guess right now we'd expect "rockchip,rk3288w-cru", "rockchip,rk3288-cru",
> 
> Thinking again about this, I'm wondering if we should switch to having
> only one per variant ... like on the two rk3188 variants,
> so declaring separate rk3288-cru and rk3288w-cru of-clks with shared
> common code.
> 

If we want to take this route (which I think makes sense), we should
do that sooner than later, so we don't release two different implementations
with two different requirements.

This change should be quite simple, no?

Thanks,
Ezequiel




^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v4 1/2] clk: rockchip: rk3288: Handle clock tree for rk3288w
  2020-07-03 15:02       ` Ezequiel Garcia
@ 2020-07-03 15:05         ` Heiko Stuebner
  0 siblings, 0 replies; 13+ messages in thread
From: Heiko Stuebner @ 2020-07-03 15:05 UTC (permalink / raw)
  To: Ezequiel Garcia
  Cc: Jagan Teki, Mylène Josserand, Michael Turquette,
	Stephen Boyd, Rob Herring, devicetree, linux-kernel,
	open list:ARM/Rockchip SoC...,
	kernel, linux-clk, linux-arm-kernel

Am Freitag, 3. Juli 2020, 17:02:52 CEST schrieb Ezequiel Garcia:
> On Fri, 2020-07-03 at 16:11 +0200, Heiko Stuebner wrote:
> > Hi Jagan,
> > 
> > Am Montag, 29. Juni 2020, 21:11:03 CEST schrieb Jagan Teki:
> > > On Tue, Jun 2, 2020 at 1:37 PM Mylène Josserand
> > > <mylene.josserand@collabora.com> wrote:
> > > > The revision rk3288w has a different clock tree about "hclk_vio"
> > > > clock, according to the BSP kernel code.
> > > > 
> > > > This patch handles this difference by detecting which device-tree
> > > > we are using. If it is a "rockchip,rk3288-cru", let's register
> > > > the clock tree as it was before. If the device-tree node is
> > > > "rockchip,rk3288w-cru", we will apply the difference with this
> > > > version of this SoC.
> > > > 
> > > > Noticed that this new device-tree compatible must be handled in
> > > > bootloader such as u-boot.
> > > > 
> > > > Signed-off-by: Mylène Josserand <mylene.josserand@collabora.com>
> > > > ---
> > > >  drivers/clk/rockchip/clk-rk3288.c | 20 ++++++++++++++++++--
> > > >  1 file changed, 18 insertions(+), 2 deletions(-)
> > > > 
> > > > diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
> > > > index cc2a177bbdbf..204976e2d0cb 100644
> > > > --- a/drivers/clk/rockchip/clk-rk3288.c
> > > > +++ b/drivers/clk/rockchip/clk-rk3288.c
> > > > @@ -425,8 +425,6 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
> > > >         COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
> > > >                         RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS,
> > > >                         RK3288_CLKGATE_CON(3), 0, GFLAGS),
> > > > -       DIV(0, "hclk_vio", "aclk_vio0", 0,
> > > > -                       RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
> > > >         COMPOSITE(0, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
> > > >                         RK3288_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,
> > > >                         RK3288_CLKGATE_CON(3), 2, GFLAGS),
> > > > @@ -819,6 +817,16 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
> > > >         INVERTER(0, "pclk_isp", "pclk_isp_in", RK3288_CLKSEL_CON(29), 3, IFLAGS),
> > > >  };
> > > > 
> > > > +static struct rockchip_clk_branch rk3288w_hclkvio_branch[] __initdata = {
> > > > +       DIV(0, "hclk_vio", "aclk_vio1", 0,
> > > > +                       RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
> > > > +};
> > > > +
> > > > +static struct rockchip_clk_branch rk3288_hclkvio_branch[] __initdata = {
> > > > +       DIV(0, "hclk_vio", "aclk_vio0", 0,
> > > > +                       RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
> > > > +};
> > > > +
> > > >  static const char *const rk3288_critical_clocks[] __initconst = {
> > > >         "aclk_cpu",
> > > >         "aclk_peri",
> > > > @@ -936,6 +944,14 @@ static void __init rk3288_clk_init(struct device_node *np)
> > > >                                    RK3288_GRF_SOC_STATUS1);
> > > >         rockchip_clk_register_branches(ctx, rk3288_clk_branches,
> > > >                                   ARRAY_SIZE(rk3288_clk_branches));
> > > > +
> > > > +       if (of_device_is_compatible(np, "rockchip,rk3288w-cru"))
> > > > +               rockchip_clk_register_branches(ctx, rk3288w_hclkvio_branch,
> > > > +                                              ARRAY_SIZE(rk3288w_hclkvio_branch));
> > > > +       else
> > > > +               rockchip_clk_register_branches(ctx, rk3288_hclkvio_branch,
> > > > +                                              ARRAY_SIZE(rk3288_hclkvio_branch));
> > > > +
> > > 
> > > Sorry for the late query on this. I am a bit unclear about this
> > > compatible change, does Linux expect to replace rockchip,rk3288-cru
> > > with rockchip,rk3288w-cru in bootloader if the chip is RK3288w? or
> > > append the existing cru compatible node with rockchip,rk3288w-cru?
> > > because replace new cru node make clock never probe since the
> > > CLK_OF_DECLARE checking rockchip,rk3288-cru
> > 
> > I guess right now we'd expect "rockchip,rk3288w-cru", "rockchip,rk3288-cru",
> > 
> > Thinking again about this, I'm wondering if we should switch to having
> > only one per variant ... like on the two rk3188 variants,
> > so declaring separate rk3288-cru and rk3288w-cru of-clks with shared
> > common code.
> > 
> 
> If we want to take this route (which I think makes sense), we should
> do that sooner than later, so we don't release two different implementations
> with two different requirements.
> 
> This change should be quite simple, no?

the underlying change is queued for 5.9, but yeah I am currently testing
exactly such a patch ;-)
Especially as when reading the binding addition it states
rk3288w-cru _or_ rk3288-cru for the compatible.


Heiko



^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v4 1/2] clk: rockchip: rk3288: Handle clock tree for rk3288w
  2020-07-03 14:48         ` Heiko Stuebner
@ 2020-07-03 15:43           ` Robin Murphy
  0 siblings, 0 replies; 13+ messages in thread
From: Robin Murphy @ 2020-07-03 15:43 UTC (permalink / raw)
  To: Heiko Stuebner, Jagan Teki
  Cc: Mylène Josserand, Michael Turquette, Stephen Boyd,
	Rob Herring, devicetree, linux-kernel,
	open list:ARM/Rockchip SoC...,
	kernel, linux-clk, linux-arm-kernel

On 2020-07-03 15:48, Heiko Stuebner wrote:
> Am Freitag, 3. Juli 2020, 16:23:27 CEST schrieb Jagan Teki:
>> On Fri, Jul 3, 2020 at 7:41 PM Heiko Stuebner <heiko@sntech.de> wrote:
>>>
>>> Hi Jagan,
>>>
>>> Am Montag, 29. Juni 2020, 21:11:03 CEST schrieb Jagan Teki:
>>>> On Tue, Jun 2, 2020 at 1:37 PM Mylène Josserand
>>>> <mylene.josserand@collabora.com> wrote:
>>>>>
>>>>> The revision rk3288w has a different clock tree about "hclk_vio"
>>>>> clock, according to the BSP kernel code.
>>>>>
>>>>> This patch handles this difference by detecting which device-tree
>>>>> we are using. If it is a "rockchip,rk3288-cru", let's register
>>>>> the clock tree as it was before. If the device-tree node is
>>>>> "rockchip,rk3288w-cru", we will apply the difference with this
>>>>> version of this SoC.
>>>>>
>>>>> Noticed that this new device-tree compatible must be handled in
>>>>> bootloader such as u-boot.
>>>>>
>>>>> Signed-off-by: Mylène Josserand <mylene.josserand@collabora.com>
>>>>> ---
>>>>>   drivers/clk/rockchip/clk-rk3288.c | 20 ++++++++++++++++++--
>>>>>   1 file changed, 18 insertions(+), 2 deletions(-)
>>>>>
>>>>> diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
>>>>> index cc2a177bbdbf..204976e2d0cb 100644
>>>>> --- a/drivers/clk/rockchip/clk-rk3288.c
>>>>> +++ b/drivers/clk/rockchip/clk-rk3288.c
>>>>> @@ -425,8 +425,6 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
>>>>>          COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
>>>>>                          RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS,
>>>>>                          RK3288_CLKGATE_CON(3), 0, GFLAGS),
>>>>> -       DIV(0, "hclk_vio", "aclk_vio0", 0,
>>>>> -                       RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
>>>>>          COMPOSITE(0, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
>>>>>                          RK3288_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,
>>>>>                          RK3288_CLKGATE_CON(3), 2, GFLAGS),
>>>>> @@ -819,6 +817,16 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
>>>>>          INVERTER(0, "pclk_isp", "pclk_isp_in", RK3288_CLKSEL_CON(29), 3, IFLAGS),
>>>>>   };
>>>>>
>>>>> +static struct rockchip_clk_branch rk3288w_hclkvio_branch[] __initdata = {
>>>>> +       DIV(0, "hclk_vio", "aclk_vio1", 0,
>>>>> +                       RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
>>>>> +};
>>>>> +
>>>>> +static struct rockchip_clk_branch rk3288_hclkvio_branch[] __initdata = {
>>>>> +       DIV(0, "hclk_vio", "aclk_vio0", 0,
>>>>> +                       RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
>>>>> +};
>>>>> +
>>>>>   static const char *const rk3288_critical_clocks[] __initconst = {
>>>>>          "aclk_cpu",
>>>>>          "aclk_peri",
>>>>> @@ -936,6 +944,14 @@ static void __init rk3288_clk_init(struct device_node *np)
>>>>>                                     RK3288_GRF_SOC_STATUS1);
>>>>>          rockchip_clk_register_branches(ctx, rk3288_clk_branches,
>>>>>                                    ARRAY_SIZE(rk3288_clk_branches));
>>>>> +
>>>>> +       if (of_device_is_compatible(np, "rockchip,rk3288w-cru"))
>>>>> +               rockchip_clk_register_branches(ctx, rk3288w_hclkvio_branch,
>>>>> +                                              ARRAY_SIZE(rk3288w_hclkvio_branch));
>>>>> +       else
>>>>> +               rockchip_clk_register_branches(ctx, rk3288_hclkvio_branch,
>>>>> +                                              ARRAY_SIZE(rk3288_hclkvio_branch));
>>>>> +
>>>>
>>>> Sorry for the late query on this. I am a bit unclear about this
>>>> compatible change, does Linux expect to replace rockchip,rk3288-cru
>>>> with rockchip,rk3288w-cru in bootloader if the chip is RK3288w? or
>>>> append the existing cru compatible node with rockchip,rk3288w-cru?
>>>> because replace new cru node make clock never probe since the
>>>> CLK_OF_DECLARE checking rockchip,rk3288-cru
>>>
>>> I guess right now we'd expect "rockchip,rk3288w-cru", "rockchip,rk3288-cru",
>>>
>>> Thinking again about this, I'm wondering if we should switch to having
>>> only one per variant ... like on the two rk3188 variants,
>>> so declaring separate rk3288-cru and rk3288w-cru of-clks with shared
>>> common code.
>>
>> What if can check the root compatible instead cru compatible for revision W like
>>
>> -  if (of_device_is_compatible(np, "rockchip,rk3288w-cru"))
>> + if (of_device_is_compatible(np, "rockchip,rk3288w"))
> 
> you'd need to check against the root compatible.
> 
>>
>> This way we can have a single compatible update at bootloader that
>> makes Linux adjust revision W chips code.
>>
>> Doesn't it make sense?
> 
> The compatible describes the block and the rk3288w's cru isn't the same as
> the rk3288's ... as the clock routing is different, so it should have a
> different compatible value, I think.

Right, if two devices behave differently in a way that one behaviour is 
not a strict superset of the other, and there's no way to tell which is 
which by simply looking at the device itself, then by definition they 
are not compatible.

> As the DT sis supposed to be a _generic_ description of the hardware,
> we don't want to cement hacks to other implementations would need to copy.

Indeed it's a pain in the bum for driver developers to be given a new 
thing that's 99.9% compatible with the old thing but the one tiny 
difference fundamentally breaks it, and the temptation to look for an 
easy way out is strong, but c'est la vie ;)

The question I always bear in mind for cases like these is this: If a 
kernel without the driver patch runs on the new system with the expected 
new DTB, will it:

A) work entirely correctly
B) ignore the device (with or without an error), but the rest of the 
system still works fine
C) ignore the device and fail to boot at all (with or without an error) 
because it's critical to operation of the rest of the system
D) probe the device and superficially appear to be OK but actually be 
broken in weird and subtle ways

A and B are the ideal answers. C is a little unfortunate, but acceptable 
if neither A nor B is possible. D is a sign that you're doing something 
wrong, unless there are *very* specific circumstances that might justify 
it (e.g. the SoC is exclusively deployed in embedded devices with a 
controlled update mechanism such that users could never introduce this 
mismatch in the first place).

Robin.

^ permalink raw reply	[flat|nested] 13+ messages in thread

end of thread, back to index

Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-06-02  8:06 [PATCH v4 0/2] ARM: Add Rockchip rk3288w support Mylène Josserand
2020-06-02  8:06 ` [PATCH v4 1/2] clk: rockchip: rk3288: Handle clock tree for rk3288w Mylène Josserand
2020-06-29 19:11   ` Jagan Teki
2020-07-03 14:11     ` Heiko Stuebner
2020-07-03 14:23       ` Jagan Teki
2020-07-03 14:48         ` Heiko Stuebner
2020-07-03 15:43           ` Robin Murphy
2020-07-03 15:02       ` Ezequiel Garcia
2020-07-03 15:05         ` Heiko Stuebner
2020-06-02  8:06 ` [PATCH v4 2/2] dt-bindings: clocks: rk3288: add rk3288w compatible Mylène Josserand
2020-06-09 22:47   ` Rob Herring
2020-06-17  8:58 ` [PATCH v4 0/2] ARM: Add Rockchip rk3288w support Heiko Stuebner
2020-06-29  7:59   ` Mylene Josserand

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