* [PATCH 1/4] clk: renesas: rcar-gen3: Add support for ZG clock
@ 2023-06-17 15:02 Adam Ford
2023-06-17 15:03 ` [PATCH 2/4] clk: renesas: r8a774a1: Add 3dge and ZG support Adam Ford
` (3 more replies)
0 siblings, 4 replies; 8+ messages in thread
From: Adam Ford @ 2023-06-17 15:02 UTC (permalink / raw)
To: linux-clk
Cc: aford, Adam Ford, Geert Uytterhoeven, Michael Turquette,
Stephen Boyd, linux-renesas-soc, linux-kernel
A clock used for the 3D graphics appears to be common
among multiple SoC's, so add a generic gen3 clock
for clocking the graphics. This is similar to the
cpg_z_clk, with a different frequency control register
and different flags. Instead of duplicating the code,
make cpg_z_clk_register into a helper function and
call the help function with the FCR and flags as
a parameter.
Signed-off-by: Adam Ford <aford173@gmail.com>
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
index b3ef62fa612e..d0129a650941 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -264,11 +264,13 @@ static const struct clk_ops cpg_z_clk_ops = {
.set_rate = cpg_z_clk_set_rate,
};
-static struct clk * __init cpg_z_clk_register(const char *name,
+static struct clk * __init __cpg_z_clk_register(const char *name,
const char *parent_name,
void __iomem *reg,
unsigned int div,
- unsigned int offset)
+ unsigned int offset,
+ unsigned int fcr,
+ unsigned int flags)
{
struct clk_init_data init = {};
struct cpg_z_clk *zclk;
@@ -280,11 +282,11 @@ static struct clk * __init cpg_z_clk_register(const char *name,
init.name = name;
init.ops = &cpg_z_clk_ops;
- init.flags = CLK_SET_RATE_PARENT;
+ init.flags = flags;
init.parent_names = &parent_name;
init.num_parents = 1;
- zclk->reg = reg + CPG_FRQCRC;
+ zclk->reg = reg + fcr;
zclk->kick_reg = reg + CPG_FRQCRB;
zclk->hw.init = &init;
zclk->mask = GENMASK(offset + 4, offset);
@@ -301,6 +303,27 @@ static struct clk * __init cpg_z_clk_register(const char *name,
return clk;
}
+static struct clk * __init cpg_z_clk_register(const char *name,
+ const char *parent_name,
+ void __iomem *reg,
+ unsigned int div,
+ unsigned int offset)
+{
+ return __cpg_z_clk_register(name, parent_name, reg, div, offset,
+ CPG_FRQCRC, CLK_SET_RATE_PARENT);
+}
+
+static struct clk * __init cpg_zg_clk_register(const char *name,
+ const char *parent_name,
+ void __iomem *reg,
+ unsigned int div,
+ unsigned int offset)
+{
+ return __cpg_z_clk_register(name, parent_name, reg, div, offset,
+ CPG_FRQCRB, 0);
+
+}
+
static const struct clk_div_table cpg_rpcsrc_div_table[] = {
{ 2, 5 }, { 3, 6 }, { 0, 0 },
};
@@ -438,6 +461,10 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
return cpg_z_clk_register(core->name, __clk_get_name(parent),
base, core->div, core->offset);
+ case CLK_TYPE_GEN3_ZG:
+ return cpg_zg_clk_register(core->name, __clk_get_name(parent),
+ base, core->div, core->offset);
+
case CLK_TYPE_GEN3_OSC:
/*
* Clock combining OSC EXTAL predivider and a fixed divider
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h
index 9028bf4295ce..bfdc649bdf12 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -22,6 +22,7 @@ enum rcar_gen3_clk_types {
CLK_TYPE_GEN3_R,
CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */
CLK_TYPE_GEN3_Z,
+ CLK_TYPE_GEN3_ZG,
CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */
CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */
CLK_TYPE_GEN3_RPCSRC,
--
2.39.2
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/4] clk: renesas: r8a774a1: Add 3dge and ZG support
2023-06-17 15:02 [PATCH 1/4] clk: renesas: rcar-gen3: Add support for ZG clock Adam Ford
@ 2023-06-17 15:03 ` Adam Ford
2023-06-19 8:05 ` Geert Uytterhoeven
2023-06-17 15:03 ` [PATCH 3/4] clk: renesas: r8a774e1: " Adam Ford
` (2 subsequent siblings)
3 siblings, 1 reply; 8+ messages in thread
From: Adam Ford @ 2023-06-17 15:03 UTC (permalink / raw)
To: linux-clk
Cc: aford, Adam Ford, Geert Uytterhoeven, Michael Turquette,
Stephen Boyd, linux-renesas-soc, linux-kernel
The 3dge and ZG clocks are necessary to support the 3D graphics.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
index ad03c09ebc1f..7e70c9a9affa 100644
--- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
@@ -76,6 +76,7 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = {
/* Core Clock Outputs */
DEF_GEN3_Z("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
+ DEF_GEN3_Z("zg", R8A774A1_CLK_ZG, CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24),
DEF_FIXED("ztr", R8A774A1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A774A1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A774A1_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
@@ -123,6 +124,7 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = {
};
static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = {
+ DEF_MOD("3dge", 112, R8A774A1_CLK_ZG),
DEF_MOD("tmu4", 121, R8A774A1_CLK_S0D6),
DEF_MOD("tmu3", 122, R8A774A1_CLK_S3D2),
DEF_MOD("tmu2", 123, R8A774A1_CLK_S3D2),
--
2.39.2
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 3/4] clk: renesas: r8a774e1: Add 3dge and ZG support
2023-06-17 15:02 [PATCH 1/4] clk: renesas: rcar-gen3: Add support for ZG clock Adam Ford
2023-06-17 15:03 ` [PATCH 2/4] clk: renesas: r8a774a1: Add 3dge and ZG support Adam Ford
@ 2023-06-17 15:03 ` Adam Ford
2023-06-19 8:06 ` Geert Uytterhoeven
2023-06-17 15:03 ` [PATCH 4/4] " Adam Ford
2023-06-19 8:05 ` [PATCH 1/4] clk: renesas: rcar-gen3: Add support for ZG clock Geert Uytterhoeven
3 siblings, 1 reply; 8+ messages in thread
From: Adam Ford @ 2023-06-17 15:03 UTC (permalink / raw)
To: linux-clk
Cc: aford, Adam Ford, Geert Uytterhoeven, Michael Turquette,
Stephen Boyd, linux-renesas-soc, linux-kernel
The 3dge and ZG clocks are necessary to support the 3D graphics.
Signed-off-by: Adam Ford <aford173@gmail.com>
diff --git a/drivers/clk/renesas/r8a774e1-cpg-mssr.c b/drivers/clk/renesas/r8a774e1-cpg-mssr.c
index a790061db877..13fed5e59068 100644
--- a/drivers/clk/renesas/r8a774e1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774e1-cpg-mssr.c
@@ -76,6 +76,7 @@ static const struct cpg_core_clk r8a774e1_core_clks[] __initconst = {
/* Core Clock Outputs */
DEF_GEN3_Z("z", R8A774E1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
DEF_GEN3_Z("z2", R8A774E1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
+ DEF_GEN3_Z("zg", R8A774E1_CLK_ZG, CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24),
DEF_FIXED("ztr", R8A774E1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A774E1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A774E1_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
@@ -124,6 +125,7 @@ static const struct cpg_core_clk r8a774e1_core_clks[] __initconst = {
};
static const struct mssr_mod_clk r8a774e1_mod_clks[] __initconst = {
+ DEF_MOD("3dge", 112, R8A774E1_CLK_ZG),
DEF_MOD("fdp1-1", 118, R8A774E1_CLK_S0D1),
DEF_MOD("fdp1-0", 119, R8A774E1_CLK_S0D1),
DEF_MOD("tmu4", 121, R8A774E1_CLK_S0D6),
--
2.39.2
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 4/4] clk: renesas: r8a774e1: Add 3dge and ZG support
2023-06-17 15:02 [PATCH 1/4] clk: renesas: rcar-gen3: Add support for ZG clock Adam Ford
2023-06-17 15:03 ` [PATCH 2/4] clk: renesas: r8a774a1: Add 3dge and ZG support Adam Ford
2023-06-17 15:03 ` [PATCH 3/4] clk: renesas: r8a774e1: " Adam Ford
@ 2023-06-17 15:03 ` Adam Ford
2023-06-19 8:08 ` Geert Uytterhoeven
2023-06-19 8:05 ` [PATCH 1/4] clk: renesas: rcar-gen3: Add support for ZG clock Geert Uytterhoeven
3 siblings, 1 reply; 8+ messages in thread
From: Adam Ford @ 2023-06-17 15:03 UTC (permalink / raw)
To: linux-clk
Cc: aford, Adam Ford, Geert Uytterhoeven, Michael Turquette,
Stephen Boyd, linux-renesas-soc, linux-kernel
The 3dge and ZG clocks are necessary to support the 3D graphics.
Signed-off-by: Adam Ford <aford173@gmail.com>
diff --git a/drivers/clk/renesas/r8a774b1-cpg-mssr.c b/drivers/clk/renesas/r8a774b1-cpg-mssr.c
index ab087b02ef90..33d4e5ff9ff6 100644
--- a/drivers/clk/renesas/r8a774b1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774b1-cpg-mssr.c
@@ -73,6 +73,7 @@ static const struct cpg_core_clk r8a774b1_core_clks[] __initconst = {
/* Core Clock Outputs */
DEF_GEN3_Z("z", R8A774B1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
+ DEF_GEN3_Z("zg", R8A774B1_CLK_ZG, CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24),
DEF_FIXED("ztr", R8A774B1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A774B1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A774B1_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
@@ -120,6 +121,7 @@ static const struct cpg_core_clk r8a774b1_core_clks[] __initconst = {
};
static const struct mssr_mod_clk r8a774b1_mod_clks[] __initconst = {
+ DEF_MOD("3dge", 112, R8A774B1_CLK_ZG),
DEF_MOD("tmu4", 121, R8A774B1_CLK_S0D6),
DEF_MOD("tmu3", 122, R8A774B1_CLK_S3D2),
DEF_MOD("tmu2", 123, R8A774B1_CLK_S3D2),
--
2.39.2
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 1/4] clk: renesas: rcar-gen3: Add support for ZG clock
2023-06-17 15:02 [PATCH 1/4] clk: renesas: rcar-gen3: Add support for ZG clock Adam Ford
` (2 preceding siblings ...)
2023-06-17 15:03 ` [PATCH 4/4] " Adam Ford
@ 2023-06-19 8:05 ` Geert Uytterhoeven
3 siblings, 0 replies; 8+ messages in thread
From: Geert Uytterhoeven @ 2023-06-19 8:05 UTC (permalink / raw)
To: Adam Ford
Cc: linux-clk, aford, Michael Turquette, Stephen Boyd,
linux-renesas-soc, linux-kernel
On Sat, Jun 17, 2023 at 5:03 PM Adam Ford <aford173@gmail.com> wrote:
> A clock used for the 3D graphics appears to be common
> among multiple SoC's, so add a generic gen3 clock
> for clocking the graphics. This is similar to the
> cpg_z_clk, with a different frequency control register
> and different flags. Instead of duplicating the code,
> make cpg_z_clk_register into a helper function and
> call the help function with the FCR and flags as
> a parameter.
>
> Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk-for-v6.6.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/4] clk: renesas: r8a774a1: Add 3dge and ZG support
2023-06-17 15:03 ` [PATCH 2/4] clk: renesas: r8a774a1: Add 3dge and ZG support Adam Ford
@ 2023-06-19 8:05 ` Geert Uytterhoeven
0 siblings, 0 replies; 8+ messages in thread
From: Geert Uytterhoeven @ 2023-06-19 8:05 UTC (permalink / raw)
To: Adam Ford
Cc: linux-clk, aford, Michael Turquette, Stephen Boyd,
linux-renesas-soc, linux-kernel
On Sat, Jun 17, 2023 at 5:03 PM Adam Ford <aford173@gmail.com> wrote:
> The 3dge and ZG clocks are necessary to support the 3D graphics.
>
> Signed-off-by: Adam Ford <aford173@gmail.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks, will queue in renesas-clk-for-v6.6.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 3/4] clk: renesas: r8a774e1: Add 3dge and ZG support
2023-06-17 15:03 ` [PATCH 3/4] clk: renesas: r8a774e1: " Adam Ford
@ 2023-06-19 8:06 ` Geert Uytterhoeven
0 siblings, 0 replies; 8+ messages in thread
From: Geert Uytterhoeven @ 2023-06-19 8:06 UTC (permalink / raw)
To: Adam Ford
Cc: linux-clk, aford, Michael Turquette, Stephen Boyd,
linux-renesas-soc, linux-kernel
On Sat, Jun 17, 2023 at 5:03 PM Adam Ford <aford173@gmail.com> wrote:
> The 3dge and ZG clocks are necessary to support the 3D graphics.
>
> Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk-for-v6.6.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 4/4] clk: renesas: r8a774e1: Add 3dge and ZG support
2023-06-17 15:03 ` [PATCH 4/4] " Adam Ford
@ 2023-06-19 8:08 ` Geert Uytterhoeven
0 siblings, 0 replies; 8+ messages in thread
From: Geert Uytterhoeven @ 2023-06-19 8:08 UTC (permalink / raw)
To: Adam Ford
Cc: linux-clk, Adam Ford-BE, Geert Uytterhoeven, Michael Turquette,
Stephen Boyd, Linux-Renesas, Linux Kernel Mailing List
On Sat, Jun 17, 2023 at 5:03 PM Adam Ford <aford173@gmail.com> wrote:
> The 3dge and ZG clocks are necessary to support the 3D graphics.
>
> Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk-for-v6.6, with s/e1/b1/ in the one-line summary.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2023-06-19 8:09 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
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2023-06-17 15:02 [PATCH 1/4] clk: renesas: rcar-gen3: Add support for ZG clock Adam Ford
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2023-06-19 8:05 ` Geert Uytterhoeven
2023-06-17 15:03 ` [PATCH 3/4] clk: renesas: r8a774e1: " Adam Ford
2023-06-19 8:06 ` Geert Uytterhoeven
2023-06-17 15:03 ` [PATCH 4/4] " Adam Ford
2023-06-19 8:08 ` Geert Uytterhoeven
2023-06-19 8:05 ` [PATCH 1/4] clk: renesas: rcar-gen3: Add support for ZG clock Geert Uytterhoeven
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