From: Nicolas Boichat <drinkcat@chromium.org>
To: Weiyi Lu <weiyi.lu@mediatek.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>,
Stephen Boyd <sboyd@codeaurora.org>,
Rob Herring <robh@kernel.org>,
James Liao <jamesjj.liao@mediatek.com>,
Fan Chen <fan.chen@mediatek.com>,
linux-arm Mailing List <linux-arm-kernel@lists.infradead.org>,
lkml <linux-kernel@vger.kernel.org>,
"moderated list:ARM/Mediatek SoC support"
<linux-mediatek@lists.infradead.org>,
linux-clk@vger.kernel.org,
srv_heupstream <srv_heupstream@mediatek.com>,
stable@vger.kernel.org
Subject: Re: [PATCH v5 6/9] clk: mediatek: Add flags support for mtk_gate data
Date: Fri, 8 Mar 2019 14:20:57 +0800 [thread overview]
Message-ID: <CANMq1KDzSpc6sam5wgUZX_vD4200WPnVs5CxQuu-CSV69ffArQ@mail.gmail.com> (raw)
In-Reply-To: <20190305050546.23431-8-weiyi.lu@mediatek.com>
On Tue, Mar 5, 2019 at 1:06 PM Weiyi Lu <weiyi.lu@mediatek.com> wrote:
>
> On some Mediatek platforms, there are critical clocks of
> clock gate type.
> To register clock gate with flags CLK_IS_CRITICAL,
> we need to add the flags field in mtk_gate data and register APIs.
>
> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Reviewed-and-tested-by: Nicolas Boichat <drinkcat@chromium.org>
> ---
> drivers/clk/mediatek/clk-gate.c | 5 +++--
> drivers/clk/mediatek/clk-gate.h | 3 ++-
> drivers/clk/mediatek/clk-mtk.c | 3 ++-
> drivers/clk/mediatek/clk-mtk.h | 1 +
> 4 files changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c
> index 934bf0e45e26..85daf826619a 100644
> --- a/drivers/clk/mediatek/clk-gate.c
> +++ b/drivers/clk/mediatek/clk-gate.c
> @@ -157,7 +157,8 @@ struct clk *mtk_clk_register_gate(
> int clr_ofs,
> int sta_ofs,
> u8 bit,
> - const struct clk_ops *ops)
> + const struct clk_ops *ops,
> + unsigned long flags)
> {
> struct mtk_clk_gate *cg;
> struct clk *clk;
> @@ -168,7 +169,7 @@ struct clk *mtk_clk_register_gate(
> return ERR_PTR(-ENOMEM);
>
> init.name = name;
> - init.flags = CLK_SET_RATE_PARENT;
> + init.flags = flags | CLK_SET_RATE_PARENT;
> init.parent_names = parent_name ? &parent_name : NULL;
> init.num_parents = parent_name ? 1 : 0;
> init.ops = ops;
> diff --git a/drivers/clk/mediatek/clk-gate.h b/drivers/clk/mediatek/clk-gate.h
> index 72ef89b3ad7b..9f766dfe1d57 100644
> --- a/drivers/clk/mediatek/clk-gate.h
> +++ b/drivers/clk/mediatek/clk-gate.h
> @@ -47,6 +47,7 @@ struct clk *mtk_clk_register_gate(
> int clr_ofs,
> int sta_ofs,
> u8 bit,
> - const struct clk_ops *ops);
> + const struct clk_ops *ops,
> + unsigned long flags);
>
> #endif /* __DRV_CLK_GATE_H */
> diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
> index 9c0ae4278a94..35359e5397c7 100644
> --- a/drivers/clk/mediatek/clk-mtk.c
> +++ b/drivers/clk/mediatek/clk-mtk.c
> @@ -130,7 +130,8 @@ int mtk_clk_register_gates(struct device_node *node,
> gate->regs->set_ofs,
> gate->regs->clr_ofs,
> gate->regs->sta_ofs,
> - gate->shift, gate->ops);
> + gate->shift, gate->ops,
> + gate->flags);
>
> if (IS_ERR(clk)) {
> pr_err("Failed to register clk %s: %ld\n",
> diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
> index 11b5517903d0..928905496c4b 100644
> --- a/drivers/clk/mediatek/clk-mtk.h
> +++ b/drivers/clk/mediatek/clk-mtk.h
> @@ -158,6 +158,7 @@ struct mtk_gate {
> const struct mtk_gate_regs *regs;
> int shift;
> const struct clk_ops *ops;
> + unsigned long flags;
> };
>
> int mtk_clk_register_gates(struct device_node *node,
> --
> 2.18.0
>
next prev parent reply other threads:[~2019-03-08 6:21 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-05 5:05 [PATCH v5 0/9] Mediatek MT8183 clock support Weiyi Lu
2019-03-05 5:05 ` Weiyi Lu
2019-03-05 18:41 ` Stephen Boyd
2019-03-05 5:05 ` [PATCH v5 1/9] clk: mediatek: Disable tuner_en before change PLL rate Weiyi Lu
2019-03-05 6:42 ` James Liao
2019-03-07 16:09 ` Matthias Brugger
2019-04-11 20:16 ` Stephen Boyd
2019-03-05 5:05 ` [PATCH v5 2/9] clk: mediatek: Add new clkmux register API Weiyi Lu
2019-03-05 6:43 ` James Liao
2019-03-08 6:17 ` Nicolas Boichat
2019-03-14 23:21 ` Nicolas Boichat
2019-04-11 20:12 ` Stephen Boyd
2019-04-11 20:16 ` Stephen Boyd
2019-03-05 5:05 ` [PATCH v5 3/9] clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_data Weiyi Lu
2019-03-05 6:46 ` James Liao
2019-03-08 6:20 ` Nicolas Boichat
2019-04-11 20:14 ` Stephen Boyd
2019-04-11 20:16 ` Stephen Boyd
2019-03-05 5:05 ` [PATCH v5 4/9] dt-bindings: ARM: Mediatek: Document bindings for MT8183 Weiyi Lu
2019-03-05 5:05 ` [PATCH v5 5/9] clk: mediatek: Add dt-bindings for MT8183 clocks Weiyi Lu
2019-04-11 20:16 ` Stephen Boyd
2019-03-05 5:05 ` [PATCH v5 6/9] clk: mediatek: Add flags support for mtk_gate data Weiyi Lu
2019-03-05 6:47 ` James Liao
2019-03-08 6:20 ` Nicolas Boichat [this message]
2019-04-11 20:19 ` Stephen Boyd
2019-04-12 2:42 ` Weiyi Lu
2019-03-05 5:05 ` [PATCH v5 7/9] clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_data Weiyi Lu
2019-03-05 6:47 ` James Liao
2019-03-08 6:23 ` Nicolas Boichat
2019-04-11 20:21 ` Stephen Boyd
2019-03-05 5:05 ` [PATCH v5 8/9] clk: mediatek: Add MT8183 clock support Weiyi Lu
2019-03-08 6:42 ` Nicolas Boichat
2019-03-08 14:46 ` Nicolas Boichat
2019-04-11 20:24 ` Stephen Boyd
2019-04-11 20:24 ` Stephen Boyd
2019-03-05 5:05 ` [PATCH v5 9/9] clk: mediatek: Allow changing PLL rate when it is off Weiyi Lu
2019-03-05 6:48 ` James Liao
2019-04-11 20:24 ` Stephen Boyd
2019-03-28 5:18 ` [PATCH v5 0/9] Mediatek MT8183 clock support Weiyi Lu
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