* Re: [PATCH 00/18] ARM: qcom: apq8064: support CPU frequency scaling
2023-06-12 5:39 [PATCH 00/18] ARM: qcom: apq8064: support CPU frequency scaling Dmitry Baryshkov
@ 2023-06-11 16:27 ` Christian Marangi
2023-06-12 14:20 ` Dmitry Baryshkov
2023-06-12 5:39 ` [PATCH 01/18] dt-bindings: opp: opp-v2-kryo-cpu: support Qualcomm Krait SoCs Dmitry Baryshkov
` (17 subsequent siblings)
18 siblings, 1 reply; 36+ messages in thread
From: Christian Marangi @ 2023-06-11 16:27 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Ilia Lin, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki, linux-arm-msm, devicetree, linux-pm,
linux-clk
On Mon, Jun 12, 2023 at 08:39:04AM +0300, Dmitry Baryshkov wrote:
> Implement CPUFreq support for one of the oldest supported Qualcomm
> platforms, APQ8064. Each core has independent power and frequency
> control. Additionally the L2 cache is scaled to follow the CPU
> frequencies (failure to do so results in strange semi-random crashes).
Hi, can we talk, maybe in private about this interconnect-cpu thing?
I see you follow the original implementation of the msm_bus where in
practice with the use of the kbps the correct clock and voltage was set.
(and this was also used to set the fabric clock from nominal to fast)
On ipq806x and I assume other SoC there isn't always a 1:1 map of CPU
freq and L2 freq. For example on ipq8064 we have max CPU freq of 1.4GHz
and L2 freq of 1.2GHz, on ipq8065 we have CPU 1.7GHz and L2 of 1.4GHz.
(and even that is curious since I used the debug regs and the cxo
crystal to measure the clock by hardware (yes i ported the very ancient
clk-debug to modern kernel and it works and discovered all sort of
things) the L2 (I assume due to climitation of the hfpll) actually can't
never reach that frequency (1.4GHz in reality results to something like
1.2GHz from what I notice a stable clock is there only with frequency of
max 1GHz))
So my idea was to introduce a simple devfreq driver and use the PASSIVE
governor where it was added the possibility to link to a CPU frequency
and with interpolation select the L2 frequency (and voltage)
From some old comments in ancient qsdk code it was pointed out that due
to a hw limitation the secondary cpu can't stay at a high clock if L2
was at the idle clock. (no idea if this is specific to IPQ806x) So this
might be a cause of your crash? (I also have random crash with L2
scaling and we are planning to just force the L2 at max frequency)
But sorry for all of this (maybe) useless info. I checked the other
patch and I didn't understand how the different L2 frequency are
declared and even the voltage. Is this something that will come later?
I'm very interested in this implementation.
>
> Core voltage is controlled through the SAW2 devices, one for each core.
> The L2 has two regulators, vdd-mem and vdd-dig.
>
> Depenency: [1] for interconnect-clk implementation
>
> https://lore.kernel.org/linux-arm-msm/20230512001334.2983048-3-dmitry.baryshkov@linaro.org/
>
--
Ansuel
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 15/18] ARM: dts: qcom: apq8064: provide voltage scaling tables
2023-06-12 13:33 ` Dmitry Baryshkov
@ 2023-06-11 22:16 ` Christian Marangi
2023-06-12 13:59 ` Stephan Gerhold
1 sibling, 0 replies; 36+ messages in thread
From: Christian Marangi @ 2023-06-11 22:16 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Stephan Gerhold, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Ilia Lin,
Viresh Kumar, Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki, linux-arm-msm, devicetree, linux-pm,
linux-clk
On Mon, Jun 12, 2023 at 04:33:09PM +0300, Dmitry Baryshkov wrote:
> On 12/06/2023 12:01, Stephan Gerhold wrote:
> > On Mon, Jun 12, 2023 at 08:39:19AM +0300, Dmitry Baryshkov wrote:
> > > APQ8064 has 4 speed bins, each of them having from 4 to 6 categorization
> > > kinds. Provide tables necessary to handle voltage scaling on this SoC.
> > >
> > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > > ---
> > > arch/arm/boot/dts/qcom-apq8064.dtsi | 1017 +++++++++++++++++++++++++++
> > > 1 file changed, 1017 insertions(+)
> > >
> > > diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
> > > index 4ef13f3d702b..f35853b59544 100644
> > > --- a/arch/arm/boot/dts/qcom-apq8064.dtsi
> > > +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
> > > @@ -49,6 +49,9 @@ CPU0: cpu@0 {
> > > clocks = <&kraitcc KRAIT_CPU_0>;
> > > clock-names = "cpu";
> > > clock-latency = <100000>;
> > > + vdd-mem-supply = <&pm8921_l24>;
> > > + vdd-dig-supply = <&pm8921_s3>;
> > > + vdd-core-supply = <&saw0_vreg>;
> > > interconnects = <&kraitcc MASTER_KRAIT_L2 &kraitcc SLAVE_KRAIT_L2>;
> > > operating-points-v2 = <&cpu_opp_table>;
> > > #cooling-cells = <2>;
> > > @@ -66,6 +69,9 @@ CPU1: cpu@1 {
> > > clocks = <&kraitcc KRAIT_CPU_1>;
> > > clock-names = "cpu";
> > > clock-latency = <100000>;
> > > + vdd-mem-supply = <&pm8921_l24>;
> > > + vdd-dig-supply = <&pm8921_s3>;
> > > + vdd-core-supply = <&saw1_vreg>;
> > > interconnects = <&kraitcc MASTER_KRAIT_L2 &kraitcc SLAVE_KRAIT_L2>;
> > > operating-points-v2 = <&cpu_opp_table>;
> > > #cooling-cells = <2>;
> > > @@ -83,6 +89,9 @@ CPU2: cpu@2 {
> > > clocks = <&kraitcc KRAIT_CPU_2>;
> > > clock-names = "cpu";
> > > clock-latency = <100000>;
> > > + vdd-mem-supply = <&pm8921_l24>;
> > > + vdd-dig-supply = <&pm8921_s3>;
> > > + vdd-core-supply = <&saw2_vreg>;
> > > interconnects = <&kraitcc MASTER_KRAIT_L2 &kraitcc SLAVE_KRAIT_L2>;
> > > operating-points-v2 = <&cpu_opp_table>;
> > > #cooling-cells = <2>;
> > > @@ -100,6 +109,9 @@ CPU3: cpu@3 {
> > > clocks = <&kraitcc KRAIT_CPU_3>;
> > > clock-names = "cpu";
> > > clock-latency = <100000>;
> > > + vdd-mem-supply = <&pm8921_l24>;
> > > + vdd-dig-supply = <&pm8921_s3>;
> > > + vdd-core-supply = <&saw3_vreg>;
> > > interconnects = <&kraitcc MASTER_KRAIT_L2 &kraitcc SLAVE_KRAIT_L2>;
> > > operating-points-v2 = <&cpu_opp_table>;
> > > #cooling-cells = <2>;
> > > @@ -132,6 +144,81 @@ cpu_opp_table: opp-table-cpu {
> > > opp-384000000 {
> > > opp-hz = /bits/ 64 <384000000>;
> > > opp-peak-kBps = <384000>;
> > > + opp-microvolt-speed0-pvs0 = <1050000 1050000 1150000>,
> > > + <950000 950000 1150000>,
> > > + <950000 950000 975000>;
> >
> > I think this won't result in the correct switch order without making
> > some changes to the OPP core. In _set_opp() the OPP core does
> >
> > /* Scaling up? Configure required OPPs before frequency */
> > if (!scaling_down) {
> > _set_required_opps();
> > _set_opp_bw();
> > opp_table->config_regulators();
> > }
> >
> > opp_table->config_clks();
> >
> > /* Scaling down? Configure required OPPs after frequency */
> > if (scaling_down) {
> > opp_table->config_regulators();
> > _set_opp_bw();
> > _set_required_opps();
> > }
> >
> > Since the "bandwidth" for the L2 cache is set before the regulators
> > there is a short window where the L2 clock is running at a high
> > frequency with too low voltage, which could potentially cause
> > instability. On downstream this seems to be done in the proper order [1].
> >
> > I'm not sure if the order in the OPP core is on purpose. If not, you
> > could propose moving the config_regulators() first (for scaling up)
> > and last (for scaling down). This would resolve the problem.
>
> Nice catch, I missed this ordering point.
>
> >
> > The alternative that I've already argued for on IRC in #linux-msm a
> > couple of days ago would be to give the L2 cache (here: "interconnect")
> > an own OPP table where it can describe its voltage requirements,
> > independent from the CPU. That way the icc_set_bw() would be guaranteed
> > to apply the correct voltage before adjusting the L2 cache clock. It
> > looks like the "l2_level" voltages for vdd_dig and vdd_mem are not
> > speedbin/PVS-specific [2] so this would also significantly reduce the DT
> > size, since you wouldn't need to repeat the same vdd_dig/vdd_mem
> > voltages for all of them.
>
> Yes. I fact our discussion triggered me to do this patchset.
>
> So, another option would be to have something like the following snippet. Do
> you know if we are allowed to squish additional data into the L2 cache DT
> node?
>
I have a similar implementation with the l2 devfreq driver where I need
to put a compatible in the l2-cache node. From what I observed, keeping
the l2-cache node in the cpus node makes the extra compile not work
(nothing is probed) but moving the l2-cache node in the soc node and
referencing the phandle makes the compatible correctly works and that
doesn't seems to cause any problem. IMHO it would be better to have a
separate opp table for l2, should keep things more organized.
> CPU0: cpu@0 {
> vdd-core-supply = <&saw0_vreg>;
> interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>;
> operating-points-v2 = <&cpu_opp_table>;
> };
>
> L2: l2-cache {
> compatible = "qcom,apq8064-l2-cache", "cache";
>
> clocks = <&kraitcc KRAIT_L2>;
> vdd-mem-supply = <&pm8921_l24>;
> vdd-dig-supply = <&pm8921_s3>;
> operating-points-v2 = <&l2_opp_table>;
>
> l2_opp_table {
> compatible = "operating-points-v2";
> opp-384000000 {
> opp-hz = /bits/ 64 <384000000>;
> opp-microvolt = <1050000 1050000 1150000>,
> <950000 950000 1150000>;
> };
>
> opp-648000000 {
> opp-hz = /bits/ 64 <648000000>;
> opp-microvolt = <1050000 1050000 1150000>,
> <1050000 1050000 1150000>;
> };
>
> opp-1134000000 {
> opp-hz = /bits/ 64 <1134000000>;
> opp-microvolt = <1150000 1150000 1150000>,
> <1150000 1150000 1150000>;
> };
> };
> };
>
> >
> > Thanks,
> > Stephan
> >
> > [1]: https://git.codelinaro.org/clo/la/kernel/msm/-/blob/LA.AF.1.2.1-08410-8064.0/arch/arm/mach-msm/acpuclock-krait.c#L529-588
> > [2]: https://git.codelinaro.org/clo/la/kernel/msm/-/blob/LA.AF.1.2.1-08410-8064.0/arch/arm/mach-msm/acpuclock-8064.c#L118-135
>
> --
> With best wishes
> Dmitry
>
--
Ansuel
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 00/18] ARM: qcom: apq8064: support CPU frequency scaling
@ 2023-06-12 5:39 Dmitry Baryshkov
2023-06-11 16:27 ` Christian Marangi
` (18 more replies)
0 siblings, 19 replies; 36+ messages in thread
From: Dmitry Baryshkov @ 2023-06-12 5:39 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Ilia Lin, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki
Cc: linux-arm-msm, devicetree, linux-pm, linux-clk, Christian Marangi
Implement CPUFreq support for one of the oldest supported Qualcomm
platforms, APQ8064. Each core has independent power and frequency
control. Additionally the L2 cache is scaled to follow the CPU
frequencies (failure to do so results in strange semi-random crashes).
Core voltage is controlled through the SAW2 devices, one for each core.
The L2 has two regulators, vdd-mem and vdd-dig.
Depenency: [1] for interconnect-clk implementation
https://lore.kernel.org/linux-arm-msm/20230512001334.2983048-3-dmitry.baryshkov@linaro.org/
Dmitry Baryshkov (18):
dt-bindings: opp: opp-v2-kryo-cpu: support Qualcomm Krait SoCs
dt-bindings: soc: qcom: merge qcom,saw2.txt into qcom,spm.yaml
dt-bindings: soc: qcom: qcom,saw2: define optional regulator node
dt-bindings: clock: qcom,krait-cc: Krait core clock controller
clk: qcom: krait-cc: rewrite driver to use clk_hw instead of clk
clk: qcom: krait-cc: export L2 clock as an interconnect
soc: qcom: spm: add support for voltage regulator
cpufreq: qcom-nvmem: also accept operating-points-v2-krait-cpu
cpufreq: qcom-nvmem: Add support for voltage scaling
cpufreq: qcom-nvmem: drop pvs_ver for format a fuses
cpufreq: qcom-nvmem: provide separate configuration data for apq8064
ARM: dts: qcom: apq8064: rename SAW nodes to power-manager
ARM: dts: qcom: apq8064: declare SAW2 regulators
ARM: dts: qcom: apq8064: add simple CPUFreq support
ARM: dts: qcom: apq8064: provide voltage scaling tables
ARM: dts: qcom: apq8064: enable passive CPU cooling
ARM: dts: qcom: apq8064-asus-nexus7-flo: constraint cpufreq regulators
ARM: dts: qcom: apq8064-ifc6410: constraint cpufreq regulators
.../devicetree/bindings/arm/msm/qcom,saw2.txt | 58 -
.../bindings/opp/opp-v2-kryo-cpu.yaml | 11 +-
.../qcom/{qcom,spm.yaml => qcom,saw2.yaml} | 39 +-
.../boot/dts/qcom-apq8064-asus-nexus7-flo.dts | 14 +-
arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 18 +-
arch/arm/boot/dts/qcom-apq8064.dtsi | 1247 ++++++++++++++++-
drivers/clk/qcom/Kconfig | 1 +
drivers/clk/qcom/krait-cc.c | 185 +--
drivers/cpufreq/qcom-cpufreq-nvmem.c | 164 ++-
drivers/soc/qcom/spm.c | 205 ++-
include/dt-bindings/clock/qcom,krait-cc.h | 20 +
include/soc/qcom/spm.h | 9 +
12 files changed, 1806 insertions(+), 165 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
rename Documentation/devicetree/bindings/soc/qcom/{qcom,spm.yaml => qcom,saw2.yaml} (58%)
create mode 100644 include/dt-bindings/clock/qcom,krait-cc.h
--
2.39.2
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 01/18] dt-bindings: opp: opp-v2-kryo-cpu: support Qualcomm Krait SoCs
2023-06-12 5:39 [PATCH 00/18] ARM: qcom: apq8064: support CPU frequency scaling Dmitry Baryshkov
2023-06-11 16:27 ` Christian Marangi
@ 2023-06-12 5:39 ` Dmitry Baryshkov
2023-06-14 16:01 ` Krzysztof Kozlowski
2023-06-12 5:39 ` [PATCH 02/18] dt-bindings: soc: qcom: merge qcom,saw2.txt into qcom,spm.yaml Dmitry Baryshkov
` (16 subsequent siblings)
18 siblings, 1 reply; 36+ messages in thread
From: Dmitry Baryshkov @ 2023-06-12 5:39 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Ilia Lin, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki
Cc: linux-arm-msm, devicetree, linux-pm, linux-clk, Christian Marangi
Exted the opp-v2-kryo-cpu.yaml to support defining OPP tables for the
previous generation of Qualcomm CPUs, 32-bit Krait-based platforms.
It makes no sense to use 'operating-points-v2-kryo-cpu' compatibility
node for the Krait cores. Add support for the Krait-specific
'operating-points-v2-krait-cpu' compatibility string and the relevant
opp-microvolt subclasses properties.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../devicetree/bindings/opp/opp-v2-kryo-cpu.yaml | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml b/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml
index bbbad31ae4ca..93ec778bf333 100644
--- a/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml
+++ b/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml
@@ -26,7 +26,9 @@ description: |
properties:
compatible:
- const: operating-points-v2-kryo-cpu
+ enum:
+ - operating-points-v2-krait-cpu
+ - operating-points-v2-kryo-cpu
nvmem-cells:
description: |
@@ -63,14 +65,15 @@ patternProperties:
5: MSM8996SG, speedbin 1
6: MSM8996SG, speedbin 2
7-31: unused
- enum: [0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7,
- 0x9, 0xd, 0xe, 0xf,
- 0x10, 0x20, 0x30, 0x70]
+ $ref: /schemas/types.yaml#/definitions/uint32
clock-latency-ns: true
required-opps: true
+ patternProperties:
+ '^opp-microvolt-speed[0-9]+-pvs[0-9]+$': true
+
required:
- opp-hz
--
2.39.2
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 02/18] dt-bindings: soc: qcom: merge qcom,saw2.txt into qcom,spm.yaml
2023-06-12 5:39 [PATCH 00/18] ARM: qcom: apq8064: support CPU frequency scaling Dmitry Baryshkov
2023-06-11 16:27 ` Christian Marangi
2023-06-12 5:39 ` [PATCH 01/18] dt-bindings: opp: opp-v2-kryo-cpu: support Qualcomm Krait SoCs Dmitry Baryshkov
@ 2023-06-12 5:39 ` Dmitry Baryshkov
2023-06-14 16:03 ` Krzysztof Kozlowski
2023-06-12 5:39 ` [PATCH 03/18] dt-bindings: soc: qcom: qcom,saw2: define optional regulator node Dmitry Baryshkov
` (15 subsequent siblings)
18 siblings, 1 reply; 36+ messages in thread
From: Dmitry Baryshkov @ 2023-06-12 5:39 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Ilia Lin, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki
Cc: linux-arm-msm, devicetree, linux-pm, linux-clk, Christian Marangi
The Qualcomm SPM / SAW2 device is described in two bindigns files:
arm/msm/qcom,saw2.txt and soc/qcom/qcom,spm.yaml. Merge the former into
the latter, adding detailed device node description. While we are at it,
also rename qcom,spm.yaml to qcom,saw2.yaml to follow the actual
compatible used for these devices.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../devicetree/bindings/arm/msm/qcom,saw2.txt | 58 -------------------
.../qcom/{qcom,spm.yaml => qcom,saw2.yaml} | 22 +++++--
2 files changed, 16 insertions(+), 64 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
rename Documentation/devicetree/bindings/soc/qcom/{qcom,spm.yaml => qcom,saw2.yaml} (68%)
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
deleted file mode 100644
index c0e3c3a42bea..000000000000
--- a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
+++ /dev/null
@@ -1,58 +0,0 @@
-SPM AVS Wrapper 2 (SAW2)
-
-The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the
-Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable
-power-controller that transitions a piece of hardware (like a processor or
-subsystem) into and out of low power modes via a direct connection to
-the PMIC. It can also be wired up to interact with other processors in the
-system, notifying them when a low power state is entered or exited.
-
-Multiple revisions of the SAW hardware are supported using these Device Nodes.
-SAW2 revisions differ in the register offset and configuration data. Also, the
-same revision of the SAW in different SoCs may have different configuration
-data due the differences in hardware capabilities. Hence the SoC name, the
-version of the SAW hardware in that SoC and the distinction between cpu (big
-or Little) or cache, may be needed to uniquely identify the SAW register
-configuration and initialization data. The compatible string is used to
-indicate this parameter.
-
-PROPERTIES
-
-- compatible:
- Usage: required
- Value type: <string>
- Definition: Must have
- "qcom,saw2"
- A more specific value could be one of:
- "qcom,apq8064-saw2-v1.1-cpu"
- "qcom,msm8226-saw2-v2.1-cpu"
- "qcom,msm8974-saw2-v2.1-cpu"
- "qcom,apq8084-saw2-v2.1-cpu"
-
-- reg:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: the first element specifies the base address and size of
- the register region. An optional second element specifies
- the base address and size of the alias register region.
-
-- regulator:
- Usage: optional
- Value type: boolean
- Definition: Indicates that this SPM device acts as a regulator device
- device for the core (CPU or Cache) the SPM is attached
- to.
-
-Example 1:
-
- power-controller@2099000 {
- compatible = "qcom,saw2";
- reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
- regulator;
- };
-
-Example 2:
- saw0: power-controller@f9089000 {
- compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
- reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
- };
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml
similarity index 68%
rename from Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml
rename to Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml
index 20c8cd38ff0d..a016242367b9 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml
@@ -1,18 +1,26 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
-$id: http://devicetree.org/schemas/soc/qcom/qcom,spm.yaml#
+$id: http://devicetree.org/schemas/soc/qcom/qcom,saw2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Qualcomm Subsystem Power Manager
+title: Qualcomm Subsystem Power Manager / SPM AVS Wrapper 2 (SAW2)
maintainers:
- Andy Gross <agross@kernel.org>
- Bjorn Andersson <bjorn.andersson@linaro.org>
description: |
- This binding describes the Qualcomm Subsystem Power Manager, used to control
- the peripheral logic surrounding the application cores in Qualcomm platforms.
+ The Qualcomm Subsystem Power Manager is used to control the peripheral logic
+ surrounding the application cores in Qualcomm platforms.
+
+ The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the
+ Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable
+ power-controller that transitions a piece of hardware (like a processor or
+ subsystem) into and out of low power modes via a direct connection to
+ the PMIC. It can also be wired up to interact with other processors in the
+ system, notifying them when a low power state is entered or exited.
+
properties:
compatible:
@@ -34,8 +42,10 @@ properties:
- const: qcom,saw2
reg:
- description: Base address and size of the SPM register region
- maxItems: 1
+ items:
+ - description: Base address and size of the SPM register region
+ - description: Base address and size of the alias register region
+ minItems: 1
required:
- compatible
--
2.39.2
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 03/18] dt-bindings: soc: qcom: qcom,saw2: define optional regulator node
2023-06-12 5:39 [PATCH 00/18] ARM: qcom: apq8064: support CPU frequency scaling Dmitry Baryshkov
` (2 preceding siblings ...)
2023-06-12 5:39 ` [PATCH 02/18] dt-bindings: soc: qcom: merge qcom,saw2.txt into qcom,spm.yaml Dmitry Baryshkov
@ 2023-06-12 5:39 ` Dmitry Baryshkov
2023-06-14 16:05 ` Krzysztof Kozlowski
2023-06-12 5:39 ` [PATCH 04/18] dt-bindings: clock: qcom,krait-cc: Krait core clock controller Dmitry Baryshkov
` (14 subsequent siblings)
18 siblings, 1 reply; 36+ messages in thread
From: Dmitry Baryshkov @ 2023-06-12 5:39 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Ilia Lin, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki
Cc: linux-arm-msm, devicetree, linux-pm, linux-clk, Christian Marangi
The SAW2 device can optionally provide a voltage regulator supplying the
CPU core, cluster or L2 cache. Describe it in the device bindings.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../devicetree/bindings/soc/qcom/qcom,saw2.yaml | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml
index a016242367b9..b809a9cc0916 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml
@@ -47,6 +47,10 @@ properties:
- description: Base address and size of the alias register region
minItems: 1
+ regulator:
+ $ref: /schemas/regulator/regulator.yaml#
+ description: corresponding core, cluster or cache voltage supply regulator
+
required:
- compatible
- reg
@@ -92,4 +96,17 @@ examples:
reg = <0x17912000 0x1000>;
};
+ - |
+ /*
+ * Example 3: SAW2 with the bundled regulator definition.
+ */
+ power-manager@2089000 {
+ compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
+ reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
+
+ regulator {
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1300000>;
+ };
+ };
...
--
2.39.2
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 04/18] dt-bindings: clock: qcom,krait-cc: Krait core clock controller
2023-06-12 5:39 [PATCH 00/18] ARM: qcom: apq8064: support CPU frequency scaling Dmitry Baryshkov
` (3 preceding siblings ...)
2023-06-12 5:39 ` [PATCH 03/18] dt-bindings: soc: qcom: qcom,saw2: define optional regulator node Dmitry Baryshkov
@ 2023-06-12 5:39 ` Dmitry Baryshkov
[not found] ` <3ce1bd9b0cb23e4e60b093327e705d69.sboyd@kernel.org>
2023-06-12 5:39 ` [PATCH 05/18] clk: qcom: krait-cc: rewrite driver to use clk_hw instead of clk Dmitry Baryshkov
` (13 subsequent siblings)
18 siblings, 1 reply; 36+ messages in thread
From: Dmitry Baryshkov @ 2023-06-12 5:39 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Ilia Lin, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki
Cc: linux-arm-msm, devicetree, linux-pm, linux-clk, Christian Marangi
Define bindings for the Qualcomm Krait CPU and L2 clock controller. This
device is used on old Qualcomm SoCs (APQ8064, MSM8960) and supports up
to 4 core clocks and a separate L2 clock. Furthermore, L2 clock is
represented as the interconnect to facilitate L2 frequency scaling
together with scaling the CPU frequencies.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
include/dt-bindings/clock/qcom,krait-cc.h | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
create mode 100644 include/dt-bindings/clock/qcom,krait-cc.h
diff --git a/include/dt-bindings/clock/qcom,krait-cc.h b/include/dt-bindings/clock/qcom,krait-cc.h
new file mode 100644
index 000000000000..c3542b6d73e2
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,krait-cc.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2023 Linaro Ltd. All rights reserved.
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_KRAIT_CC_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_KRAIT_CC_H
+
+#define KRAIT_CPU_0 0
+#define KRAIT_CPU_1 1
+#define KRAIT_CPU_2 2
+#define KRAIT_CPU_3 3
+#define KRAIT_L2 4
+
+#define KRAIT_NUM_CLOCKS 5
+
+#define MASTER_KRAIT_L2 0
+#define SLAVE_KRAIT_L2 1
+
+#endif
--
2.39.2
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 05/18] clk: qcom: krait-cc: rewrite driver to use clk_hw instead of clk
2023-06-12 5:39 [PATCH 00/18] ARM: qcom: apq8064: support CPU frequency scaling Dmitry Baryshkov
` (4 preceding siblings ...)
2023-06-12 5:39 ` [PATCH 04/18] dt-bindings: clock: qcom,krait-cc: Krait core clock controller Dmitry Baryshkov
@ 2023-06-12 5:39 ` Dmitry Baryshkov
2023-06-12 5:39 ` [PATCH 06/18] clk: qcom: krait-cc: export L2 clock as an interconnect Dmitry Baryshkov
` (12 subsequent siblings)
18 siblings, 0 replies; 36+ messages in thread
From: Dmitry Baryshkov @ 2023-06-12 5:39 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Ilia Lin, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki
Cc: linux-arm-msm, devicetree, linux-pm, linux-clk, Christian Marangi
The krait-cc driver still uses struct clk internally. Rewrite it to
allocate and register struct clk_hw instead.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/clk/qcom/krait-cc.c | 122 ++++++++++++++++--------------------
1 file changed, 54 insertions(+), 68 deletions(-)
diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c
index 410ae8390f1c..2ce38024dc0d 100644
--- a/drivers/clk/qcom/krait-cc.c
+++ b/drivers/clk/qcom/krait-cc.c
@@ -235,7 +235,7 @@ krait_add_pri_mux(struct device *dev, struct clk_hw *hfpll_div, struct clk_hw *s
.parent_data = p_data,
.num_parents = ARRAY_SIZE(p_data),
.ops = &krait_mux_clk_ops,
- .flags = CLK_SET_RATE_PARENT,
+ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
};
struct clk_hw *clk;
char *hfpll_name;
@@ -324,19 +324,6 @@ static struct clk_hw *krait_add_clks(struct device *dev, int id, bool unique_aux
return pri_mux;
}
-static struct clk *krait_of_get(struct of_phandle_args *clkspec, void *data)
-{
- unsigned int idx = clkspec->args[0];
- struct clk **clks = data;
-
- if (idx >= clks_max) {
- pr_err("%s: invalid clock index %d\n", __func__, idx);
- return ERR_PTR(-EINVAL);
- }
-
- return clks[idx] ? : ERR_PTR(-ENODEV);
-}
-
static const struct of_device_id krait_cc_match_table[] = {
{ .compatible = "qcom,krait-cc-v1", (void *)1UL },
{ .compatible = "qcom,krait-cc-v2" },
@@ -344,60 +331,81 @@ static const struct of_device_id krait_cc_match_table[] = {
};
MODULE_DEVICE_TABLE(of, krait_cc_match_table);
+static int krait_clk_reinit(struct clk_hw *hw, int cpu)
+{
+ struct clk *clk;
+ unsigned long cur_rate, aux_rate;
+ char name[5]; /* CPUn */
+
+ if (cpu == -1)
+ strcpy(name, "L2");
+ else
+ snprintf(name, sizeof(name), "CPU%d", cpu);
+
+ clk = clk_hw_get_clk(hw, clk_hw_get_name(hw));
+ if (IS_ERR(clk))
+ return PTR_ERR(clk);
+
+ aux_rate = 384000000;
+
+ cur_rate = clk_get_rate(clk);
+ if (cur_rate < aux_rate) {
+ pr_info("%s @ Undefined rate %lu. Forcing new rate.\n",
+ name, cur_rate / 1000);
+ cur_rate = aux_rate;
+ }
+
+ clk_set_rate(clk, aux_rate);
+ clk_set_rate(clk, 2);
+ clk_set_rate(clk, cur_rate);
+ pr_info("%s @ %lu KHz\n", name, clk_get_rate(clk) / 1000);
+
+ clk_put(clk);
+
+ return 0;
+}
+
static int krait_cc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
const struct of_device_id *id;
- unsigned long cur_rate, aux_rate;
int cpu;
- struct clk_hw *mux, *l2_pri_mux;
- struct clk *clk, **clks;
+ struct clk_hw *clk;
+ struct clk_hw_onecell_data *clks;
id = of_match_device(krait_cc_match_table, dev);
if (!id)
return -ENODEV;
/* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */
- clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1);
+ clk = clk_hw_register_fixed_rate(dev, "qsb", NULL, 0, 1);
if (IS_ERR(clk))
return PTR_ERR(clk);
if (!id->data) {
- clk = clk_register_fixed_factor(dev, "acpu_aux",
- "gpll0_vote", 0, 1, 2);
+ clk = clk_hw_register_fixed_factor(dev, "acpu_aux", "gpll0_vote", 0, 1, 2);
if (IS_ERR(clk))
return PTR_ERR(clk);
}
/* Krait configurations have at most 4 CPUs and one L2 */
- clks = devm_kcalloc(dev, clks_max, sizeof(*clks), GFP_KERNEL);
+ clks = devm_kzalloc(dev, struct_size(clks, hws, clks_max), GFP_KERNEL);
if (!clks)
return -ENOMEM;
+ clks->num = clks_max;
+
for_each_possible_cpu(cpu) {
- mux = krait_add_clks(dev, cpu, id->data);
- if (IS_ERR(mux))
- return PTR_ERR(mux);
- clks[cpu] = mux->clk;
+ clk = krait_add_clks(dev, cpu, id->data);
+ if (IS_ERR(clk))
+ return PTR_ERR(clk);
+ clks->hws[cpu] = clk;
}
- l2_pri_mux = krait_add_clks(dev, -1, id->data);
- if (IS_ERR(l2_pri_mux))
- return PTR_ERR(l2_pri_mux);
- clks[l2_mux] = l2_pri_mux->clk;
-
- /*
- * We don't want the CPU or L2 clocks to be turned off at late init
- * if CPUFREQ or HOTPLUG configs are disabled. So, bump up the
- * refcount of these clocks. Any cpufreq/hotplug manager can assume
- * that the clocks have already been prepared and enabled by the time
- * they take over.
- */
- for_each_online_cpu(cpu) {
- clk_prepare_enable(clks[l2_mux]);
- WARN(clk_prepare_enable(clks[cpu]),
- "Unable to turn on CPU%d clock", cpu);
- }
+ clk = krait_add_clks(dev, -1, id->data);
+ if (IS_ERR(clk))
+ return PTR_ERR(clk);
+ clks->hws[l2_mux] = clk;
/*
* Force reinit of HFPLLs and muxes to overwrite any potential
@@ -410,33 +418,11 @@ static int krait_cc_probe(struct platform_device *pdev)
* two different rates to force a HFPLL reinit under all
* circumstances.
*/
- cur_rate = clk_get_rate(clks[l2_mux]);
- aux_rate = 384000000;
- if (cur_rate < aux_rate) {
- pr_info("L2 @ Undefined rate. Forcing new rate.\n");
- cur_rate = aux_rate;
- }
- clk_set_rate(clks[l2_mux], aux_rate);
- clk_set_rate(clks[l2_mux], 2);
- clk_set_rate(clks[l2_mux], cur_rate);
- pr_info("L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000);
- for_each_possible_cpu(cpu) {
- clk = clks[cpu];
- cur_rate = clk_get_rate(clk);
- if (cur_rate < aux_rate) {
- pr_info("CPU%d @ Undefined rate. Forcing new rate.\n", cpu);
- cur_rate = aux_rate;
- }
-
- clk_set_rate(clk, aux_rate);
- clk_set_rate(clk, 2);
- clk_set_rate(clk, cur_rate);
- pr_info("CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000);
- }
+ krait_clk_reinit(clks->hws[l2_mux], -1);
+ for_each_possible_cpu(cpu)
+ krait_clk_reinit(clks->hws[cpu], cpu);
- of_clk_add_provider(dev->of_node, krait_of_get, clks);
-
- return 0;
+ return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clks);
}
static struct platform_driver krait_cc_driver = {
--
2.39.2
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 06/18] clk: qcom: krait-cc: export L2 clock as an interconnect
2023-06-12 5:39 [PATCH 00/18] ARM: qcom: apq8064: support CPU frequency scaling Dmitry Baryshkov
` (5 preceding siblings ...)
2023-06-12 5:39 ` [PATCH 05/18] clk: qcom: krait-cc: rewrite driver to use clk_hw instead of clk Dmitry Baryshkov
@ 2023-06-12 5:39 ` Dmitry Baryshkov
2023-06-12 5:39 ` [PATCH 07/18] soc: qcom: spm: add support for voltage regulator Dmitry Baryshkov
` (11 subsequent siblings)
18 siblings, 0 replies; 36+ messages in thread
From: Dmitry Baryshkov @ 2023-06-12 5:39 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Ilia Lin, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki
Cc: linux-arm-msm, devicetree, linux-pm, linux-clk, Christian Marangi
While scaling the CPU frequency, L2 frequency should also be scaled
following the CPU frequency. To simplify such scaling, export the L2
clock as an interconnect, to facilitate aggregating CPU votes and
selecting the maximum vote.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/clk/qcom/Kconfig | 1 +
drivers/clk/qcom/krait-cc.c | 75 +++++++++++++++++++++++++++++--------
2 files changed, 60 insertions(+), 16 deletions(-)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 97f23f978343..3d56263ce494 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -1065,6 +1065,7 @@ config KRAITCC
tristate "Krait Clock Controller"
depends on ARM
select KRAIT_CLOCKS
+ select INTERCONNECT_CLK if INTERCONNECT
help
Support for the Krait CPU clocks on Qualcomm devices.
Say Y if you want to support CPU frequency scaling.
diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c
index 2ce38024dc0d..f16321fc6dd7 100644
--- a/drivers/clk/qcom/krait-cc.c
+++ b/drivers/clk/qcom/krait-cc.c
@@ -11,19 +11,13 @@
#include <linux/of_device.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
+#include <linux/interconnect-clk.h>
+#include <linux/interconnect-provider.h>
#include <linux/slab.h>
-#include "clk-krait.h"
-
-enum {
- cpu0_mux = 0,
- cpu1_mux,
- cpu2_mux,
- cpu3_mux,
- l2_mux,
+#include <dt-bindings/clock/qcom,krait-cc.h>
- clks_max,
-};
+#include "clk-krait.h"
static unsigned int sec_mux_map[] = {
2,
@@ -365,11 +359,54 @@ static int krait_clk_reinit(struct clk_hw *hw, int cpu)
return 0;
}
+#ifdef CONFIG_INTERCONNECT
+
+/* Random ID that doesn't clash with main qnoc and OSM */
+#define L2_MASTER_NODE 2000
+
+static int krait_cc_icc_register(struct platform_device *pdev, struct clk_hw *l2_hw)
+{
+ struct device *dev = &pdev->dev;
+ struct clk *clk = devm_clk_hw_get_clk(dev, l2_hw, "l2");
+ const struct icc_clk_data data[] = {
+ { .clk = clk, .name = "l2", },
+ };
+ struct icc_provider *provider;
+
+ provider = icc_clk_register(dev, L2_MASTER_NODE, ARRAY_SIZE(data), data);
+ if (IS_ERR(provider))
+ return PTR_ERR(provider);
+
+ platform_set_drvdata(pdev, provider);
+
+ return 0;
+}
+
+static int krait_cc_icc_remove(struct platform_device *pdev)
+{
+ struct icc_provider *provider = platform_get_drvdata(pdev);
+
+ icc_clk_unregister(provider);
+
+ return 0;
+}
+#define krait_cc_icc_sync_state icc_sync_state
+#else
+static int krait_cc_icc_register(struct platform_device *pdev, struct clk_hw *l2_hw)
+{
+ dev_warn(&pdev->dev, "CONFIG_INTERCONNECT is disabled, L2 clock is fixed\n");
+
+ return 0;
+}
+#define krait_cc_icc_remove(pdev) (0)
+#define krait_cc_icc_sync_state NULL
+#endif
+
static int krait_cc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
const struct of_device_id *id;
- int cpu;
+ int cpu, ret;
struct clk_hw *clk;
struct clk_hw_onecell_data *clks;
@@ -389,11 +426,11 @@ static int krait_cc_probe(struct platform_device *pdev)
}
/* Krait configurations have at most 4 CPUs and one L2 */
- clks = devm_kzalloc(dev, struct_size(clks, hws, clks_max), GFP_KERNEL);
+ clks = devm_kzalloc(dev, struct_size(clks, hws, KRAIT_NUM_CLOCKS), GFP_KERNEL);
if (!clks)
return -ENOMEM;
- clks->num = clks_max;
+ clks->num = KRAIT_NUM_CLOCKS;
for_each_possible_cpu(cpu) {
clk = krait_add_clks(dev, cpu, id->data);
@@ -405,7 +442,7 @@ static int krait_cc_probe(struct platform_device *pdev)
clk = krait_add_clks(dev, -1, id->data);
if (IS_ERR(clk))
return PTR_ERR(clk);
- clks->hws[l2_mux] = clk;
+ clks->hws[KRAIT_L2] = clk;
/*
* Force reinit of HFPLLs and muxes to overwrite any potential
@@ -418,18 +455,24 @@ static int krait_cc_probe(struct platform_device *pdev)
* two different rates to force a HFPLL reinit under all
* circumstances.
*/
- krait_clk_reinit(clks->hws[l2_mux], -1);
+ krait_clk_reinit(clks->hws[KRAIT_L2], -1);
for_each_possible_cpu(cpu)
krait_clk_reinit(clks->hws[cpu], cpu);
- return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clks);
+ ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clks);
+ if (ret)
+ return ret;
+
+ return krait_cc_icc_register(pdev, clks->hws[KRAIT_L2]);
}
static struct platform_driver krait_cc_driver = {
.probe = krait_cc_probe,
+ .remove = krait_cc_icc_remove,
.driver = {
.name = "krait-cc",
.of_match_table = krait_cc_match_table,
+ .sync_state = krait_cc_icc_sync_state,
},
};
module_platform_driver(krait_cc_driver);
--
2.39.2
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 07/18] soc: qcom: spm: add support for voltage regulator
2023-06-12 5:39 [PATCH 00/18] ARM: qcom: apq8064: support CPU frequency scaling Dmitry Baryshkov
` (6 preceding siblings ...)
2023-06-12 5:39 ` [PATCH 06/18] clk: qcom: krait-cc: export L2 clock as an interconnect Dmitry Baryshkov
@ 2023-06-12 5:39 ` Dmitry Baryshkov
2023-06-12 5:39 ` [PATCH 08/18] cpufreq: qcom-nvmem: also accept operating-points-v2-krait-cpu Dmitry Baryshkov
` (10 subsequent siblings)
18 siblings, 0 replies; 36+ messages in thread
From: Dmitry Baryshkov @ 2023-06-12 5:39 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Ilia Lin, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki
Cc: linux-arm-msm, devicetree, linux-pm, linux-clk, Christian Marangi
The SPM / SAW2 device also provides a voltage regulator functionality
with optional AVS (Adaptive Voltage Scaling) support. The exact register
sequence and voltage ranges differs from device to device.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/soc/qcom/spm.c | 205 ++++++++++++++++++++++++++++++++++++++++-
include/soc/qcom/spm.h | 9 ++
2 files changed, 212 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c
index a6cbeb40831b..3c16a7e1710c 100644
--- a/drivers/soc/qcom/spm.c
+++ b/drivers/soc/qcom/spm.c
@@ -9,19 +9,31 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/linear_range.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
+#include <linux/bitfield.h>
#include <linux/err.h>
#include <linux/platform_device.h>
+#include <linux/regulator/driver.h>
+#include <linux/smp.h>
#include <soc/qcom/spm.h>
+#define FIELD_SET(current, mask, val) \
+ (((current) & ~(mask)) | FIELD_PREP((mask), (val)))
+
#define SPM_CTL_INDEX 0x7f
#define SPM_CTL_INDEX_SHIFT 4
#define SPM_CTL_EN BIT(0)
+#define SPM_1_1_AVS_CTL_AVS_ENABLED BIT(27)
+#define SPM_AVS_CTL_MIN_VLVL (0x3f << 10)
+#define SPM_AVS_CTL_MAX_VLVL (0x3f << 17)
+
enum spm_reg {
SPM_REG_CFG,
SPM_REG_SPM_CTL,
@@ -31,10 +43,12 @@ enum spm_reg {
SPM_REG_PMIC_DATA_1,
SPM_REG_VCTL,
SPM_REG_SEQ_ENTRY,
- SPM_REG_SPM_STS,
+ SPM_REG_STS0,
+ SPM_REG_STS1,
SPM_REG_PMIC_STS,
SPM_REG_AVS_CTL,
SPM_REG_AVS_LIMIT,
+ SPM_REG_RST,
SPM_REG_NR,
};
@@ -171,6 +185,10 @@ static const struct spm_reg_data spm_reg_8226_cpu = {
static const u16 spm_reg_offset_v1_1[SPM_REG_NR] = {
[SPM_REG_CFG] = 0x08,
+ [SPM_REG_STS0] = 0x0c,
+ [SPM_REG_STS1] = 0x10,
+ [SPM_REG_VCTL] = 0x14,
+ [SPM_REG_AVS_CTL] = 0x18,
[SPM_REG_SPM_CTL] = 0x20,
[SPM_REG_PMIC_DLY] = 0x24,
[SPM_REG_PMIC_DATA_0] = 0x28,
@@ -178,7 +196,12 @@ static const u16 spm_reg_offset_v1_1[SPM_REG_NR] = {
[SPM_REG_SEQ_ENTRY] = 0x80,
};
+static void smp_set_vdd_v1_1(void *data);
+
/* SPM register data for 8064 */
+static struct linear_range spm_v1_1_regulator_range =
+ REGULATOR_LINEAR_RANGE(700000, 0, 56, 12500);
+
static const struct spm_reg_data spm_reg_8064_cpu = {
.reg_offset = spm_reg_offset_v1_1,
.spm_cfg = 0x1F,
@@ -189,6 +212,10 @@ static const struct spm_reg_data spm_reg_8064_cpu = {
0x10, 0x54, 0x30, 0x0C, 0x24, 0x30, 0x0F },
.start_index[PM_SLEEP_MODE_STBY] = 0,
.start_index[PM_SLEEP_MODE_SPC] = 2,
+ .set_vdd = smp_set_vdd_v1_1,
+ .range = &spm_v1_1_regulator_range,
+ .init_uV = 1300000,
+ .ramp_delay = 1250,
};
static inline void spm_register_write(struct spm_driver_data *drv,
@@ -240,6 +267,179 @@ void spm_set_low_power_mode(struct spm_driver_data *drv,
spm_register_write_sync(drv, SPM_REG_SPM_CTL, ctl_val);
}
+static int spm_set_voltage_sel(struct regulator_dev *rdev, unsigned int selector)
+{
+ struct spm_driver_data *drv = rdev_get_drvdata(rdev);
+
+ drv->volt_sel = selector;
+
+ /* Always do the SAW register writes on the corresponding CPU */
+ return smp_call_function_single(drv->reg_cpu, drv->reg_data->set_vdd, drv, true);
+}
+
+static int spm_get_voltage_sel(struct regulator_dev *rdev)
+{
+ struct spm_driver_data *drv = rdev_get_drvdata(rdev);
+
+ return drv->volt_sel;
+}
+
+static const struct regulator_ops spm_reg_ops = {
+ .set_voltage_sel = spm_set_voltage_sel,
+ .get_voltage_sel = spm_get_voltage_sel,
+ .list_voltage = regulator_list_voltage_linear_range,
+ .set_voltage_time_sel = regulator_set_voltage_time_sel,
+};
+
+static void smp_set_vdd_v1_1(void *data)
+{
+ struct spm_driver_data *drv = data;
+ unsigned int vlevel = drv->volt_sel;
+ unsigned int vctl, data0, data1, avs_ctl, sts;
+ bool avs_enabled;
+
+ vlevel |= 0x80; /* band */
+
+ avs_ctl = spm_register_read(drv, SPM_REG_AVS_CTL);
+ vctl = spm_register_read(drv, SPM_REG_VCTL);
+ data0 = spm_register_read(drv, SPM_REG_PMIC_DATA_0);
+ data1 = spm_register_read(drv, SPM_REG_PMIC_DATA_1);
+
+ avs_enabled = avs_ctl & SPM_1_1_AVS_CTL_AVS_ENABLED;
+
+ /* If AVS is enabled, switch it off during the voltage change */
+ if (avs_enabled) {
+ avs_ctl &= ~SPM_1_1_AVS_CTL_AVS_ENABLED;
+ spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl);
+ }
+
+ /* Kick the state machine back to idle */
+ spm_register_write(drv, SPM_REG_RST, 1);
+
+ vctl = FIELD_SET(vctl, 0xff, vlevel);
+ data0 = FIELD_SET(data0, 0xff, vlevel);
+ data1 = FIELD_SET(data1, 0x3f, vlevel);
+ data1 = FIELD_SET(data1, 0x3f << 16, vlevel);
+
+ spm_register_write(drv, SPM_REG_VCTL, vctl);
+ spm_register_write(drv, SPM_REG_PMIC_DATA_0, data0);
+ spm_register_write(drv, SPM_REG_PMIC_DATA_1, data1);
+
+ if (read_poll_timeout_atomic(spm_register_read,
+ sts, sts == vlevel,
+ 1, 200, false,
+ drv, SPM_REG_STS1)) {
+ dev_err_ratelimited(drv->dev, "timeout setting the voltage (%x %x)!\n", sts, vlevel);
+ goto enable_avs;
+ }
+
+ if (avs_enabled) {
+ unsigned int max_avs = vlevel & 0x3f;
+ unsigned int min_avs = max(max_avs, 4U) - 4;
+ avs_ctl = FIELD_SET(avs_ctl, SPM_AVS_CTL_MIN_VLVL, min_avs);
+ avs_ctl = FIELD_SET(avs_ctl, SPM_AVS_CTL_MAX_VLVL, max_avs);
+ spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl);
+ }
+
+enable_avs:
+ if (avs_enabled) {
+ avs_ctl |= SPM_1_1_AVS_CTL_AVS_ENABLED;
+ spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl);
+ }
+}
+
+static int spm_get_cpu(struct device *dev)
+{
+ int cpu;
+ bool found;
+
+ for_each_possible_cpu(cpu) {
+ struct device_node *cpu_node, *saw_node;
+
+ cpu_node = of_cpu_device_node_get(cpu);
+ if (!cpu_node)
+ continue;
+
+ saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0);
+ found = (saw_node == dev->of_node);
+ of_node_put(saw_node);
+ of_node_put(cpu_node);
+
+ if (found)
+ return cpu;
+ }
+
+ /* L2 SPM is not bound to any CPU, tie it to CPU0 */
+
+ return 0;
+}
+
+#ifdef CONFIG_REGULATOR
+static int spm_register_regulator(struct device *dev, struct spm_driver_data *drv)
+{
+ struct regulator_config config = {
+ .dev = dev,
+ .driver_data = drv,
+ };
+ struct regulator_desc *rdesc;
+ struct regulator_dev *rdev;
+ int ret;
+ bool found;
+
+ if (!drv->reg_data->set_vdd)
+ return 0;
+
+ rdesc = devm_kzalloc(dev, sizeof(*rdesc), GFP_KERNEL);
+ if (!rdesc)
+ return -ENOMEM;
+
+ rdesc->name = "spm";
+ rdesc->of_match = of_match_ptr("regulator");
+ rdesc->type = REGULATOR_VOLTAGE;
+ rdesc->owner = THIS_MODULE;
+ rdesc->ops = &spm_reg_ops;
+
+ rdesc->linear_ranges = drv->reg_data->range;
+ rdesc->n_linear_ranges = 1;
+ rdesc->n_voltages = rdesc->linear_ranges[rdesc->n_linear_ranges - 1].max_sel + 1;
+ rdesc->ramp_delay = drv->reg_data->ramp_delay;
+
+ drv->reg_cpu = spm_get_cpu(dev);
+ dev_dbg(dev, "SAW2 bound to CPU %d\n", drv->reg_cpu);
+
+ /*
+ * Program initial voltage, otherwise registration will also try
+ * setting the voltage, which might result in undervolting the CPU.
+ */
+ drv->volt_sel = DIV_ROUND_UP(drv->reg_data->init_uV - rdesc->min_uV,
+ rdesc->uV_step);
+ ret = linear_range_get_selector_high(drv->reg_data->range,
+ drv->reg_data->init_uV,
+ &drv->volt_sel,
+ &found);
+ if (ret) {
+ dev_err(dev, "Initial uV value out of bounds\n");
+ return ret;
+ }
+
+ /* Always do the SAW register writes on the corresponding CPU */
+ smp_call_function_single(drv->reg_cpu, drv->reg_data->set_vdd, drv, true);
+
+ rdev = devm_regulator_register(dev, rdesc, &config);
+ if (IS_ERR(rdev)) {
+ dev_err(dev, "failed to register regulator\n");
+ return PTR_ERR(rdev);
+ }
+
+ return 0;
+}
+#else
+static int spm_register_regulator(struct device *dev, struct spm_driver_data *drv)
+{
+ return 0;
+}
+#endif
+
static const struct of_device_id spm_match_table[] = {
{ .compatible = "qcom,sdm660-gold-saw2-v4.1-l2",
.data = &spm_reg_660_gold_l2 },
@@ -292,6 +492,7 @@ static int spm_dev_probe(struct platform_device *pdev)
return -ENODEV;
drv->reg_data = match_id->data;
+ drv->dev = &pdev->dev;
platform_set_drvdata(pdev, drv);
/* Write the SPM sequences first.. */
@@ -319,7 +520,7 @@ static int spm_dev_probe(struct platform_device *pdev)
if (drv->reg_data->reg_offset[SPM_REG_SPM_CTL])
spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY);
- return 0;
+ return spm_register_regulator(&pdev->dev, drv);
}
static struct platform_driver spm_driver = {
diff --git a/include/soc/qcom/spm.h b/include/soc/qcom/spm.h
index 4951f9d8b0bd..9859ebe42003 100644
--- a/include/soc/qcom/spm.h
+++ b/include/soc/qcom/spm.h
@@ -30,11 +30,20 @@ struct spm_reg_data {
u32 avs_limit;
u8 seq[MAX_SEQ_DATA];
u8 start_index[PM_SLEEP_MODE_NR];
+
+ smp_call_func_t set_vdd;
+ /* for now we support only a single range */
+ struct linear_range *range;
+ unsigned int ramp_delay;
+ unsigned int init_uV;
};
struct spm_driver_data {
void __iomem *reg_base;
const struct spm_reg_data *reg_data;
+ struct device *dev;
+ unsigned int volt_sel;
+ int reg_cpu;
};
void spm_set_low_power_mode(struct spm_driver_data *drv,
--
2.39.2
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 08/18] cpufreq: qcom-nvmem: also accept operating-points-v2-krait-cpu
2023-06-12 5:39 [PATCH 00/18] ARM: qcom: apq8064: support CPU frequency scaling Dmitry Baryshkov
` (7 preceding siblings ...)
2023-06-12 5:39 ` [PATCH 07/18] soc: qcom: spm: add support for voltage regulator Dmitry Baryshkov
@ 2023-06-12 5:39 ` Dmitry Baryshkov
2023-06-12 5:39 ` [PATCH 09/18] cpufreq: qcom-nvmem: Add support for voltage scaling Dmitry Baryshkov
` (9 subsequent siblings)
18 siblings, 0 replies; 36+ messages in thread
From: Dmitry Baryshkov @ 2023-06-12 5:39 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Ilia Lin, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki
Cc: linux-arm-msm, devicetree, linux-pm, linux-clk, Christian Marangi
the qcom-cpufreq-nvmem driver attempts to support both Qualcomm Kryo
(newer 64-bit ARMv8 cores) and Krait (older 32-bit ARMv7 cores). It
makes no sense to use 'operating-points-v2-kryo-cpu' compatibility node
for the Krait cores. Add support for 'operating-points-v2-krait-cpu'
compatibility string.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/cpufreq/qcom-cpufreq-nvmem.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
index a88b6fe5db50..fee9736f7326 100644
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -238,7 +238,8 @@ static int qcom_cpufreq_probe(struct platform_device *pdev)
if (!np)
return -ENOENT;
- ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu");
+ ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu") ||
+ of_device_is_compatible(np, "operating-points-v2-krait-cpu");
if (!ret) {
of_node_put(np);
return -ENOENT;
--
2.39.2
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 09/18] cpufreq: qcom-nvmem: Add support for voltage scaling
2023-06-12 5:39 [PATCH 00/18] ARM: qcom: apq8064: support CPU frequency scaling Dmitry Baryshkov
` (8 preceding siblings ...)
2023-06-12 5:39 ` [PATCH 08/18] cpufreq: qcom-nvmem: also accept operating-points-v2-krait-cpu Dmitry Baryshkov
@ 2023-06-12 5:39 ` Dmitry Baryshkov
2023-06-12 5:39 ` [PATCH 10/18] cpufreq: qcom-nvmem: drop pvs_ver for format a fuses Dmitry Baryshkov
` (8 subsequent siblings)
18 siblings, 0 replies; 36+ messages in thread
From: Dmitry Baryshkov @ 2023-06-12 5:39 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Ilia Lin, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki
Cc: linux-arm-msm, devicetree, linux-pm, linux-clk, Christian Marangi
If requested by the platform, scale voltages according to data specified
in the OPP tables.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/cpufreq/qcom-cpufreq-nvmem.c | 115 ++++++++++++++++++++++++++-
1 file changed, 114 insertions(+), 1 deletion(-)
diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
index fee9736f7326..18d6e6ed1bd0 100644
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -26,6 +26,7 @@
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/pm_opp.h>
+#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <linux/soc/qcom/smem.h>
@@ -39,6 +40,7 @@ struct qcom_cpufreq_match_data {
char **pvs_name,
struct qcom_cpufreq_drv *drv);
const char **genpd_names;
+ const char * const *regulator_names;
};
struct qcom_cpufreq_drv {
@@ -218,6 +220,110 @@ static const struct qcom_cpufreq_match_data match_data_qcs404 = {
.genpd_names = qcs404_genpd_names,
};
+#define NUM_SUPPLIES 2
+static int qcom_cpufreq_config_regulators(struct device *dev,
+ struct dev_pm_opp *old_opp,
+ struct dev_pm_opp *new_opp,
+ struct regulator **regulators,
+ unsigned int count)
+{
+ struct dev_pm_opp_supply supplies[NUM_SUPPLIES];
+ unsigned long old_freq, freq;
+ unsigned int i;
+ int ret;
+
+ if (WARN_ON_ONCE(count != NUM_SUPPLIES))
+ return -EINVAL;
+
+ ret = dev_pm_opp_get_supplies(new_opp, supplies);
+ if (WARN_ON(ret))
+ return ret;
+
+ old_freq = dev_pm_opp_get_freq(old_opp);
+ freq = dev_pm_opp_get_freq(new_opp);
+
+ WARN_ON(!old_freq || !freq);
+ if (freq > old_freq) {
+ for (i = 0; i < count; i++) {
+ struct regulator *reg = regulators[i];
+ struct dev_pm_opp_supply *supply = &supplies[i];
+
+ dev_dbg(dev, "%s: voltages (mV): %lu %lu %lu\n", __func__,
+ supply->u_volt_min, supply->u_volt, supply->u_volt_max);
+
+ ret = regulator_set_voltage_triplet(reg,
+ supply->u_volt_min,
+ supply->u_volt,
+ supply->u_volt_max);
+ if (ret) {
+ dev_err(dev, "%s: failed to set voltage (%lu %lu %lu mV): %d\n",
+ __func__, supply->u_volt_min, supply->u_volt,
+ supply->u_volt_max, ret);
+ goto restore_backwards;
+ }
+ }
+ } else {
+ for (i = count; i > 0; i--) {
+ struct regulator *reg = regulators[i - 1];
+ struct dev_pm_opp_supply *supply = &supplies[i - 1];
+
+ dev_dbg(dev, "%s: voltages (mV): %lu %lu %lu\n", __func__,
+ supply->u_volt_min, supply->u_volt, supply->u_volt_max);
+
+ ret = regulator_set_voltage_triplet(reg,
+ supply->u_volt_min,
+ supply->u_volt,
+ supply->u_volt_max);
+ if (ret) {
+ dev_err(dev, "%s: failed to set voltage (%lu %lu %lu mV): %d\n",
+ __func__, supply->u_volt_min, supply->u_volt,
+ supply->u_volt_max, ret);
+ goto restore_forward;
+ }
+ }
+ }
+
+ return 0;
+
+restore_backwards:
+
+ dev_pm_opp_get_supplies(old_opp, supplies);
+
+ for (; i > 0; i--) {
+ struct regulator *reg = regulators[i - 1];
+ struct dev_pm_opp_supply *supply = &supplies[i - 1];
+
+ dev_dbg(dev, "%s: voltages (mV): %lu %lu %lu\n", __func__,
+ supply->u_volt_min, supply->u_volt, supply->u_volt_max);
+
+ regulator_set_voltage_triplet(reg,
+ supply->u_volt_min,
+ supply->u_volt,
+ supply->u_volt_max);
+ }
+
+ return ret;
+
+restore_forward:
+
+ dev_pm_opp_get_supplies(old_opp, supplies);
+
+ for ( ; i < count; i++) {
+ struct regulator *reg = regulators[i];
+ struct dev_pm_opp_supply *supply = &supplies[i];
+
+ dev_dbg(dev, "%s: voltages (mV): %lu %lu %lu\n", __func__,
+ supply->u_volt_min, supply->u_volt, supply->u_volt_max);
+
+ regulator_set_voltage_triplet(reg,
+ supply->u_volt_min,
+ supply->u_volt,
+ supply->u_volt_max);
+ }
+
+ return ret;
+}
+
static int qcom_cpufreq_probe(struct platform_device *pdev)
{
struct qcom_cpufreq_drv *drv;
@@ -305,7 +411,14 @@ static int qcom_cpufreq_probe(struct platform_device *pdev)
config.virt_devs = NULL;
}
- if (config.supported_hw || config.genpd_names) {
+ if (drv->data->regulator_names) {
+ config.config_regulators = qcom_cpufreq_config_regulators;
+ config.regulator_names = drv->data->regulator_names;
+ }
+
+ if (config.supported_hw ||
+ config.genpd_names ||
+ config.regulator_names) {
drv->opp_tokens[cpu] = dev_pm_opp_set_config(cpu_dev, &config);
if (drv->opp_tokens[cpu] < 0) {
ret = drv->opp_tokens[cpu];
--
2.39.2
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 10/18] cpufreq: qcom-nvmem: drop pvs_ver for format a fuses
2023-06-12 5:39 [PATCH 00/18] ARM: qcom: apq8064: support CPU frequency scaling Dmitry Baryshkov
` (9 preceding siblings ...)
2023-06-12 5:39 ` [PATCH 09/18] cpufreq: qcom-nvmem: Add support for voltage scaling Dmitry Baryshkov
@ 2023-06-12 5:39 ` Dmitry Baryshkov
2023-06-12 5:39 ` [PATCH 11/18] cpufreq: qcom-nvmem: provide separate configuration data for apq8064 Dmitry Baryshkov
` (7 subsequent siblings)
18 siblings, 0 replies; 36+ messages in thread
From: Dmitry Baryshkov @ 2023-06-12 5:39 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Ilia Lin, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki
Cc: linux-arm-msm, devicetree, linux-pm, linux-clk, Christian Marangi
The fuses used on msm8960 / apq8064 / ipq806x families of devices do not
have the pvs version. Drop this argument from parsing function.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/cpufreq/qcom-cpufreq-nvmem.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
index 18d6e6ed1bd0..fc446acfda22 100644
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -52,7 +52,7 @@ struct qcom_cpufreq_drv {
static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev;
static void get_krait_bin_format_a(struct device *cpu_dev,
- int *speed, int *pvs, int *pvs_ver,
+ int *speed, int *pvs,
u8 *buf)
{
u32 pte_efuse;
@@ -183,7 +183,7 @@ static int qcom_cpufreq_krait_name_version(struct device *cpu_dev,
switch (len) {
case 4:
- get_krait_bin_format_a(cpu_dev, &speed, &pvs, &pvs_ver,
+ get_krait_bin_format_a(cpu_dev, &speed, &pvs,
speedbin);
break;
case 8:
--
2.39.2
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 11/18] cpufreq: qcom-nvmem: provide separate configuration data for apq8064
2023-06-12 5:39 [PATCH 00/18] ARM: qcom: apq8064: support CPU frequency scaling Dmitry Baryshkov
` (10 preceding siblings ...)
2023-06-12 5:39 ` [PATCH 10/18] cpufreq: qcom-nvmem: drop pvs_ver for format a fuses Dmitry Baryshkov
@ 2023-06-12 5:39 ` Dmitry Baryshkov
2023-06-12 5:39 ` [PATCH 12/18] ARM: dts: qcom: apq8064: rename SAW nodes to power-manager Dmitry Baryshkov
` (6 subsequent siblings)
18 siblings, 0 replies; 36+ messages in thread
From: Dmitry Baryshkov @ 2023-06-12 5:39 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Ilia Lin, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki
Cc: linux-arm-msm, devicetree, linux-pm, linux-clk, Christian Marangi
APQ8064 can scale core and memory voltages according to the frequency
needs. Rather than reusing the A/B format multiplexer, use a simple fuse
parsing function and configure required regulators.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/cpufreq/qcom-cpufreq-nvmem.c | 44 ++++++++++++++++++++++++++--
1 file changed, 42 insertions(+), 2 deletions(-)
diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
index fc446acfda22..e5fede594399 100644
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -206,6 +206,34 @@ static int qcom_cpufreq_krait_name_version(struct device *cpu_dev,
return ret;
}
+static int qcom_cpufreq_apq8064_name_version(struct device *cpu_dev,
+ struct nvmem_cell *speedbin_nvmem,
+ char **pvs_name,
+ struct qcom_cpufreq_drv *drv)
+{
+ int speed = 0, pvs = 0;
+ u8 *speedbin;
+ size_t len;
+ int ret = 0;
+
+ speedbin = nvmem_cell_read(speedbin_nvmem, &len);
+ if (IS_ERR(speedbin))
+ return PTR_ERR(speedbin);
+
+ if (len != 4)
+ return -EINVAL;
+
+ get_krait_bin_format_a(cpu_dev, &speed, &pvs, speedbin);
+
+ snprintf(*pvs_name, sizeof("speedXX-pvsXX"), "speed%d-pvs%d",
+ speed, pvs);
+
+ drv->versions = (1 << speed);
+
+ kfree(speedbin);
+ return ret;
+}
+
static const struct qcom_cpufreq_match_data match_data_kryo = {
.get_version = qcom_cpufreq_kryo_name_version,
};
@@ -220,7 +248,19 @@ static const struct qcom_cpufreq_match_data match_data_qcs404 = {
.genpd_names = qcs404_genpd_names,
};
-#define NUM_SUPPLIES 2
+static const char * apq8064_regulator_names[] = {
+ "vdd-mem",
+ "vdd-dig",
+ "vdd-core",
+ NULL
+};
+
+static const struct qcom_cpufreq_match_data match_data_apq8064 = {
+ .get_version = qcom_cpufreq_apq8064_name_version,
+ .regulator_names = apq8064_regulator_names,
+};
+
+#define NUM_SUPPLIES 3
static int qcom_cpufreq_config_regulators(struct device *dev,
struct dev_pm_opp *old_opp,
struct dev_pm_opp *new_opp,
@@ -477,7 +517,7 @@ static const struct of_device_id qcom_cpufreq_match_list[] __initconst = {
{ .compatible = "qcom,msm8996", .data = &match_data_kryo },
{ .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
{ .compatible = "qcom,ipq8064", .data = &match_data_krait },
- { .compatible = "qcom,apq8064", .data = &match_data_krait },
+ { .compatible = "qcom,apq8064", .data = &match_data_apq8064 },
{ .compatible = "qcom,msm8974", .data = &match_data_krait },
{ .compatible = "qcom,msm8960", .data = &match_data_krait },
{},
--
2.39.2
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 12/18] ARM: dts: qcom: apq8064: rename SAW nodes to power-manager
2023-06-12 5:39 [PATCH 00/18] ARM: qcom: apq8064: support CPU frequency scaling Dmitry Baryshkov
` (11 preceding siblings ...)
2023-06-12 5:39 ` [PATCH 11/18] cpufreq: qcom-nvmem: provide separate configuration data for apq8064 Dmitry Baryshkov
@ 2023-06-12 5:39 ` Dmitry Baryshkov
2023-06-12 5:39 ` [PATCH 13/18] ARM: dts: qcom: apq8064: declare SAW2 regulators Dmitry Baryshkov
` (5 subsequent siblings)
18 siblings, 0 replies; 36+ messages in thread
From: Dmitry Baryshkov @ 2023-06-12 5:39 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Ilia Lin, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki
Cc: linux-arm-msm, devicetree, linux-pm, linux-clk, Christian Marangi
Per the power-domain.yaml, the power-controller node name is reserved
for power-domain providers. Rename SAW2 nodes to 'power-manager', the
name which is suggested by qcom,spm.yaml
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index d2289205ff81..471eeca6a589 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -422,25 +422,25 @@ acc3: clock-controller@20b8000 {
#clock-cells = <0>;
};
- saw0: power-controller@2089000 {
+ saw0: power-manager@2089000 {
compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
regulator;
};
- saw1: power-controller@2099000 {
+ saw1: power-manager@2099000 {
compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
regulator;
};
- saw2: power-controller@20a9000 {
+ saw2: power-manager@20a9000 {
compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
regulator;
};
- saw3: power-controller@20b9000 {
+ saw3: power-manager@20b9000 {
compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
regulator;
--
2.39.2
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 13/18] ARM: dts: qcom: apq8064: declare SAW2 regulators
2023-06-12 5:39 [PATCH 00/18] ARM: qcom: apq8064: support CPU frequency scaling Dmitry Baryshkov
` (12 preceding siblings ...)
2023-06-12 5:39 ` [PATCH 12/18] ARM: dts: qcom: apq8064: rename SAW nodes to power-manager Dmitry Baryshkov
@ 2023-06-12 5:39 ` Dmitry Baryshkov
2023-06-12 5:39 ` [PATCH 14/18] ARM: dts: qcom: apq8064: add simple CPUFreq support Dmitry Baryshkov
` (4 subsequent siblings)
18 siblings, 0 replies; 36+ messages in thread
From: Dmitry Baryshkov @ 2023-06-12 5:39 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Ilia Lin, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki
Cc: linux-arm-msm, devicetree, linux-pm, linux-clk, Christian Marangi
The SAW2 (SPM and AVS Wrapper) among other things is yet another way to
handle CPU-related PMIC regulators. Provide a way to control voltage of
these regulators.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 24 ++++++++++++++++++++----
1 file changed, 20 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 471eeca6a589..1eb6d752ebae 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -425,25 +425,41 @@ acc3: clock-controller@20b8000 {
saw0: power-manager@2089000 {
compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
- regulator;
+
+ saw0_vreg: regulator {
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1300000>;
+ };
};
saw1: power-manager@2099000 {
compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
- regulator;
+
+ saw1_vreg: regulator {
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1300000>;
+ };
};
saw2: power-manager@20a9000 {
compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
- regulator;
+
+ saw2_vreg: regulator {
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1300000>;
+ };
};
saw3: power-manager@20b9000 {
compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
- regulator;
+
+ saw3_vreg: regulator {
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1300000>;
+ };
};
sps_sic_non_secure: sps-sic-non-secure@12100000 {
--
2.39.2
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 14/18] ARM: dts: qcom: apq8064: add simple CPUFreq support
2023-06-12 5:39 [PATCH 00/18] ARM: qcom: apq8064: support CPU frequency scaling Dmitry Baryshkov
` (13 preceding siblings ...)
2023-06-12 5:39 ` [PATCH 13/18] ARM: dts: qcom: apq8064: declare SAW2 regulators Dmitry Baryshkov
@ 2023-06-12 5:39 ` Dmitry Baryshkov
2023-06-12 5:39 ` [PATCH 15/18] ARM: dts: qcom: apq8064: provide voltage scaling tables Dmitry Baryshkov
` (3 subsequent siblings)
18 siblings, 0 replies; 36+ messages in thread
From: Dmitry Baryshkov @ 2023-06-12 5:39 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Ilia Lin, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki
Cc: linux-arm-msm, devicetree, linux-pm, linux-clk, Christian Marangi
Declare CPU frequency-scaling properties. Each CPU has its own clock,
how all CPUs have the same OPP table. Voltage scaling is not (yet)
enabled with this patch. It will be enabled later.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 169 ++++++++++++++++++++++++++++
1 file changed, 169 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 1eb6d752ebae..4ef13f3d702b 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -2,6 +2,7 @@
/dts-v1/;
#include <dt-bindings/clock/qcom,gcc-msm8960.h>
+#include <dt-bindings/clock/qcom,krait-cc.h>
#include <dt-bindings/clock/qcom,lcc-msm8960.h>
#include <dt-bindings/reset/qcom,gcc-msm8960.h>
#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
@@ -45,6 +46,12 @@ CPU0: cpu@0 {
qcom,acc = <&acc0>;
qcom,saw = <&saw0>;
cpu-idle-states = <&CPU_SPC>;
+ clocks = <&kraitcc KRAIT_CPU_0>;
+ clock-names = "cpu";
+ clock-latency = <100000>;
+ interconnects = <&kraitcc MASTER_KRAIT_L2 &kraitcc SLAVE_KRAIT_L2>;
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>;
};
CPU1: cpu@1 {
@@ -56,6 +63,12 @@ CPU1: cpu@1 {
qcom,acc = <&acc1>;
qcom,saw = <&saw1>;
cpu-idle-states = <&CPU_SPC>;
+ clocks = <&kraitcc KRAIT_CPU_1>;
+ clock-names = "cpu";
+ clock-latency = <100000>;
+ interconnects = <&kraitcc MASTER_KRAIT_L2 &kraitcc SLAVE_KRAIT_L2>;
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>;
};
CPU2: cpu@2 {
@@ -67,6 +80,12 @@ CPU2: cpu@2 {
qcom,acc = <&acc2>;
qcom,saw = <&saw2>;
cpu-idle-states = <&CPU_SPC>;
+ clocks = <&kraitcc KRAIT_CPU_2>;
+ clock-names = "cpu";
+ clock-latency = <100000>;
+ interconnects = <&kraitcc MASTER_KRAIT_L2 &kraitcc SLAVE_KRAIT_L2>;
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>;
};
CPU3: cpu@3 {
@@ -78,6 +97,12 @@ CPU3: cpu@3 {
qcom,acc = <&acc3>;
qcom,saw = <&saw3>;
cpu-idle-states = <&CPU_SPC>;
+ clocks = <&kraitcc KRAIT_CPU_3>;
+ clock-names = "cpu";
+ clock-latency = <100000>;
+ interconnects = <&kraitcc MASTER_KRAIT_L2 &kraitcc SLAVE_KRAIT_L2>;
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>;
};
L2: l2-cache {
@@ -97,6 +122,121 @@ CPU_SPC: spc {
};
};
+ cpu_opp_table: opp-table-cpu {
+ compatible = "operating-points-v2-krait-cpu";
+ nvmem-cells = <&speedbin_efuse>;
+
+ /*
+ * Voltage thresholds are <target min max>
+ */
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ opp-peak-kBps = <384000>;
+ opp-supported-hw = <0x4007>;
+ /*
+ * higher latency as it requires switching between
+ * clock sources
+ */
+ clock-latency-ns = <244144>;
+ };
+
+ opp-486000000 {
+ opp-hz = /bits/ 64 <486000000>;
+ opp-peak-kBps = <648000>;
+ opp-supported-hw = <0x4007>;
+ };
+
+ opp-594000000 {
+ opp-hz = /bits/ 64 <594000000>;
+ opp-peak-kBps = <648000>;
+ opp-supported-hw = <0x4007>;
+ };
+
+ opp-702000000 {
+ opp-hz = /bits/ 64 <702000000>;
+ opp-peak-kBps = <648000>;
+ opp-supported-hw = <0x4007>;
+ };
+
+ opp-810000000 {
+ opp-hz = /bits/ 64 <810000000>;
+ opp-peak-kBps = <648000>;
+ opp-supported-hw = <0x4007>;
+ };
+
+ opp-918000000 {
+ opp-hz = /bits/ 64 <918000000>;
+ opp-peak-kBps = <648000>;
+ opp-supported-hw = <0x4007>;
+ };
+
+ opp-1026000000 {
+ opp-hz = /bits/ 64 <1026000000>;
+ opp-peak-kBps = <648000>;
+ opp-supported-hw = <0x4007>;
+ };
+
+ opp-1134000000 {
+ opp-hz = /bits/ 64 <1134000000>;
+ opp-peak-kBps = <1134000>;
+ opp-supported-hw = <0x4007>;
+ };
+
+ opp-1242000000 {
+ opp-hz = /bits/ 64 <1242000000>;
+ opp-peak-kBps = <1134000>;
+ opp-supported-hw = <0x4007>;
+ };
+
+ opp-1350000000 {
+ opp-hz = /bits/ 64 <1350000000>;
+ opp-peak-kBps = <1134000>;
+ opp-supported-hw = <0x4007>;
+ };
+
+ opp-1458000000 {
+ opp-hz = /bits/ 64 <1458000000>;
+ opp-peak-kBps = <1134000>;
+ opp-supported-hw = <0x4007>;
+ };
+
+ opp-1512000000 {
+ opp-hz = /bits/ 64 <1512000000>;
+ opp-peak-kBps = <1134000>;
+ opp-supported-hw = <0x4001>;
+ };
+
+ opp-1566000000 {
+ opp-hz = /bits/ 64 <1566000000>;
+ opp-peak-kBps = <1134000>;
+ opp-supported-hw = <0x06>;
+ };
+
+ opp-1674000000 {
+ opp-hz = /bits/ 64 <1674000000>;
+ opp-peak-kBps = <1134000>;
+ opp-supported-hw = <0x06>;
+ };
+
+ opp-1728000000 {
+ opp-hz = /bits/ 64 <1728000000>;
+ opp-peak-kBps = <1134000>;
+ opp-supported-hw = <0x02>;
+ };
+
+ opp-1782000000 {
+ opp-hz = /bits/ 64 <1782000000>;
+ opp-peak-kBps = <1134000>;
+ opp-supported-hw = <0x04>;
+ };
+
+ opp-1890000000 {
+ opp-hz = /bits/ 64 <1890000000>;
+ opp-peak-kBps = <1134000>;
+ opp-supported-hw = <0x04>;
+ };
+ };
+
memory@0 {
device_type = "memory";
reg = <0x0 0x0>;
@@ -213,6 +353,32 @@ sleep_clk: sleep_clk {
};
};
+ kraitcc: clock-controller {
+ compatible = "qcom,krait-cc-v1";
+ clocks = <&gcc PLL9>, /* hfpll0 */
+ <&gcc PLL10>, /* hfpll1 */
+ <&gcc PLL16>, /* hfpll2 */
+ <&gcc PLL17>, /* hfpll3 */
+ <&gcc PLL12>, /* hfpll_l2 */
+ <&acc0>,
+ <&acc1>,
+ <&acc2>,
+ <&acc3>,
+ <&l2cc>;
+ clock-names = "hfpll0",
+ "hfpll1",
+ "hfpll2",
+ "hfpll3",
+ "hfpll_l2",
+ "acpu0_aux",
+ "acpu1_aux",
+ "acpu2_aux",
+ "acpu3_aux",
+ "acpu_l2_aux";
+ #clock-cells = <1>;
+ #interconnect-cells = <1>;
+ };
+
sfpb_mutex: hwmutex {
compatible = "qcom,sfpb-mutex";
syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
@@ -834,6 +1000,9 @@ qfprom: qfprom@700000 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
+ speedbin_efuse: speedbin@c0 {
+ reg = <0x0c0 0x4>;
+ };
tsens_calib: calib@404 {
reg = <0x404 0x10>;
};
--
2.39.2
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 15/18] ARM: dts: qcom: apq8064: provide voltage scaling tables
2023-06-12 5:39 [PATCH 00/18] ARM: qcom: apq8064: support CPU frequency scaling Dmitry Baryshkov
` (14 preceding siblings ...)
2023-06-12 5:39 ` [PATCH 14/18] ARM: dts: qcom: apq8064: add simple CPUFreq support Dmitry Baryshkov
@ 2023-06-12 5:39 ` Dmitry Baryshkov
2023-06-12 9:01 ` Stephan Gerhold
2023-06-12 5:39 ` [PATCH 16/18] ARM: dts: qcom: apq8064: enable passive CPU cooling Dmitry Baryshkov
` (2 subsequent siblings)
18 siblings, 1 reply; 36+ messages in thread
From: Dmitry Baryshkov @ 2023-06-12 5:39 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Ilia Lin, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki
Cc: linux-arm-msm, devicetree, linux-pm, linux-clk, Christian Marangi
APQ8064 has 4 speed bins, each of them having from 4 to 6 categorization
kinds. Provide tables necessary to handle voltage scaling on this SoC.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 1017 +++++++++++++++++++++++++++
1 file changed, 1017 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 4ef13f3d702b..f35853b59544 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -49,6 +49,9 @@ CPU0: cpu@0 {
clocks = <&kraitcc KRAIT_CPU_0>;
clock-names = "cpu";
clock-latency = <100000>;
+ vdd-mem-supply = <&pm8921_l24>;
+ vdd-dig-supply = <&pm8921_s3>;
+ vdd-core-supply = <&saw0_vreg>;
interconnects = <&kraitcc MASTER_KRAIT_L2 &kraitcc SLAVE_KRAIT_L2>;
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>;
@@ -66,6 +69,9 @@ CPU1: cpu@1 {
clocks = <&kraitcc KRAIT_CPU_1>;
clock-names = "cpu";
clock-latency = <100000>;
+ vdd-mem-supply = <&pm8921_l24>;
+ vdd-dig-supply = <&pm8921_s3>;
+ vdd-core-supply = <&saw1_vreg>;
interconnects = <&kraitcc MASTER_KRAIT_L2 &kraitcc SLAVE_KRAIT_L2>;
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>;
@@ -83,6 +89,9 @@ CPU2: cpu@2 {
clocks = <&kraitcc KRAIT_CPU_2>;
clock-names = "cpu";
clock-latency = <100000>;
+ vdd-mem-supply = <&pm8921_l24>;
+ vdd-dig-supply = <&pm8921_s3>;
+ vdd-core-supply = <&saw2_vreg>;
interconnects = <&kraitcc MASTER_KRAIT_L2 &kraitcc SLAVE_KRAIT_L2>;
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>;
@@ -100,6 +109,9 @@ CPU3: cpu@3 {
clocks = <&kraitcc KRAIT_CPU_3>;
clock-names = "cpu";
clock-latency = <100000>;
+ vdd-mem-supply = <&pm8921_l24>;
+ vdd-dig-supply = <&pm8921_s3>;
+ vdd-core-supply = <&saw3_vreg>;
interconnects = <&kraitcc MASTER_KRAIT_L2 &kraitcc SLAVE_KRAIT_L2>;
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>;
@@ -132,6 +144,81 @@ cpu_opp_table: opp-table-cpu {
opp-384000000 {
opp-hz = /bits/ 64 <384000000>;
opp-peak-kBps = <384000>;
+ opp-microvolt-speed0-pvs0 = <1050000 1050000 1150000>,
+ <950000 950000 1150000>,
+ <950000 950000 975000>;
+ opp-microvolt-speed0-pvs1 = <1050000 1050000 1150000>,
+ <950000 950000 1150000>,
+ <925000 900000 950000>;
+ opp-microvolt-speed0-pvs3 = <1050000 1050000 1150000>,
+ <950000 950000 1150000>,
+ <875000 850000 900000>;
+ opp-microvolt-speed0-pvs4 = <1050000 1050000 1150000>,
+ <950000 950000 1150000>,
+ <875000 850000 900000>;
+ opp-microvolt-speed1-pvs0 = <1050000 1050000 1150000>,
+ <950000 950000 1150000>,
+ <950000 950000 975000>;
+ opp-microvolt-speed1-pvs1 = <1050000 1050000 1150000>,
+ <950000 950000 1150000>,
+ <975000 950000 1000000>;
+ opp-microvolt-speed1-pvs2 = <1050000 1050000 1150000>,
+ <950000 950000 1150000>,
+ <950000 925000 975000>;
+ opp-microvolt-speed1-pvs3 = <1050000 1050000 1150000>,
+ <950000 950000 1150000>,
+ <925000 900000 950000>;
+ opp-microvolt-speed1-pvs4 = <1050000 1050000 1150000>,
+ <950000 950000 1150000>,
+ <900000 875000 925000>;
+ opp-microvolt-speed1-pvs5 = <1050000 1050000 1150000>,
+ <950000 950000 1150000>,
+ <900000 875000 925000>;
+ opp-microvolt-speed1-pvs6 = <1050000 1050000 1150000>,
+ <950000 950000 1150000>,
+ <900000 875000 925000>;
+ opp-microvolt-speed2-pvs0 = <1050000 1050000 1150000>,
+ <950000 950000 1150000>,
+ <950000 950000 975000>;
+ opp-microvolt-speed2-pvs1 = <1050000 1050000 1150000>,
+ <950000 950000 1150000>,
+ <925000 925000 925000>;
+ opp-microvolt-speed2-pvs2 = <1050000 1050000 1150000>,
+ <950000 950000 1150000>,
+ <925000 900000 950000>;
+ opp-microvolt-speed2-pvs3 = <1050000 1050000 1150000>,
+ <950000 950000 1150000>,
+ <925000 900000 950000>;
+ opp-microvolt-speed2-pvs4 = <1050000 1050000 1150000>,
+ <950000 950000 1150000>,
+ <900000 875000 925000>;
+ opp-microvolt-speed2-pvs5 = <1050000 1050000 1150000>,
+ <950000 950000 1150000>,
+ <900000 875000 925000>;
+ opp-microvolt-speed2-pvs6 = <1050000 1050000 1150000>,
+ <950000 950000 1150000>,
+ <900000 875000 925000>;
+ opp-microvolt-speed14-pvs0 = <1050000 1050000 1150000>,
+ <950000 950000 1150000>,
+ <950000 950000 975000>;
+ opp-microvolt-speed14-pvs1 = <1050000 1050000 1150000>,
+ <950000 950000 1150000>,
+ <975000 950000 1000000>;
+ opp-microvolt-speed14-pvs2 = <1050000 1050000 1150000>,
+ <950000 950000 1150000>,
+ <950000 925000 975000>;
+ opp-microvolt-speed14-pvs3 = <1050000 1050000 1150000>,
+ <950000 950000 1150000>,
+ <925000 900000 950000>;
+ opp-microvolt-speed14-pvs4 = <1050000 1050000 1150000>,
+ <950000 950000 1150000>,
+ <900000 875000 925000>;
+ opp-microvolt-speed14-pvs5 = <1050000 1050000 1150000>,
+ <950000 950000 1150000>,
+ <875000 875000 875000>;
+ opp-microvolt-speed14-pvs6 = <1050000 1050000 1150000>,
+ <950000 950000 1150000>,
+ <900000 875000 925000>;
opp-supported-hw = <0x4007>;
/*
* higher latency as it requires switching between
@@ -143,96 +230,1026 @@ opp-384000000 {
opp-486000000 {
opp-hz = /bits/ 64 <486000000>;
opp-peak-kBps = <648000>;
+ opp-microvolt-speed0-pvs0 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <975000 975000 1000000>;
+ opp-microvolt-speed0-pvs1 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <950000 925000 975000>;
+ opp-microvolt-speed0-pvs3 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <900000 875000 925000>;
+ opp-microvolt-speed0-pvs4 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <900000 875000 925000>;
+ opp-microvolt-speed1-pvs0 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <950000 950000 975000>;
+ opp-microvolt-speed1-pvs1 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <975000 950000 1000000>;
+ opp-microvolt-speed1-pvs2 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <950000 925000 975000>;
+ opp-microvolt-speed1-pvs3 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <925000 900000 950000>;
+ opp-microvolt-speed1-pvs4 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <900000 875000 925000>;
+ opp-microvolt-speed1-pvs5 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <900000 875000 925000>;
+ opp-microvolt-speed1-pvs6 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <900000 875000 925000>;
+ opp-microvolt-speed2-pvs0 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <950000 950000 975000>;
+ opp-microvolt-speed2-pvs1 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <925000 925000 925000>;
+ opp-microvolt-speed2-pvs2 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <925000 900000 950000>;
+ opp-microvolt-speed2-pvs3 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <925000 900000 950000>;
+ opp-microvolt-speed2-pvs4 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <900000 875000 925000>;
+ opp-microvolt-speed2-pvs5 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <900000 875000 925000>;
+ opp-microvolt-speed2-pvs6 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <900000 875000 925000>;
+ opp-microvolt-speed14-pvs0 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <950000 950000 975000>;
+ opp-microvolt-speed14-pvs1 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <975000 950000 1000000>;
+ opp-microvolt-speed14-pvs2 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <950000 925000 975000>;
+ opp-microvolt-speed14-pvs3 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <925000 900000 950000>;
+ opp-microvolt-speed14-pvs4 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <900000 875000 925000>;
+ opp-microvolt-speed14-pvs5 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <875000 875000 875000>;
+ opp-microvolt-speed14-pvs6 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <875000 875000 875000>;
opp-supported-hw = <0x4007>;
};
opp-594000000 {
opp-hz = /bits/ 64 <594000000>;
opp-peak-kBps = <648000>;
+ opp-microvolt-speed0-pvs0 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <1000000 1000000 1025000>;
+ opp-microvolt-speed0-pvs1 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <975000 950000 1000000>;
+ opp-microvolt-speed0-pvs3 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <925000 900000 950000>;
+ opp-microvolt-speed0-pvs4 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <925000 900000 950000>;
+ opp-microvolt-speed1-pvs0 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <950000 950000 975000>;
+ opp-microvolt-speed1-pvs1 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <975000 950000 1000000>;
+ opp-microvolt-speed1-pvs2 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <950000 925000 975000>;
+ opp-microvolt-speed1-pvs3 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <925000 900000 950000>;
+ opp-microvolt-speed1-pvs4 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <900000 875000 925000>;
+ opp-microvolt-speed1-pvs5 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <900000 875000 925000>;
+ opp-microvolt-speed1-pvs6 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <900000 875000 925000>;
+ opp-microvolt-speed2-pvs0 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <950000 950000 975000>;
+ opp-microvolt-speed2-pvs1 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <925000 925000 925000>;
+ opp-microvolt-speed2-pvs2 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <925000 900000 950000>;
+ opp-microvolt-speed2-pvs3 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <925000 900000 950000>;
+ opp-microvolt-speed2-pvs4 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <900000 875000 925000>;
+ opp-microvolt-speed2-pvs5 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <900000 875000 925000>;
+ opp-microvolt-speed2-pvs6 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <900000 875000 925000>;
+ opp-microvolt-speed14-pvs0 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <950000 950000 975000>;
+ opp-microvolt-speed14-pvs1 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <975000 950000 1000000>;
+ opp-microvolt-speed14-pvs2 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <950000 925000 975000>;
+ opp-microvolt-speed14-pvs3 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <925000 900000 950000>;
+ opp-microvolt-speed14-pvs4 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <900000 875000 925000>;
+ opp-microvolt-speed14-pvs5 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <875000 875000 875000>;
+ opp-microvolt-speed14-pvs6 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <900000 875000 925000>;
opp-supported-hw = <0x4007>;
};
opp-702000000 {
opp-hz = /bits/ 64 <702000000>;
opp-peak-kBps = <648000>;
+ opp-microvolt-speed0-pvs0 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <1025000 1025000 1050000>;
+ opp-microvolt-speed0-pvs1 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <1000000 975000 1025000>;
+ opp-microvolt-speed0-pvs3 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <950000 925000 975000>;
+ opp-microvolt-speed0-pvs4 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <950000 925000 975000>;
+ opp-microvolt-speed1-pvs0 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <962500 962500 987500>;
+ opp-microvolt-speed1-pvs1 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <987500 962500 1012500>;
+ opp-microvolt-speed1-pvs2 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <950000 925000 975000>;
+ opp-microvolt-speed1-pvs3 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <925000 900000 950000>;
+ opp-microvolt-speed1-pvs4 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <900000 875000 925000>;
+ opp-microvolt-speed1-pvs5 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <900000 875000 925000>;
+ opp-microvolt-speed1-pvs6 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <900000 875000 925000>;
+ opp-microvolt-speed2-pvs0 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <950000 950000 975000>;
+ opp-microvolt-speed2-pvs1 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <925000 925000 925000>;
+ opp-microvolt-speed2-pvs2 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <925000 900000 950000>;
+ opp-microvolt-speed2-pvs3 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <925000 900000 950000>;
+ opp-microvolt-speed2-pvs4 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <900000 875000 925000>;
+ opp-microvolt-speed2-pvs5 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <900000 875000 925000>;
+ opp-microvolt-speed2-pvs6 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <900000 875000 925000>;
+ opp-microvolt-speed14-pvs0 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <962500 962500 987500>;
+ opp-microvolt-speed14-pvs1 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <987500 962500 1012500>;
+ opp-microvolt-speed14-pvs2 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <950000 925000 975000>;
+ opp-microvolt-speed14-pvs3 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <925000 900000 950000>;
+ opp-microvolt-speed14-pvs4 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <900000 875000 925000>;
+ opp-microvolt-speed14-pvs5 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <875000 875000 875000>;
+ opp-microvolt-speed14-pvs6 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <900000 875000 925000>;
opp-supported-hw = <0x4007>;
};
opp-810000000 {
opp-hz = /bits/ 64 <810000000>;
opp-peak-kBps = <648000>;
+ opp-microvolt-speed0-pvs0 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <1075000 1075000 1100000>;
+ opp-microvolt-speed0-pvs1 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <1050000 1025000 1075000>;
+ opp-microvolt-speed0-pvs3 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <1000000 975000 1025000>;
+ opp-microvolt-speed0-pvs4 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <987500 962500 1012500>;
+ opp-microvolt-speed1-pvs0 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <1000000 1000000 1025000>;
+ opp-microvolt-speed1-pvs1 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <1000000 975000 1025000>;
+ opp-microvolt-speed1-pvs2 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <962500 937500 987500>;
+ opp-microvolt-speed1-pvs3 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <925000 900000 950000>;
+ opp-microvolt-speed1-pvs4 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <912500 887500 937500>;
+ opp-microvolt-speed1-pvs5 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <912500 887500 937500>;
+ opp-microvolt-speed1-pvs6 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <912500 887500 937500>;
+ opp-microvolt-speed2-pvs0 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <962500 962500 987500>;
+ opp-microvolt-speed2-pvs1 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <937500 937500 937500>;
+ opp-microvolt-speed2-pvs2 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <937500 912500 962500>;
+ opp-microvolt-speed2-pvs3 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <925000 900000 950000>;
+ opp-microvolt-speed2-pvs4 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <912500 887500 937500>;
+ opp-microvolt-speed2-pvs5 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <912500 887500 937500>;
+ opp-microvolt-speed2-pvs6 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <912500 887500 937500>;
+ opp-microvolt-speed14-pvs0 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <1000000 1000000 1025000>;
+ opp-microvolt-speed14-pvs1 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <1000000 975000 1025000>;
+ opp-microvolt-speed14-pvs2 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <962500 937500 987500>;
+ opp-microvolt-speed14-pvs3 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <925000 900000 950000>;
+ opp-microvolt-speed14-pvs4 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <912500 887500 937500>;
+ opp-microvolt-speed14-pvs5 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <887500 887500 887500>;
+ opp-microvolt-speed14-pvs6 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <912500 887500 937500>;
opp-supported-hw = <0x4007>;
};
opp-918000000 {
opp-hz = /bits/ 64 <918000000>;
opp-peak-kBps = <648000>;
+ opp-microvolt-speed0-pvs0 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <1100000 1100000 1125000>;
+ opp-microvolt-speed0-pvs1 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <1075000 1050000 1100000>;
+ opp-microvolt-speed0-pvs3 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <1025000 1000000 1050000>;
+ opp-microvolt-speed0-pvs4 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <1000000 975000 1025000>;
+ opp-microvolt-speed1-pvs0 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <1025000 1025000 1050000>;
+ opp-microvolt-speed1-pvs1 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <1025000 1000000 1050000>;
+ opp-microvolt-speed1-pvs2 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <975000 950000 1000000>;
+ opp-microvolt-speed1-pvs3 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <950000 925000 975000>;
+ opp-microvolt-speed1-pvs4 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <925000 900000 950000>;
+ opp-microvolt-speed1-pvs5 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <925000 900000 950000>;
+ opp-microvolt-speed1-pvs6 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <925000 900000 950000>;
+ opp-microvolt-speed2-pvs0 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <975000 975000 1000000>;
+ opp-microvolt-speed2-pvs1 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <950000 950000 950000>;
+ opp-microvolt-speed2-pvs2 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <950000 925000 975000>;
+ opp-microvolt-speed2-pvs3 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <937500 912500 962500>;
+ opp-microvolt-speed2-pvs4 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <925000 900000 950000>;
+ opp-microvolt-speed2-pvs5 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <925000 900000 950000>;
+ opp-microvolt-speed2-pvs6 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <925000 900000 950000>;
+ opp-microvolt-speed14-pvs0 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <1025000 1025000 1050000>;
+ opp-microvolt-speed14-pvs1 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <1025000 1000000 1050000>;
+ opp-microvolt-speed14-pvs2 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <975000 950000 1000000>;
+ opp-microvolt-speed14-pvs3 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <950000 925000 975000>;
+ opp-microvolt-speed14-pvs4 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <925000 900000 950000>;
+ opp-microvolt-speed14-pvs5 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <900000 900000 900000>;
+ opp-microvolt-speed14-pvs6 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <925000 900000 950000>;
opp-supported-hw = <0x4007>;
};
opp-1026000000 {
opp-hz = /bits/ 64 <1026000000>;
opp-peak-kBps = <648000>;
+ opp-microvolt-speed0-pvs0 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <1125000 1125000 1150000>;
+ opp-microvolt-speed0-pvs1 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <1100000 1075000 1125000>;
+ opp-microvolt-speed0-pvs3 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <1050000 1025000 1075000>;
+ opp-microvolt-speed0-pvs4 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <1025000 1000000 1050000>;
+ opp-microvolt-speed1-pvs0 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <1037500 1037500 1062500>;
+ opp-microvolt-speed1-pvs1 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <1037500 1012500 1062500>;
+ opp-microvolt-speed1-pvs2 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <1000000 975000 1025000>;
+ opp-microvolt-speed1-pvs3 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <975000 950000 1000000>;
+ opp-microvolt-speed1-pvs4 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <950000 925000 975000>;
+ opp-microvolt-speed1-pvs5 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <950000 925000 975000>;
+ opp-microvolt-speed1-pvs6 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <950000 925000 975000>;
+ opp-microvolt-speed2-pvs0 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <1000000 1000000 1025000>;
+ opp-microvolt-speed2-pvs1 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <975000 975000 975000>;
+ opp-microvolt-speed2-pvs2 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <975000 950000 1000000>;
+ opp-microvolt-speed2-pvs3 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <962500 937500 987500>;
+ opp-microvolt-speed2-pvs4 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <950000 925000 975000>;
+ opp-microvolt-speed2-pvs5 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <950000 925000 975000>;
+ opp-microvolt-speed2-pvs6 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <950000 925000 975000>;
+ opp-microvolt-speed14-pvs0 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <1037500 1037500 1062500>;
+ opp-microvolt-speed14-pvs1 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <1037500 1012500 1062500>;
+ opp-microvolt-speed14-pvs2 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <1000000 975000 1025000>;
+ opp-microvolt-speed14-pvs3 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <975000 950000 1000000>;
+ opp-microvolt-speed14-pvs4 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <950000 925000 975000>;
+ opp-microvolt-speed14-pvs5 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <925000 925000 925000>;
+ opp-microvolt-speed14-pvs6 = <1050000 1050000 1150000>,
+ <1050000 1050000 1150000>,
+ <950000 925000 975000>;
opp-supported-hw = <0x4007>;
};
opp-1134000000 {
opp-hz = /bits/ 64 <1134000000>;
opp-peak-kBps = <1134000>;
+ opp-microvolt-speed0-pvs0 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1175000 1175000 1200000>;
+ opp-microvolt-speed0-pvs1 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1150000 1125000 1175000>;
+ opp-microvolt-speed0-pvs3 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1100000 1075000 1125000>;
+ opp-microvolt-speed0-pvs4 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1075000 1050000 1100000>;
+ opp-microvolt-speed1-pvs0 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1075000 1075000 1100000>;
+ opp-microvolt-speed1-pvs1 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1062500 1037500 1087500>;
+ opp-microvolt-speed1-pvs2 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1025000 1000000 1050000>;
+ opp-microvolt-speed1-pvs3 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1000000 975000 1025000>;
+ opp-microvolt-speed1-pvs4 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <975000 950000 1000000>;
+ opp-microvolt-speed1-pvs5 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <962500 937500 987500>;
+ opp-microvolt-speed1-pvs6 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <962500 937500 987500>;
+ opp-microvolt-speed2-pvs0 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1025000 1025000 1050000>;
+ opp-microvolt-speed2-pvs1 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1000000 1000000 1000000>;
+ opp-microvolt-speed2-pvs2 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1000000 975000 1025000>;
+ opp-microvolt-speed2-pvs3 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <987500 962500 1012500>;
+ opp-microvolt-speed2-pvs4 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <975000 950000 1000000>;
+ opp-microvolt-speed2-pvs5 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <962500 937500 987500>;
+ opp-microvolt-speed2-pvs6 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <962500 937500 987500>;
+ opp-microvolt-speed14-pvs0 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1075000 1075000 1100000>;
+ opp-microvolt-speed14-pvs1 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1062500 1037500 1087500>;
+ opp-microvolt-speed14-pvs2 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1025000 1000000 1050000>;
+ opp-microvolt-speed14-pvs3 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1000000 975000 1025000>;
+ opp-microvolt-speed14-pvs4 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <975000 950000 1000000>;
+ opp-microvolt-speed14-pvs5 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <937500 937500 937500>;
+ opp-microvolt-speed14-pvs6 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <962500 937500 987500>;
opp-supported-hw = <0x4007>;
};
opp-1242000000 {
opp-hz = /bits/ 64 <1242000000>;
opp-peak-kBps = <1134000>;
+ opp-microvolt-speed0-pvs0 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1200000 1200000 1225000>;
+ opp-microvolt-speed0-pvs1 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1175000 1150000 1200000>;
+ opp-microvolt-speed0-pvs3 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1125000 1100000 1150000>;
+ opp-microvolt-speed0-pvs4 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1100000 1075000 1125000>;
+ opp-microvolt-speed1-pvs0 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1087500 1087500 1112500>;
+ opp-microvolt-speed1-pvs1 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1075000 1050000 1100000>;
+ opp-microvolt-speed1-pvs2 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1037500 1012500 1062500>;
+ opp-microvolt-speed1-pvs3 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1012500 987500 1037500>;
+ opp-microvolt-speed1-pvs4 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <987500 962500 1012500>;
+ opp-microvolt-speed1-pvs5 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <975000 950000 1000000>;
+ opp-microvolt-speed1-pvs6 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <975000 950000 1000000>;
+ opp-microvolt-speed2-pvs0 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1037500 1037500 1062500>;
+ opp-microvolt-speed2-pvs1 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1012500 1012500 1012500>;
+ opp-microvolt-speed2-pvs2 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1012500 987500 1037500>;
+ opp-microvolt-speed2-pvs3 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1000000 975000 1025000>;
+ opp-microvolt-speed2-pvs4 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <987500 962500 1012500>;
+ opp-microvolt-speed2-pvs5 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <975000 950000 1000000>;
+ opp-microvolt-speed2-pvs6 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <975000 950000 1000000>;
+ opp-microvolt-speed14-pvs0 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1087500 1087500 1112500>;
+ opp-microvolt-speed14-pvs1 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1075000 1050000 1100000>;
+ opp-microvolt-speed14-pvs2 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1037500 1012500 1062500>;
+ opp-microvolt-speed14-pvs3 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1012500 987500 1037500>;
+ opp-microvolt-speed14-pvs4 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <987500 962500 1012500>;
+ opp-microvolt-speed14-pvs5 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <950000 950000 950000>;
+ opp-microvolt-speed14-pvs6 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <975000 950000 1000000>;
opp-supported-hw = <0x4007>;
};
opp-1350000000 {
opp-hz = /bits/ 64 <1350000000>;
opp-peak-kBps = <1134000>;
+ opp-microvolt-speed0-pvs0 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1225000 1225000 1250000>;
+ opp-microvolt-speed0-pvs1 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1200000 1175000 1225000>;
+ opp-microvolt-speed0-pvs3 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1150000 1125000 1175000>;
+ opp-microvolt-speed0-pvs4 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1125000 1100000 1150000>;
+ opp-microvolt-speed1-pvs0 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1125000 1125000 1150000>;
+ opp-microvolt-speed1-pvs1 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1112500 1087500 1137500>;
+ opp-microvolt-speed1-pvs2 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1062500 1037500 1087500>;
+ opp-microvolt-speed1-pvs3 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1025000 1000000 1050000>;
+ opp-microvolt-speed1-pvs4 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1000000 975000 1025000>;
+ opp-microvolt-speed1-pvs5 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <987500 962500 1012500>;
+ opp-microvolt-speed1-pvs6 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <987500 962500 1012500>;
+ opp-microvolt-speed2-pvs0 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1062500 1062500 1087500>;
+ opp-microvolt-speed2-pvs1 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1037500 1037500 1037500>;
+ opp-microvolt-speed2-pvs2 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1037500 1012500 1062500>;
+ opp-microvolt-speed2-pvs3 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1025000 1000000 1050000>;
+ opp-microvolt-speed2-pvs4 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1000000 975000 1025000>;
+ opp-microvolt-speed2-pvs5 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <987500 962500 1012500>;
+ opp-microvolt-speed2-pvs6 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <987500 962500 1012500>;
+ opp-microvolt-speed14-pvs0 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1125000 1125000 1150000>;
+ opp-microvolt-speed14-pvs1 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1112500 1087500 1137500>;
+ opp-microvolt-speed14-pvs2 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1062500 1037500 1087500>;
+ opp-microvolt-speed14-pvs3 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1025000 1000000 1050000>;
+ opp-microvolt-speed14-pvs4 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1000000 975000 1025000>;
+ opp-microvolt-speed14-pvs5 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <962500 962500 962500>;
+ opp-microvolt-speed14-pvs6 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <987500 962500 1012500>;
opp-supported-hw = <0x4007>;
};
opp-1458000000 {
opp-hz = /bits/ 64 <1458000000>;
opp-peak-kBps = <1134000>;
+ opp-microvolt-speed0-pvs0 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1237500 1237500 1262500>;
+ opp-microvolt-speed0-pvs1 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1212500 1187500 1237500>;
+ opp-microvolt-speed0-pvs3 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1162500 1137500 1187500>;
+ opp-microvolt-speed0-pvs4 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1137500 1112500 1162500>;
+ opp-microvolt-speed1-pvs0 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1150000 1150000 1175000>;
+ opp-microvolt-speed1-pvs1 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1137500 1112500 1162500>;
+ opp-microvolt-speed1-pvs2 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1100000 1075000 1125000>;
+ opp-microvolt-speed1-pvs3 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1062500 1037500 1087500>;
+ opp-microvolt-speed1-pvs4 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1025000 1000000 1050000>;
+ opp-microvolt-speed1-pvs5 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1012500 987500 1037500>;
+ opp-microvolt-speed1-pvs6 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1000000 975000 1025000>;
+ opp-microvolt-speed2-pvs0 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1100000 1100000 1125000>;
+ opp-microvolt-speed2-pvs1 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1075000 1075000 1075000>;
+ opp-microvolt-speed2-pvs2 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1075000 1050000 1100000>;
+ opp-microvolt-speed2-pvs3 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1050000 1025000 1075000>;
+ opp-microvolt-speed2-pvs4 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1025000 1000000 1050000>;
+ opp-microvolt-speed2-pvs5 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1012500 987500 1037500>;
+ opp-microvolt-speed2-pvs6 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1000000 975000 1025000>;
+ opp-microvolt-speed14-pvs0 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1150000 1150000 1175000>;
+ opp-microvolt-speed14-pvs1 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1137500 1112500 1162500>;
+ opp-microvolt-speed14-pvs2 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1100000 1075000 1125000>;
+ opp-microvolt-speed14-pvs3 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1062500 1037500 1087500>;
+ opp-microvolt-speed14-pvs4 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1025000 1000000 1050000>;
+ opp-microvolt-speed14-pvs5 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <987500 987500 987500>;
+ opp-microvolt-speed14-pvs6 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1000000 975000 1025000>;
opp-supported-hw = <0x4007>;
};
opp-1512000000 {
opp-hz = /bits/ 64 <1512000000>;
opp-peak-kBps = <1134000>;
+ opp-microvolt-speed0-pvs0 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1250000 1250000 1275000>;
+ opp-microvolt-speed0-pvs1 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1225000 1200000 1250000>;
+ opp-microvolt-speed0-pvs3 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1175000 1150000 1200000>;
+ opp-microvolt-speed0-pvs4 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1150000 1125000 1175000>;
+ opp-microvolt-speed14-pvs0 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1162500 1162500 1187500>;
+ opp-microvolt-speed14-pvs1 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1150000 1125000 1175000>;
+ opp-microvolt-speed14-pvs2 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1112500 1087500 1137500>;
+ opp-microvolt-speed14-pvs3 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1075000 1050000 1100000>;
+ opp-microvolt-speed14-pvs4 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1037500 1012500 1062500>;
+ opp-microvolt-speed14-pvs5 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1000000 1000000 1000000>;
+ opp-microvolt-speed14-pvs6 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1012500 987500 1037500>;
opp-supported-hw = <0x4001>;
};
opp-1566000000 {
opp-hz = /bits/ 64 <1566000000>;
opp-peak-kBps = <1134000>;
+ opp-microvolt-speed1-pvs0 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1175000 1175000 1200000>;
+ opp-microvolt-speed1-pvs1 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1175000 1150000 1200000>;
+ opp-microvolt-speed1-pvs2 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1125000 1100000 1150000>;
+ opp-microvolt-speed1-pvs3 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1087500 1062500 1112500>;
+ opp-microvolt-speed1-pvs4 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1062500 1037500 1087500>;
+ opp-microvolt-speed1-pvs5 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1037500 1012500 1062500>;
+ opp-microvolt-speed1-pvs6 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1025000 1000000 1050000>;
+ opp-microvolt-speed2-pvs0 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1125000 1125000 1150000>;
+ opp-microvolt-speed2-pvs1 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1100000 1100000 1100000>;
+ opp-microvolt-speed2-pvs2 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1100000 1075000 1125000>;
+ opp-microvolt-speed2-pvs3 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1075000 1050000 1100000>;
+ opp-microvolt-speed2-pvs4 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1062500 1037500 1087500>;
+ opp-microvolt-speed2-pvs5 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1037500 1012500 1062500>;
+ opp-microvolt-speed2-pvs6 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1025000 1000000 1050000>;
opp-supported-hw = <0x06>;
};
opp-1674000000 {
opp-hz = /bits/ 64 <1674000000>;
opp-peak-kBps = <1134000>;
+ opp-microvolt-speed1-pvs0 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1225000 1225000 1250000>;
+ opp-microvolt-speed1-pvs1 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1212500 1187500 1237500>;
+ opp-microvolt-speed1-pvs2 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1162500 1137500 1187500>;
+ opp-microvolt-speed1-pvs3 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1125000 1100000 1150000>;
+ opp-microvolt-speed1-pvs4 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1100000 1075000 1125000>;
+ opp-microvolt-speed1-pvs5 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1075000 1050000 1100000>;
+ opp-microvolt-speed1-pvs6 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1050000 1025000 1075000>;
+ opp-microvolt-speed2-pvs0 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1175000 1175000 1200000>;
+ opp-microvolt-speed2-pvs1 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1137500 1137500 1137500>;
+ opp-microvolt-speed2-pvs2 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1137500 1112500 1162500>;
+ opp-microvolt-speed2-pvs3 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1112500 1087500 1137500>;
+ opp-microvolt-speed2-pvs4 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1100000 1075000 1125000>;
+ opp-microvolt-speed2-pvs5 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1075000 1050000 1100000>;
+ opp-microvolt-speed2-pvs6 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1050000 1025000 1075000>;
opp-supported-hw = <0x06>;
};
opp-1728000000 {
opp-hz = /bits/ 64 <1728000000>;
opp-peak-kBps = <1134000>;
+ opp-microvolt-speed1-pvs0 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1250000 1250000 1275000>;
+ opp-microvolt-speed1-pvs1 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1225000 1200000 1250000>;
+ opp-microvolt-speed1-pvs2 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1187500 1162500 1212500>;
+ opp-microvolt-speed1-pvs3 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1150000 1125000 1175000>;
+ opp-microvolt-speed1-pvs4 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1125000 1100000 1150000>;
+ opp-microvolt-speed1-pvs5 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1100000 1075000 1125000>;
+ opp-microvolt-speed1-pvs6 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1075000 1050000 1100000>;
opp-supported-hw = <0x02>;
};
opp-1782000000 {
opp-hz = /bits/ 64 <1782000000>;
opp-peak-kBps = <1134000>;
+ opp-microvolt-speed2-pvs0 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1225000 1225000 1250000>;
+ opp-microvolt-speed2-pvs1 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1187500 1187500 1187500>;
+ opp-microvolt-speed2-pvs2 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1187500 1162500 1212500>;
+ opp-microvolt-speed2-pvs3 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1162500 1137500 1187500>;
+ opp-microvolt-speed2-pvs4 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1137500 1112500 1162500>;
+ opp-microvolt-speed2-pvs5 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1112500 1087500 1137500>;
+ opp-microvolt-speed2-pvs6 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1087500 1062500 1112500>;
opp-supported-hw = <0x04>;
};
opp-1890000000 {
opp-hz = /bits/ 64 <1890000000>;
opp-peak-kBps = <1134000>;
+ opp-microvolt-speed2-pvs0 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1287500 1287500 1312500>;
+ opp-microvolt-speed2-pvs1 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1250000 1250000 1250000>;
+ opp-microvolt-speed2-pvs2 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1237500 1212500 1262500>;
+ opp-microvolt-speed2-pvs3 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1200000 1175000 1225000>;
+ opp-microvolt-speed2-pvs4 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1175000 1150000 1200000>;
+ opp-microvolt-speed2-pvs5 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1150000 1125000 1175000>;
+ opp-microvolt-speed2-pvs6 = <1150000 1150000 1150000>,
+ <1150000 1150000 1150000>,
+ <1125000 1100000 1150000>;
opp-supported-hw = <0x04>;
};
};
--
2.39.2
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 16/18] ARM: dts: qcom: apq8064: enable passive CPU cooling
2023-06-12 5:39 [PATCH 00/18] ARM: qcom: apq8064: support CPU frequency scaling Dmitry Baryshkov
` (15 preceding siblings ...)
2023-06-12 5:39 ` [PATCH 15/18] ARM: dts: qcom: apq8064: provide voltage scaling tables Dmitry Baryshkov
@ 2023-06-12 5:39 ` Dmitry Baryshkov
2023-06-12 5:39 ` [PATCH 17/18] ARM: dts: qcom: apq8064-asus-nexus7-flo: constraint cpufreq regulators Dmitry Baryshkov
2023-06-12 5:39 ` [PATCH 18/18] ARM: dts: qcom: apq8064-ifc6410: " Dmitry Baryshkov
18 siblings, 0 replies; 36+ messages in thread
From: Dmitry Baryshkov @ 2023-06-12 5:39 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Ilia Lin, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki
Cc: linux-arm-msm, devicetree, linux-pm, linux-clk, Christian Marangi
Wire up CPUs and thermal trip points to save the SoC from overheating by
lowering the CPU frequency.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index f35853b59544..82b381b66cfb 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/soc/qcom,gsbi.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
@@ -1279,6 +1280,13 @@ cpu_crit0: trip1 {
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert0>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
cpu1-thermal {
@@ -1300,6 +1308,13 @@ cpu_crit1: trip1 {
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert1>;
+ cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
cpu2-thermal {
@@ -1321,6 +1336,13 @@ cpu_crit2: trip1 {
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert2>;
+ cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
cpu3-thermal {
@@ -1342,6 +1364,13 @@ cpu_crit3: trip1 {
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert3>;
+ cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
};
--
2.39.2
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 17/18] ARM: dts: qcom: apq8064-asus-nexus7-flo: constraint cpufreq regulators
2023-06-12 5:39 [PATCH 00/18] ARM: qcom: apq8064: support CPU frequency scaling Dmitry Baryshkov
` (16 preceding siblings ...)
2023-06-12 5:39 ` [PATCH 16/18] ARM: dts: qcom: apq8064: enable passive CPU cooling Dmitry Baryshkov
@ 2023-06-12 5:39 ` Dmitry Baryshkov
2023-06-12 5:39 ` [PATCH 18/18] ARM: dts: qcom: apq8064-ifc6410: " Dmitry Baryshkov
18 siblings, 0 replies; 36+ messages in thread
From: Dmitry Baryshkov @ 2023-06-12 5:39 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Ilia Lin, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki
Cc: linux-arm-msm, devicetree, linux-pm, linux-clk, Christian Marangi
Add additional constraints to the CPUfreq-related regulators, it is
better be safe than sorry there.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts
index c57c27cd8a20..9f5d72727356 100644
--- a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts
@@ -218,9 +218,9 @@ s1 {
bias-pull-down;
};
- /* msm otg HSUSB_VDDCX */
+ /* msm otg HSUSB_VDDCX and VDD_DIG */
s3 {
- regulator-min-microvolt = <500000>;
+ regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1150000>;
qcom,switch-mode-frequency = <4800000>;
};
@@ -301,6 +301,12 @@ l23 {
bias-pull-down;
};
+ /* VDD_MEM */
+ l24 {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1150000>;
+ };
+
/*
* tabla2x-slim-CDC_VDDA_A_1P2V
* tabla2x-slim-VDDD_CDC_D
@@ -329,8 +335,12 @@ lvs6 {
/*
* mipi_dsi.1-dsi1_vddio
* pil_riva-pll_vdd
+ * HFPLL regulator
*/
lvs7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
bias-pull-down;
};
};
--
2.39.2
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 18/18] ARM: dts: qcom: apq8064-ifc6410: constraint cpufreq regulators
2023-06-12 5:39 [PATCH 00/18] ARM: qcom: apq8064: support CPU frequency scaling Dmitry Baryshkov
` (17 preceding siblings ...)
2023-06-12 5:39 ` [PATCH 17/18] ARM: dts: qcom: apq8064-asus-nexus7-flo: constraint cpufreq regulators Dmitry Baryshkov
@ 2023-06-12 5:39 ` Dmitry Baryshkov
18 siblings, 0 replies; 36+ messages in thread
From: Dmitry Baryshkov @ 2023-06-12 5:39 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Ilia Lin, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki
Cc: linux-arm-msm, devicetree, linux-pm, linux-clk, Christian Marangi
Add additional constraints to the CPUfreq-related regulators, it is
better be safe than sorry there.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
index 96307550523a..ad3cd45362df 100644
--- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
@@ -215,8 +215,8 @@ s1 {
};
s3 {
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1400000>;
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1150000>;
qcom,switch-mode-frequency = <4800000>;
};
@@ -262,6 +262,12 @@ l23 {
bias-pull-down;
};
+ l24 {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1150000>;
+ bias-pull-down;
+ };
+
lvs1 {
bias-pull-down;
};
@@ -269,6 +275,14 @@ lvs1 {
lvs6 {
bias-pull-down;
};
+
+ /* HFPLL regulator */
+ lvs7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
};
};
--
2.39.2
^ permalink raw reply related [flat|nested] 36+ messages in thread
* Re: [PATCH 15/18] ARM: dts: qcom: apq8064: provide voltage scaling tables
2023-06-12 5:39 ` [PATCH 15/18] ARM: dts: qcom: apq8064: provide voltage scaling tables Dmitry Baryshkov
@ 2023-06-12 9:01 ` Stephan Gerhold
2023-06-12 13:33 ` Dmitry Baryshkov
0 siblings, 1 reply; 36+ messages in thread
From: Stephan Gerhold @ 2023-06-12 9:01 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Ilia Lin, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki, linux-arm-msm, devicetree, linux-pm,
linux-clk, Christian Marangi
On Mon, Jun 12, 2023 at 08:39:19AM +0300, Dmitry Baryshkov wrote:
> APQ8064 has 4 speed bins, each of them having from 4 to 6 categorization
> kinds. Provide tables necessary to handle voltage scaling on this SoC.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> arch/arm/boot/dts/qcom-apq8064.dtsi | 1017 +++++++++++++++++++++++++++
> 1 file changed, 1017 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
> index 4ef13f3d702b..f35853b59544 100644
> --- a/arch/arm/boot/dts/qcom-apq8064.dtsi
> +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
> @@ -49,6 +49,9 @@ CPU0: cpu@0 {
> clocks = <&kraitcc KRAIT_CPU_0>;
> clock-names = "cpu";
> clock-latency = <100000>;
> + vdd-mem-supply = <&pm8921_l24>;
> + vdd-dig-supply = <&pm8921_s3>;
> + vdd-core-supply = <&saw0_vreg>;
> interconnects = <&kraitcc MASTER_KRAIT_L2 &kraitcc SLAVE_KRAIT_L2>;
> operating-points-v2 = <&cpu_opp_table>;
> #cooling-cells = <2>;
> @@ -66,6 +69,9 @@ CPU1: cpu@1 {
> clocks = <&kraitcc KRAIT_CPU_1>;
> clock-names = "cpu";
> clock-latency = <100000>;
> + vdd-mem-supply = <&pm8921_l24>;
> + vdd-dig-supply = <&pm8921_s3>;
> + vdd-core-supply = <&saw1_vreg>;
> interconnects = <&kraitcc MASTER_KRAIT_L2 &kraitcc SLAVE_KRAIT_L2>;
> operating-points-v2 = <&cpu_opp_table>;
> #cooling-cells = <2>;
> @@ -83,6 +89,9 @@ CPU2: cpu@2 {
> clocks = <&kraitcc KRAIT_CPU_2>;
> clock-names = "cpu";
> clock-latency = <100000>;
> + vdd-mem-supply = <&pm8921_l24>;
> + vdd-dig-supply = <&pm8921_s3>;
> + vdd-core-supply = <&saw2_vreg>;
> interconnects = <&kraitcc MASTER_KRAIT_L2 &kraitcc SLAVE_KRAIT_L2>;
> operating-points-v2 = <&cpu_opp_table>;
> #cooling-cells = <2>;
> @@ -100,6 +109,9 @@ CPU3: cpu@3 {
> clocks = <&kraitcc KRAIT_CPU_3>;
> clock-names = "cpu";
> clock-latency = <100000>;
> + vdd-mem-supply = <&pm8921_l24>;
> + vdd-dig-supply = <&pm8921_s3>;
> + vdd-core-supply = <&saw3_vreg>;
> interconnects = <&kraitcc MASTER_KRAIT_L2 &kraitcc SLAVE_KRAIT_L2>;
> operating-points-v2 = <&cpu_opp_table>;
> #cooling-cells = <2>;
> @@ -132,6 +144,81 @@ cpu_opp_table: opp-table-cpu {
> opp-384000000 {
> opp-hz = /bits/ 64 <384000000>;
> opp-peak-kBps = <384000>;
> + opp-microvolt-speed0-pvs0 = <1050000 1050000 1150000>,
> + <950000 950000 1150000>,
> + <950000 950000 975000>;
I think this won't result in the correct switch order without making
some changes to the OPP core. In _set_opp() the OPP core does
/* Scaling up? Configure required OPPs before frequency */
if (!scaling_down) {
_set_required_opps();
_set_opp_bw();
opp_table->config_regulators();
}
opp_table->config_clks();
/* Scaling down? Configure required OPPs after frequency */
if (scaling_down) {
opp_table->config_regulators();
_set_opp_bw();
_set_required_opps();
}
Since the "bandwidth" for the L2 cache is set before the regulators
there is a short window where the L2 clock is running at a high
frequency with too low voltage, which could potentially cause
instability. On downstream this seems to be done in the proper order [1].
I'm not sure if the order in the OPP core is on purpose. If not, you
could propose moving the config_regulators() first (for scaling up)
and last (for scaling down). This would resolve the problem.
The alternative that I've already argued for on IRC in #linux-msm a
couple of days ago would be to give the L2 cache (here: "interconnect")
an own OPP table where it can describe its voltage requirements,
independent from the CPU. That way the icc_set_bw() would be guaranteed
to apply the correct voltage before adjusting the L2 cache clock. It
looks like the "l2_level" voltages for vdd_dig and vdd_mem are not
speedbin/PVS-specific [2] so this would also significantly reduce the DT
size, since you wouldn't need to repeat the same vdd_dig/vdd_mem
voltages for all of them.
Thanks,
Stephan
[1]: https://git.codelinaro.org/clo/la/kernel/msm/-/blob/LA.AF.1.2.1-08410-8064.0/arch/arm/mach-msm/acpuclock-krait.c#L529-588
[2]: https://git.codelinaro.org/clo/la/kernel/msm/-/blob/LA.AF.1.2.1-08410-8064.0/arch/arm/mach-msm/acpuclock-8064.c#L118-135
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 15/18] ARM: dts: qcom: apq8064: provide voltage scaling tables
2023-06-12 9:01 ` Stephan Gerhold
@ 2023-06-12 13:33 ` Dmitry Baryshkov
2023-06-11 22:16 ` Christian Marangi
2023-06-12 13:59 ` Stephan Gerhold
0 siblings, 2 replies; 36+ messages in thread
From: Dmitry Baryshkov @ 2023-06-12 13:33 UTC (permalink / raw)
To: Stephan Gerhold
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Ilia Lin, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki, linux-arm-msm, devicetree, linux-pm,
linux-clk, Christian Marangi
On 12/06/2023 12:01, Stephan Gerhold wrote:
> On Mon, Jun 12, 2023 at 08:39:19AM +0300, Dmitry Baryshkov wrote:
>> APQ8064 has 4 speed bins, each of them having from 4 to 6 categorization
>> kinds. Provide tables necessary to handle voltage scaling on this SoC.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
>> arch/arm/boot/dts/qcom-apq8064.dtsi | 1017 +++++++++++++++++++++++++++
>> 1 file changed, 1017 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
>> index 4ef13f3d702b..f35853b59544 100644
>> --- a/arch/arm/boot/dts/qcom-apq8064.dtsi
>> +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
>> @@ -49,6 +49,9 @@ CPU0: cpu@0 {
>> clocks = <&kraitcc KRAIT_CPU_0>;
>> clock-names = "cpu";
>> clock-latency = <100000>;
>> + vdd-mem-supply = <&pm8921_l24>;
>> + vdd-dig-supply = <&pm8921_s3>;
>> + vdd-core-supply = <&saw0_vreg>;
>> interconnects = <&kraitcc MASTER_KRAIT_L2 &kraitcc SLAVE_KRAIT_L2>;
>> operating-points-v2 = <&cpu_opp_table>;
>> #cooling-cells = <2>;
>> @@ -66,6 +69,9 @@ CPU1: cpu@1 {
>> clocks = <&kraitcc KRAIT_CPU_1>;
>> clock-names = "cpu";
>> clock-latency = <100000>;
>> + vdd-mem-supply = <&pm8921_l24>;
>> + vdd-dig-supply = <&pm8921_s3>;
>> + vdd-core-supply = <&saw1_vreg>;
>> interconnects = <&kraitcc MASTER_KRAIT_L2 &kraitcc SLAVE_KRAIT_L2>;
>> operating-points-v2 = <&cpu_opp_table>;
>> #cooling-cells = <2>;
>> @@ -83,6 +89,9 @@ CPU2: cpu@2 {
>> clocks = <&kraitcc KRAIT_CPU_2>;
>> clock-names = "cpu";
>> clock-latency = <100000>;
>> + vdd-mem-supply = <&pm8921_l24>;
>> + vdd-dig-supply = <&pm8921_s3>;
>> + vdd-core-supply = <&saw2_vreg>;
>> interconnects = <&kraitcc MASTER_KRAIT_L2 &kraitcc SLAVE_KRAIT_L2>;
>> operating-points-v2 = <&cpu_opp_table>;
>> #cooling-cells = <2>;
>> @@ -100,6 +109,9 @@ CPU3: cpu@3 {
>> clocks = <&kraitcc KRAIT_CPU_3>;
>> clock-names = "cpu";
>> clock-latency = <100000>;
>> + vdd-mem-supply = <&pm8921_l24>;
>> + vdd-dig-supply = <&pm8921_s3>;
>> + vdd-core-supply = <&saw3_vreg>;
>> interconnects = <&kraitcc MASTER_KRAIT_L2 &kraitcc SLAVE_KRAIT_L2>;
>> operating-points-v2 = <&cpu_opp_table>;
>> #cooling-cells = <2>;
>> @@ -132,6 +144,81 @@ cpu_opp_table: opp-table-cpu {
>> opp-384000000 {
>> opp-hz = /bits/ 64 <384000000>;
>> opp-peak-kBps = <384000>;
>> + opp-microvolt-speed0-pvs0 = <1050000 1050000 1150000>,
>> + <950000 950000 1150000>,
>> + <950000 950000 975000>;
>
> I think this won't result in the correct switch order without making
> some changes to the OPP core. In _set_opp() the OPP core does
>
> /* Scaling up? Configure required OPPs before frequency */
> if (!scaling_down) {
> _set_required_opps();
> _set_opp_bw();
> opp_table->config_regulators();
> }
>
> opp_table->config_clks();
>
> /* Scaling down? Configure required OPPs after frequency */
> if (scaling_down) {
> opp_table->config_regulators();
> _set_opp_bw();
> _set_required_opps();
> }
>
> Since the "bandwidth" for the L2 cache is set before the regulators
> there is a short window where the L2 clock is running at a high
> frequency with too low voltage, which could potentially cause
> instability. On downstream this seems to be done in the proper order [1].
>
> I'm not sure if the order in the OPP core is on purpose. If not, you
> could propose moving the config_regulators() first (for scaling up)
> and last (for scaling down). This would resolve the problem.
Nice catch, I missed this ordering point.
>
> The alternative that I've already argued for on IRC in #linux-msm a
> couple of days ago would be to give the L2 cache (here: "interconnect")
> an own OPP table where it can describe its voltage requirements,
> independent from the CPU. That way the icc_set_bw() would be guaranteed
> to apply the correct voltage before adjusting the L2 cache clock. It
> looks like the "l2_level" voltages for vdd_dig and vdd_mem are not
> speedbin/PVS-specific [2] so this would also significantly reduce the DT
> size, since you wouldn't need to repeat the same vdd_dig/vdd_mem
> voltages for all of them.
Yes. I fact our discussion triggered me to do this patchset.
So, another option would be to have something like the following
snippet. Do you know if we are allowed to squish additional data into
the L2 cache DT node?
CPU0: cpu@0 {
vdd-core-supply = <&saw0_vreg>;
interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>;
operating-points-v2 = <&cpu_opp_table>;
};
L2: l2-cache {
compatible = "qcom,apq8064-l2-cache", "cache";
clocks = <&kraitcc KRAIT_L2>;
vdd-mem-supply = <&pm8921_l24>;
vdd-dig-supply = <&pm8921_s3>;
operating-points-v2 = <&l2_opp_table>;
l2_opp_table {
compatible = "operating-points-v2";
opp-384000000 {
opp-hz = /bits/ 64 <384000000>;
opp-microvolt = <1050000 1050000 1150000>,
<950000 950000 1150000>;
};
opp-648000000 {
opp-hz = /bits/ 64 <648000000>;
opp-microvolt = <1050000 1050000 1150000>,
<1050000 1050000 1150000>;
};
opp-1134000000 {
opp-hz = /bits/ 64 <1134000000>;
opp-microvolt = <1150000 1150000 1150000>,
<1150000 1150000 1150000>;
};
};
};
>
> Thanks,
> Stephan
>
> [1]: https://git.codelinaro.org/clo/la/kernel/msm/-/blob/LA.AF.1.2.1-08410-8064.0/arch/arm/mach-msm/acpuclock-krait.c#L529-588
> [2]: https://git.codelinaro.org/clo/la/kernel/msm/-/blob/LA.AF.1.2.1-08410-8064.0/arch/arm/mach-msm/acpuclock-8064.c#L118-135
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 15/18] ARM: dts: qcom: apq8064: provide voltage scaling tables
2023-06-12 13:33 ` Dmitry Baryshkov
2023-06-11 22:16 ` Christian Marangi
@ 2023-06-12 13:59 ` Stephan Gerhold
2023-06-12 15:38 ` Dmitry Baryshkov
1 sibling, 1 reply; 36+ messages in thread
From: Stephan Gerhold @ 2023-06-12 13:59 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Ilia Lin, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki, linux-arm-msm, devicetree, linux-pm,
linux-clk, Christian Marangi
On Mon, Jun 12, 2023 at 04:33:09PM +0300, Dmitry Baryshkov wrote:
> On 12/06/2023 12:01, Stephan Gerhold wrote:
> > On Mon, Jun 12, 2023 at 08:39:19AM +0300, Dmitry Baryshkov wrote:
> > > APQ8064 has 4 speed bins, each of them having from 4 to 6 categorization
> > > kinds. Provide tables necessary to handle voltage scaling on this SoC.
> > >
> > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > > ---
> > > arch/arm/boot/dts/qcom-apq8064.dtsi | 1017 +++++++++++++++++++++++++++
> > > 1 file changed, 1017 insertions(+)
> > >
> > > diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
> > > index 4ef13f3d702b..f35853b59544 100644
> > > --- a/arch/arm/boot/dts/qcom-apq8064.dtsi
> > > +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
> > > @@ -49,6 +49,9 @@ CPU0: cpu@0 {
> > > clocks = <&kraitcc KRAIT_CPU_0>;
> > > clock-names = "cpu";
> > > clock-latency = <100000>;
> > > + vdd-mem-supply = <&pm8921_l24>;
> > > + vdd-dig-supply = <&pm8921_s3>;
> > > + vdd-core-supply = <&saw0_vreg>;
> > > interconnects = <&kraitcc MASTER_KRAIT_L2 &kraitcc SLAVE_KRAIT_L2>;
> > > operating-points-v2 = <&cpu_opp_table>;
> > > #cooling-cells = <2>;
> > > @@ -66,6 +69,9 @@ CPU1: cpu@1 {
> > > clocks = <&kraitcc KRAIT_CPU_1>;
> > > clock-names = "cpu";
> > > clock-latency = <100000>;
> > > + vdd-mem-supply = <&pm8921_l24>;
> > > + vdd-dig-supply = <&pm8921_s3>;
> > > + vdd-core-supply = <&saw1_vreg>;
> > > interconnects = <&kraitcc MASTER_KRAIT_L2 &kraitcc SLAVE_KRAIT_L2>;
> > > operating-points-v2 = <&cpu_opp_table>;
> > > #cooling-cells = <2>;
> > > @@ -83,6 +89,9 @@ CPU2: cpu@2 {
> > > clocks = <&kraitcc KRAIT_CPU_2>;
> > > clock-names = "cpu";
> > > clock-latency = <100000>;
> > > + vdd-mem-supply = <&pm8921_l24>;
> > > + vdd-dig-supply = <&pm8921_s3>;
> > > + vdd-core-supply = <&saw2_vreg>;
> > > interconnects = <&kraitcc MASTER_KRAIT_L2 &kraitcc SLAVE_KRAIT_L2>;
> > > operating-points-v2 = <&cpu_opp_table>;
> > > #cooling-cells = <2>;
> > > @@ -100,6 +109,9 @@ CPU3: cpu@3 {
> > > clocks = <&kraitcc KRAIT_CPU_3>;
> > > clock-names = "cpu";
> > > clock-latency = <100000>;
> > > + vdd-mem-supply = <&pm8921_l24>;
> > > + vdd-dig-supply = <&pm8921_s3>;
> > > + vdd-core-supply = <&saw3_vreg>;
> > > interconnects = <&kraitcc MASTER_KRAIT_L2 &kraitcc SLAVE_KRAIT_L2>;
> > > operating-points-v2 = <&cpu_opp_table>;
> > > #cooling-cells = <2>;
> > > @@ -132,6 +144,81 @@ cpu_opp_table: opp-table-cpu {
> > > opp-384000000 {
> > > opp-hz = /bits/ 64 <384000000>;
> > > opp-peak-kBps = <384000>;
> > > + opp-microvolt-speed0-pvs0 = <1050000 1050000 1150000>,
> > > + <950000 950000 1150000>,
> > > + <950000 950000 975000>;
> >
> > I think this won't result in the correct switch order without making
> > some changes to the OPP core. In _set_opp() the OPP core does
> >
> > /* Scaling up? Configure required OPPs before frequency */
> > if (!scaling_down) {
> > _set_required_opps();
> > _set_opp_bw();
> > opp_table->config_regulators();
> > }
> >
> > opp_table->config_clks();
> >
> > /* Scaling down? Configure required OPPs after frequency */
> > if (scaling_down) {
> > opp_table->config_regulators();
> > _set_opp_bw();
> > _set_required_opps();
> > }
> >
> > Since the "bandwidth" for the L2 cache is set before the regulators
> > there is a short window where the L2 clock is running at a high
> > frequency with too low voltage, which could potentially cause
> > instability. On downstream this seems to be done in the proper order [1].
> >
> > I'm not sure if the order in the OPP core is on purpose. If not, you
> > could propose moving the config_regulators() first (for scaling up)
> > and last (for scaling down). This would resolve the problem.
>
> Nice catch, I missed this ordering point.
>
> >
> > The alternative that I've already argued for on IRC in #linux-msm a
> > couple of days ago would be to give the L2 cache (here: "interconnect")
> > an own OPP table where it can describe its voltage requirements,
> > independent from the CPU. That way the icc_set_bw() would be guaranteed
> > to apply the correct voltage before adjusting the L2 cache clock. It
> > looks like the "l2_level" voltages for vdd_dig and vdd_mem are not
> > speedbin/PVS-specific [2] so this would also significantly reduce the DT
> > size, since you wouldn't need to repeat the same vdd_dig/vdd_mem
> > voltages for all of them.
>
> Yes. I fact our discussion triggered me to do this patchset.
>
> So, another option would be to have something like the following snippet. Do
> you know if we are allowed to squish additional data into the L2 cache DT
> node?
>
I suspect no one has tried this before, so only the DT maintainers could
answer this. I would say that it just follows the existing design of
clocks/-supply/OPPs on the CPU nodes. vdd-mem-supply isn't a property of
the CPU, it's a property of the L2 cache so it actually fits better there.
I think the more controversial questions might be:
- Is a L2 cache really an "interconnect"? I suppose one could argue it
connects multiple CPU cores to a cluster (similar how a CCI connects
multiple clusters to a system).
- What would bind to the l2-cache node? A separate driver? Does that
work if it sits below the /cpus node?
Thanks,
Stephan
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 00/18] ARM: qcom: apq8064: support CPU frequency scaling
2023-06-11 16:27 ` Christian Marangi
@ 2023-06-12 14:20 ` Dmitry Baryshkov
2023-06-13 16:19 ` Christian Marangi
0 siblings, 1 reply; 36+ messages in thread
From: Dmitry Baryshkov @ 2023-06-12 14:20 UTC (permalink / raw)
To: Christian Marangi
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Ilia Lin, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki, linux-arm-msm, devicetree, linux-pm,
linux-clk
On 11/06/2023 19:27, Christian Marangi wrote:
> On Mon, Jun 12, 2023 at 08:39:04AM +0300, Dmitry Baryshkov wrote:
>> Implement CPUFreq support for one of the oldest supported Qualcomm
>> platforms, APQ8064. Each core has independent power and frequency
>> control. Additionally the L2 cache is scaled to follow the CPU
>> frequencies (failure to do so results in strange semi-random crashes).
>
> Hi, can we talk, maybe in private about this interconnect-cpu thing?
Hi, sure. Feel free to ping me on IRC (lumag) or via email. Or we can
just continue our discussion here, as it might be interesting to other
people too.
> I see you follow the original implementation of the msm_bus where in
> practice with the use of the kbps the correct clock and voltage was set.
> (and this was also used to set the fabric clock from nominal to fast)
>
> On ipq806x and I assume other SoC there isn't always a 1:1 map of CPU
> freq and L2 freq. For example on ipq8064 we have max CPU freq of 1.4GHz
> and L2 freq of 1.2GHz, on ipq8065 we have CPU 1.7GHz and L2 of 1.4GHz.
This is also the case for apq8064. The vendor kernel defines 15
frequencies for L2 cache clock, but then for some reasons all PVS tables
use just 3 entries from these 15.
> (and even that is curious since I used the debug regs and the cxo
> crystal to measure the clock by hardware (yes i ported the very ancient
> clk-debug to modern kernel and it works and discovered all sort of
> things) the L2 (I assume due to climitation of the hfpll) actually can't
> never reach that frequency (1.4GHz in reality results to something like
> 1.2GHz from what I notice a stable clock is there only with frequency of
> max 1GHz))
I would like to point you to https://github.com/andersson/debugcc/,
which is a userspace reimplementation of clk-debug. We'd appreciate your
patches there.
> So my idea was to introduce a simple devfreq driver and use the PASSIVE
> governor where it was added the possibility to link to a CPU frequency
> and with interpolation select the L2 frequency (and voltage)
I stumbled upon this idea, when I was working on the msm8996 and it's
CBF clock (CBF = interconnect between two core clusters). While it
should be possible to use DEVFREQ in simple cases (e.g. L2 clock >=
max(CPU clock), if possible). However real configurations are slightly
harder.
E.g. for the purpose of this patchset, the relationship for apq8064 is
the following (in MHz):
CPU L2
384 384
486 648
594 648
702 648
.... ...
1026 648
1134 1134
.... ....
1512 1134
.... ....
It should be noted that msm8960 also used just three values for the L2
cache frequencies. From what I can see, only msm8x60 made L2 freq
tightly follow the CPU frequency.
> From some old comments in ancient qsdk code it was pointed out that due
> to a hw limitation the secondary cpu can't stay at a high clock if L2
> was at the idle clock. (no idea if this is specific to IPQ806x) So this
> might be a cause of your crash? (I also have random crash with L2
> scaling and we are planning to just force the L2 at max frequency)
It might be related. It was more or less the same story with msm8996,
which was either 'maxcpus=2' or scaling the CBF clock.
> But sorry for all of this (maybe) useless info. I checked the other
> patch and I didn't understand how the different L2 frequency are
> declared and even the voltage. Is this something that will come later?
> I'm very interested in this implementation.
The L2 frequency (<&kraitcc 4>) is converted into bandwidth vote, which
then goes into the OPP tables. But please also see the discussion
started at the patch 15.
>
>>
>> Core voltage is controlled through the SAW2 devices, one for each core.
>> The L2 has two regulators, vdd-mem and vdd-dig.
>>
>> Depenency: [1] for interconnect-clk implementation
>>
>> https://lore.kernel.org/linux-arm-msm/20230512001334.2983048-3-dmitry.baryshkov@linaro.org/
>>
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 15/18] ARM: dts: qcom: apq8064: provide voltage scaling tables
2023-06-12 13:59 ` Stephan Gerhold
@ 2023-06-12 15:38 ` Dmitry Baryshkov
0 siblings, 0 replies; 36+ messages in thread
From: Dmitry Baryshkov @ 2023-06-12 15:38 UTC (permalink / raw)
To: Stephan Gerhold
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Ilia Lin, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki, linux-arm-msm, devicetree, linux-pm,
linux-clk, Christian Marangi
On 12/06/2023 16:59, Stephan Gerhold wrote:
> On Mon, Jun 12, 2023 at 04:33:09PM +0300, Dmitry Baryshkov wrote:
>> On 12/06/2023 12:01, Stephan Gerhold wrote:
>>> On Mon, Jun 12, 2023 at 08:39:19AM +0300, Dmitry Baryshkov wrote:
>>>> APQ8064 has 4 speed bins, each of them having from 4 to 6 categorization
>>>> kinds. Provide tables necessary to handle voltage scaling on this SoC.
>>>>
>>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>>> ---
>>>> arch/arm/boot/dts/qcom-apq8064.dtsi | 1017 +++++++++++++++++++++++++++
>>>> 1 file changed, 1017 insertions(+)
>>>>
>>>> diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
>>>> index 4ef13f3d702b..f35853b59544 100644
>>>> --- a/arch/arm/boot/dts/qcom-apq8064.dtsi
>>>> +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
>>>> @@ -49,6 +49,9 @@ CPU0: cpu@0 {
>>>> clocks = <&kraitcc KRAIT_CPU_0>;
>>>> clock-names = "cpu";
>>>> clock-latency = <100000>;
>>>> + vdd-mem-supply = <&pm8921_l24>;
>>>> + vdd-dig-supply = <&pm8921_s3>;
>>>> + vdd-core-supply = <&saw0_vreg>;
>>>> interconnects = <&kraitcc MASTER_KRAIT_L2 &kraitcc SLAVE_KRAIT_L2>;
>>>> operating-points-v2 = <&cpu_opp_table>;
>>>> #cooling-cells = <2>;
>>>> @@ -66,6 +69,9 @@ CPU1: cpu@1 {
>>>> clocks = <&kraitcc KRAIT_CPU_1>;
>>>> clock-names = "cpu";
>>>> clock-latency = <100000>;
>>>> + vdd-mem-supply = <&pm8921_l24>;
>>>> + vdd-dig-supply = <&pm8921_s3>;
>>>> + vdd-core-supply = <&saw1_vreg>;
>>>> interconnects = <&kraitcc MASTER_KRAIT_L2 &kraitcc SLAVE_KRAIT_L2>;
>>>> operating-points-v2 = <&cpu_opp_table>;
>>>> #cooling-cells = <2>;
>>>> @@ -83,6 +89,9 @@ CPU2: cpu@2 {
>>>> clocks = <&kraitcc KRAIT_CPU_2>;
>>>> clock-names = "cpu";
>>>> clock-latency = <100000>;
>>>> + vdd-mem-supply = <&pm8921_l24>;
>>>> + vdd-dig-supply = <&pm8921_s3>;
>>>> + vdd-core-supply = <&saw2_vreg>;
>>>> interconnects = <&kraitcc MASTER_KRAIT_L2 &kraitcc SLAVE_KRAIT_L2>;
>>>> operating-points-v2 = <&cpu_opp_table>;
>>>> #cooling-cells = <2>;
>>>> @@ -100,6 +109,9 @@ CPU3: cpu@3 {
>>>> clocks = <&kraitcc KRAIT_CPU_3>;
>>>> clock-names = "cpu";
>>>> clock-latency = <100000>;
>>>> + vdd-mem-supply = <&pm8921_l24>;
>>>> + vdd-dig-supply = <&pm8921_s3>;
>>>> + vdd-core-supply = <&saw3_vreg>;
>>>> interconnects = <&kraitcc MASTER_KRAIT_L2 &kraitcc SLAVE_KRAIT_L2>;
>>>> operating-points-v2 = <&cpu_opp_table>;
>>>> #cooling-cells = <2>;
>>>> @@ -132,6 +144,81 @@ cpu_opp_table: opp-table-cpu {
>>>> opp-384000000 {
>>>> opp-hz = /bits/ 64 <384000000>;
>>>> opp-peak-kBps = <384000>;
>>>> + opp-microvolt-speed0-pvs0 = <1050000 1050000 1150000>,
>>>> + <950000 950000 1150000>,
>>>> + <950000 950000 975000>;
>>>
[skipped the OPP voltage vs bw ordering]
>>
>>>
>>> The alternative that I've already argued for on IRC in #linux-msm a
>>> couple of days ago would be to give the L2 cache (here: "interconnect")
>>> an own OPP table where it can describe its voltage requirements,
>>> independent from the CPU. That way the icc_set_bw() would be guaranteed
>>> to apply the correct voltage before adjusting the L2 cache clock. It
>>> looks like the "l2_level" voltages for vdd_dig and vdd_mem are not
>>> speedbin/PVS-specific [2] so this would also significantly reduce the DT
>>> size, since you wouldn't need to repeat the same vdd_dig/vdd_mem
>>> voltages for all of them.
>>
>> Yes. I fact our discussion triggered me to do this patchset.
>>
>> So, another option would be to have something like the following snippet. Do
>> you know if we are allowed to squish additional data into the L2 cache DT
>> node?
>>
>
> I suspect no one has tried this before, so only the DT maintainers could
> answer this. I would say that it just follows the existing design of
> clocks/-supply/OPPs on the CPU nodes. vdd-mem-supply isn't a property of
> the CPU, it's a property of the L2 cache so it actually fits better there. >
> I think the more controversial questions might be:
>
> - Is a L2 cache really an "interconnect"? I suppose one could argue it
> connects multiple CPU cores to a cluster (similar how a CCI connects
> multiple clusters to a system).
Yes. This was my reasoning for CBF clock as well as for this L2 clock.
The separate L2 cache device is also an interconnect from my POV. It
connects all CPU cores and we have to vote on its frequency.
> - What would bind to the l2-cache node? A separate driver? Does that
> work if it sits below the /cpus node?
In the worst case we'd have to populate that manually. E.g. from the
qcom-cpufreq-nvmem.c
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 04/18] dt-bindings: clock: qcom,krait-cc: Krait core clock controller
[not found] ` <3ce1bd9b0cb23e4e60b093327e705d69.sboyd@kernel.org>
@ 2023-06-12 22:33 ` Dmitry Baryshkov
0 siblings, 0 replies; 36+ messages in thread
From: Dmitry Baryshkov @ 2023-06-12 22:33 UTC (permalink / raw)
To: Stephen Boyd, Andy Gross, Bjorn Andersson, Conor Dooley,
Ilia Lin, Konrad Dybcio, Krzysztof Kozlowski, Michael Turquette,
Nishanth Menon, Rafael J. Wysocki, Rob Herring, Viresh Kumar
Cc: linux-arm-msm, devicetree, linux-pm, linux-clk, Christian Marangi
On 13/06/2023 00:26, Stephen Boyd wrote:
> Quoting Dmitry Baryshkov (2023-06-11 22:39:08)
>> Define bindings for the Qualcomm Krait CPU and L2 clock controller. This
>> device is used on old Qualcomm SoCs (APQ8064, MSM8960) and supports up
>> to 4 core clocks and a separate L2 clock. Furthermore, L2 clock is
>> represented as the interconnect to facilitate L2 frequency scaling
>> together with scaling the CPU frequencies.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
>> include/dt-bindings/clock/qcom,krait-cc.h | 20 ++++++++++++++++++++
>> 1 file changed, 20 insertions(+)
>> create mode 100644 include/dt-bindings/clock/qcom,krait-cc.h
>>
>> diff --git a/include/dt-bindings/clock/qcom,krait-cc.h b/include/dt-bindings/clock/qcom,krait-cc.h
>> new file mode 100644
>> index 000000000000..c3542b6d73e2
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/qcom,krait-cc.h
>> @@ -0,0 +1,20 @@
>> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
>> +/*
>> + * Copyright (C) 2023 Linaro Ltd. All rights reserved.
>> + */
>> +
>> +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_KRAIT_CC_H
>
> Should there be INTERCONNECT here?
Of course, no. I'll fix it for v2 if this part stays intact
>
>> +#define __DT_BINDINGS_INTERCONNECT_QCOM_KRAIT_CC_H
>> +
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 00/18] ARM: qcom: apq8064: support CPU frequency scaling
2023-06-12 14:20 ` Dmitry Baryshkov
@ 2023-06-13 16:19 ` Christian Marangi
2023-06-14 20:18 ` Dmitry Baryshkov
0 siblings, 1 reply; 36+ messages in thread
From: Christian Marangi @ 2023-06-13 16:19 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Ilia Lin, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki, linux-arm-msm, devicetree, linux-pm,
linux-clk
On Mon, Jun 12, 2023 at 05:20:02PM +0300, Dmitry Baryshkov wrote:
> On 11/06/2023 19:27, Christian Marangi wrote:
> > On Mon, Jun 12, 2023 at 08:39:04AM +0300, Dmitry Baryshkov wrote:
> > > Implement CPUFreq support for one of the oldest supported Qualcomm
> > > platforms, APQ8064. Each core has independent power and frequency
> > > control. Additionally the L2 cache is scaled to follow the CPU
> > > frequencies (failure to do so results in strange semi-random crashes).
> >
> > Hi, can we talk, maybe in private about this interconnect-cpu thing?
>
> Hi, sure. Feel free to ping me on IRC (lumag) or via email. Or we can just
> continue our discussion here, as it might be interesting to other people
> too.
>
Don't know if here is the right place to discuss my concern and problem
with L2 scaling on ipq8064...
> > I see you follow the original implementation of the msm_bus where in
> > practice with the use of the kbps the correct clock and voltage was set.
> > (and this was also used to set the fabric clock from nominal to fast)
> >
> > On ipq806x and I assume other SoC there isn't always a 1:1 map of CPU
> > freq and L2 freq. For example on ipq8064 we have max CPU freq of 1.4GHz
> > and L2 freq of 1.2GHz, on ipq8065 we have CPU 1.7GHz and L2 of 1.4GHz.
>
> This is also the case for apq8064. The vendor kernel defines 15 frequencies
> for L2 cache clock, but then for some reasons all PVS tables use just 3
> entries from these 15.
>
Eh who knows why they did this... Probably the hfpll was limited or they
notice no temp/power benefits were present with scaling with that much
of steps?
> > (and even that is curious since I used the debug regs and the cxo
> > crystal to measure the clock by hardware (yes i ported the very ancient
> > clk-debug to modern kernel and it works and discovered all sort of
> > things) the L2 (I assume due to climitation of the hfpll) actually can't
> > never reach that frequency (1.4GHz in reality results to something like
> > 1.2GHz from what I notice a stable clock is there only with frequency of
> > max 1GHz))
>
> I would like to point you to https://github.com/andersson/debugcc/, which is
> a userspace reimplementation of clk-debug. We'd appreciate your patches
> there.
>
Hi, I wasted some good time on the implementation but manage to make it
work and proposed a pr! I assume the thing can be reused for apq8064 if
someone ever wants to have fun with that.
> > So my idea was to introduce a simple devfreq driver and use the PASSIVE
> > governor where it was added the possibility to link to a CPU frequency
> > and with interpolation select the L2 frequency (and voltage)
>
> I stumbled upon this idea, when I was working on the msm8996 and it's CBF
> clock (CBF = interconnect between two core clusters). While it should be
> possible to use DEVFREQ in simple cases (e.g. L2 clock >= max(CPU clock), if
> possible). However real configurations are slightly harder.
> E.g. for the purpose of this patchset, the relationship for apq8064 is the
> following (in MHz):
>
> CPU L2
> 384 384
> 486 648
> 594 648
> 702 648
> .... ...
> 1026 648
> 1134 1134
> .... ....
> 1512 1134
> .... ....
>
> It should be noted that msm8960 also used just three values for the L2 cache
> frequencies. From what I can see, only msm8x60 made L2 freq tightly follow
> the CPU frequency.
>
Happy to test and found a common path... With the merge of the cpu opp
and nvmem work, I was just about to send the L2 devfreq driver... And
also the fabric devfreq driver. But I wonder if I can use this
interconnect thing for the 2 task.
> > From some old comments in ancient qsdk code it was pointed out that due
> > to a hw limitation the secondary cpu can't stay at a high clock if L2
> > was at the idle clock. (no idea if this is specific to IPQ806x) So this
> > might be a cause of your crash? (I also have random crash with L2
> > scaling and we are planning to just force the L2 at max frequency)
>
> It might be related. It was more or less the same story with msm8996, which
> was either 'maxcpus=2' or scaling the CBF clock.
>
Might be a krait defect... and this is pretty bad...
> > But sorry for all of this (maybe) useless info. I checked the other
> > patch and I didn't understand how the different L2 frequency are
> > declared and even the voltage. Is this something that will come later?
> > I'm very interested in this implementation.
>
> The L2 frequency (<&kraitcc 4>) is converted into bandwidth vote, which then
> goes into the OPP tables. But please also see the discussion started at the
> patch 15.
>
I didn't notice you were defining multiple supply, scaling the voltage
under the hood with that trick. It's not a bad idea but as pointed out
it might be problematic, since is seems krait is very sensible with L2
frequency and voltage so we should simulate the original implementation
as close as possible...
> >
> > >
> > > Core voltage is controlled through the SAW2 devices, one for each core.
> > > The L2 has two regulators, vdd-mem and vdd-dig.
> > >
> > > Depenency: [1] for interconnect-clk implementation
> > >
> > > https://lore.kernel.org/linux-arm-msm/20230512001334.2983048-3-dmitry.baryshkov@linaro.org/
> > >
> >
>
> --
> With best wishes
> Dmitry
>
--
Ansuel
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 01/18] dt-bindings: opp: opp-v2-kryo-cpu: support Qualcomm Krait SoCs
2023-06-12 5:39 ` [PATCH 01/18] dt-bindings: opp: opp-v2-kryo-cpu: support Qualcomm Krait SoCs Dmitry Baryshkov
@ 2023-06-14 16:01 ` Krzysztof Kozlowski
2023-06-14 20:11 ` Dmitry Baryshkov
0 siblings, 1 reply; 36+ messages in thread
From: Krzysztof Kozlowski @ 2023-06-14 16:01 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Ilia Lin,
Viresh Kumar, Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki
Cc: linux-arm-msm, devicetree, linux-pm, linux-clk, Christian Marangi
On 12/06/2023 07:39, Dmitry Baryshkov wrote:
> Exted the opp-v2-kryo-cpu.yaml to support defining OPP tables for the
> previous generation of Qualcomm CPUs, 32-bit Krait-based platforms.
>
> It makes no sense to use 'operating-points-v2-kryo-cpu' compatibility
> node for the Krait cores. Add support for the Krait-specific
> 'operating-points-v2-krait-cpu' compatibility string and the relevant
> opp-microvolt subclasses properties.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> .../devicetree/bindings/opp/opp-v2-kryo-cpu.yaml | 11 +++++++----
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml b/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml
> index bbbad31ae4ca..93ec778bf333 100644
> --- a/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml
> +++ b/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml
> @@ -26,7 +26,9 @@ description: |
>
> properties:
> compatible:
> - const: operating-points-v2-kryo-cpu
> + enum:
> + - operating-points-v2-krait-cpu
> + - operating-points-v2-kryo-cpu
>
> nvmem-cells:
> description: |
> @@ -63,14 +65,15 @@ patternProperties:
> 5: MSM8996SG, speedbin 1
> 6: MSM8996SG, speedbin 2
> 7-31: unused
> - enum: [0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7,
> - 0x9, 0xd, 0xe, 0xf,
> - 0x10, 0x20, 0x30, 0x70]
Why?
> + $ref: /schemas/types.yaml#/definitions/uint32
You are changing the type. No. It should be fixed instead (enum applies
to items).
>
> clock-latency-ns: true
>
> required-opps: true
>
> + patternProperties:
> + '^opp-microvolt-speed[0-9]+-pvs[0-9]+$': true
I don't think it is a common property, so it needs description and
specific type. Specifically "pvs[0-9]" something entirely new.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 02/18] dt-bindings: soc: qcom: merge qcom,saw2.txt into qcom,spm.yaml
2023-06-12 5:39 ` [PATCH 02/18] dt-bindings: soc: qcom: merge qcom,saw2.txt into qcom,spm.yaml Dmitry Baryshkov
@ 2023-06-14 16:03 ` Krzysztof Kozlowski
0 siblings, 0 replies; 36+ messages in thread
From: Krzysztof Kozlowski @ 2023-06-14 16:03 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Ilia Lin,
Viresh Kumar, Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki
Cc: linux-arm-msm, devicetree, linux-pm, linux-clk, Christian Marangi
On 12/06/2023 07:39, Dmitry Baryshkov wrote:
> The Qualcomm SPM / SAW2 device is described in two bindigns files:
> arm/msm/qcom,saw2.txt and soc/qcom/qcom,spm.yaml. Merge the former into
> the latter, adding detailed device node description. While we are at it,
> also rename qcom,spm.yaml to qcom,saw2.yaml to follow the actual
> compatible used for these devices.
>
You also dropped "regulator" property. Please mention in the commit msg why.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 03/18] dt-bindings: soc: qcom: qcom,saw2: define optional regulator node
2023-06-12 5:39 ` [PATCH 03/18] dt-bindings: soc: qcom: qcom,saw2: define optional regulator node Dmitry Baryshkov
@ 2023-06-14 16:05 ` Krzysztof Kozlowski
2023-06-14 22:49 ` Dmitry Baryshkov
0 siblings, 1 reply; 36+ messages in thread
From: Krzysztof Kozlowski @ 2023-06-14 16:05 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Ilia Lin,
Viresh Kumar, Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki
Cc: linux-arm-msm, devicetree, linux-pm, linux-clk, Christian Marangi
On 12/06/2023 07:39, Dmitry Baryshkov wrote:
> The SAW2 device can optionally provide a voltage regulator supplying the
> CPU core, cluster or L2 cache. Describe it in the device bindings.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> .../devicetree/bindings/soc/qcom/qcom,saw2.yaml | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml
> index a016242367b9..b809a9cc0916 100644
> --- a/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml
> +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml
> @@ -47,6 +47,10 @@ properties:
> - description: Base address and size of the alias register region
> minItems: 1
>
> + regulator:
> + $ref: /schemas/regulator/regulator.yaml#
There was such property in the binding (and DTS!) but a bool. Previous
patch silently dropped it, so re-introducing it with different type is
confusing.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 01/18] dt-bindings: opp: opp-v2-kryo-cpu: support Qualcomm Krait SoCs
2023-06-14 16:01 ` Krzysztof Kozlowski
@ 2023-06-14 20:11 ` Dmitry Baryshkov
2023-06-21 8:51 ` Krzysztof Kozlowski
0 siblings, 1 reply; 36+ messages in thread
From: Dmitry Baryshkov @ 2023-06-14 20:11 UTC (permalink / raw)
To: Krzysztof Kozlowski, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Ilia Lin, Viresh Kumar, Nishanth Menon, Stephen Boyd,
Michael Turquette, Rafael J. Wysocki
Cc: linux-arm-msm, devicetree, linux-pm, linux-clk, Christian Marangi
On 14/06/2023 19:01, Krzysztof Kozlowski wrote:
> On 12/06/2023 07:39, Dmitry Baryshkov wrote:
>> Exted the opp-v2-kryo-cpu.yaml to support defining OPP tables for the
>> previous generation of Qualcomm CPUs, 32-bit Krait-based platforms.
>>
>> It makes no sense to use 'operating-points-v2-kryo-cpu' compatibility
>> node for the Krait cores. Add support for the Krait-specific
>> 'operating-points-v2-krait-cpu' compatibility string and the relevant
>> opp-microvolt subclasses properties.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
>> .../devicetree/bindings/opp/opp-v2-kryo-cpu.yaml | 11 +++++++----
>> 1 file changed, 7 insertions(+), 4 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml b/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml
>> index bbbad31ae4ca..93ec778bf333 100644
>> --- a/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml
>> +++ b/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml
>> @@ -26,7 +26,9 @@ description: |
>>
>> properties:
>> compatible:
>> - const: operating-points-v2-kryo-cpu
>> + enum:
>> + - operating-points-v2-krait-cpu
>> + - operating-points-v2-kryo-cpu
>>
>> nvmem-cells:
>> description: |
>> @@ -63,14 +65,15 @@ patternProperties:
>> 5: MSM8996SG, speedbin 1
>> 6: MSM8996SG, speedbin 2
>> 7-31: unused
>> - enum: [0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7,
>> - 0x9, 0xd, 0xe, 0xf,
>> - 0x10, 0x20, 0x30, 0x70]
>
> Why?
>
>> + $ref: /schemas/types.yaml#/definitions/uint32
>
> You are changing the type. No. It should be fixed instead (enum applies
> to items).
Currenlty this bindings are only usable for msm8996/msm8996pro. As such
we listed opp-supported-hw values that are applicable to this platform.
This series adds support for apq8064 platform, which will add new items
to this enum. I think it is not very sensible to list all of them here.
However granted there is already a good enough base type definition, I
think it would be better to drop the $ref, drop the enum, add ': true'
(is it necessary if we have a description already?) and expand
documentation.
>
>>
>> clock-latency-ns: true
>>
>> required-opps: true
>>
>> + patternProperties:
>> + '^opp-microvolt-speed[0-9]+-pvs[0-9]+$': true
>
> I don't think it is a common property, so it needs description and
> specific type. Specifically "pvs[0-9]" something entirely new.
Ack.
>
>
>
> Best regards,
> Krzysztof
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 00/18] ARM: qcom: apq8064: support CPU frequency scaling
2023-06-13 16:19 ` Christian Marangi
@ 2023-06-14 20:18 ` Dmitry Baryshkov
0 siblings, 0 replies; 36+ messages in thread
From: Dmitry Baryshkov @ 2023-06-14 20:18 UTC (permalink / raw)
To: Christian Marangi
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Ilia Lin, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki, linux-arm-msm, devicetree, linux-pm,
linux-clk
On 13/06/2023 19:19, Christian Marangi wrote:
> On Mon, Jun 12, 2023 at 05:20:02PM +0300, Dmitry Baryshkov wrote:
>> On 11/06/2023 19:27, Christian Marangi wrote:
>>> On Mon, Jun 12, 2023 at 08:39:04AM +0300, Dmitry Baryshkov wrote:
>>>> Implement CPUFreq support for one of the oldest supported Qualcomm
>>>> platforms, APQ8064. Each core has independent power and frequency
>>>> control. Additionally the L2 cache is scaled to follow the CPU
>>>> frequencies (failure to do so results in strange semi-random crashes).
>>>
>>> Hi, can we talk, maybe in private about this interconnect-cpu thing?
>>
>> Hi, sure. Feel free to ping me on IRC (lumag) or via email. Or we can just
>> continue our discussion here, as it might be interesting to other people
>> too.
>>
>
> Don't know if here is the right place to discuss my concern and problem
> with L2 scaling on ipq8064...
I think I will try segregating L2 data to l2-cache device node (I saw
your comment that it is not populated by default. I'll have to fix this).
>
>>> I see you follow the original implementation of the msm_bus where in
>>> practice with the use of the kbps the correct clock and voltage was set.
>>> (and this was also used to set the fabric clock from nominal to fast)
>>>
>>> On ipq806x and I assume other SoC there isn't always a 1:1 map of CPU
>>> freq and L2 freq. For example on ipq8064 we have max CPU freq of 1.4GHz
>>> and L2 freq of 1.2GHz, on ipq8065 we have CPU 1.7GHz and L2 of 1.4GHz.
>>
>> This is also the case for apq8064. The vendor kernel defines 15 frequencies
>> for L2 cache clock, but then for some reasons all PVS tables use just 3
>> entries from these 15.
>>
>
> Eh who knows why they did this... Probably the hfpll was limited or they
> notice no temp/power benefits were present with scaling with that much
> of steps?
>
>>> (and even that is curious since I used the debug regs and the cxo
>>> crystal to measure the clock by hardware (yes i ported the very ancient
>>> clk-debug to modern kernel and it works and discovered all sort of
>>> things) the L2 (I assume due to climitation of the hfpll) actually can't
>>> never reach that frequency (1.4GHz in reality results to something like
>>> 1.2GHz from what I notice a stable clock is there only with frequency of
>>> max 1GHz))
>>
>> I would like to point you to https://github.com/andersson/debugcc/, which is
>> a userspace reimplementation of clk-debug. We'd appreciate your patches
>> there.
>>
>
> Hi, I wasted some good time on the implementation but manage to make it
> work and proposed a pr! I assume the thing can be reused for apq8064 if
> someone ever wants to have fun with that.
Thanks a lot! Generally I think that debugcc is a very valuable
debugging tool and it should be getting more attention from the
community. With the chips newer than 8064 it is easy enough to add new
platform data.
>
>>> So my idea was to introduce a simple devfreq driver and use the PASSIVE
>>> governor where it was added the possibility to link to a CPU frequency
>>> and with interpolation select the L2 frequency (and voltage)
>>
>> I stumbled upon this idea, when I was working on the msm8996 and it's CBF
>> clock (CBF = interconnect between two core clusters). While it should be
>> possible to use DEVFREQ in simple cases (e.g. L2 clock >= max(CPU clock), if
>> possible). However real configurations are slightly harder.
>> E.g. for the purpose of this patchset, the relationship for apq8064 is the
>> following (in MHz):
>>
>> CPU L2
>> 384 384
>> 486 648
>> 594 648
>> 702 648
>> .... ...
>> 1026 648
>> 1134 1134
>> .... ....
>> 1512 1134
>> .... ....
>>
>> It should be noted that msm8960 also used just three values for the L2 cache
>> frequencies. From what I can see, only msm8x60 made L2 freq tightly follow
>> the CPU frequency.
>>
>
> Happy to test and found a common path... With the merge of the cpu opp
> and nvmem work, I was just about to send the L2 devfreq driver... And
> also the fabric devfreq driver. But I wonder if I can use this
> interconnect thing for the 2 task.
>
>>> From some old comments in ancient qsdk code it was pointed out that due
>>> to a hw limitation the secondary cpu can't stay at a high clock if L2
>>> was at the idle clock. (no idea if this is specific to IPQ806x) So this
>>> might be a cause of your crash? (I also have random crash with L2
>>> scaling and we are planning to just force the L2 at max frequency)
>>
>> It might be related. It was more or less the same story with msm8996, which
>> was either 'maxcpus=2' or scaling the CBF clock.
>>
>
> Might be a krait defect... and this is pretty bad...
I don't know if it is a defect or just a misfeature. Anyway, we know
that L2 should be clocked high enough and we can cope with it.
>
>>> But sorry for all of this (maybe) useless info. I checked the other
>>> patch and I didn't understand how the different L2 frequency are
>>> declared and even the voltage. Is this something that will come later?
>>> I'm very interested in this implementation.
>>
>> The L2 frequency (<&kraitcc 4>) is converted into bandwidth vote, which then
>> goes into the OPP tables. But please also see the discussion started at the
>> patch 15.
>>
>
> I didn't notice you were defining multiple supply, scaling the voltage
> under the hood with that trick. It's not a bad idea but as pointed out
> it might be problematic, since is seems krait is very sensible with L2
> frequency and voltage so we should simulate the original implementation
> as close as possible...
It was my original intention,as the vendor kernel does it in the
vdd-mem, vdd-dig, vdd-core, L2-freq, core freq order. I did not expect
that voltages are scaled after BW casts. (this describes freq-increase
case, in case of decreasing frequency the order is inverted).
>
>>>
>>>>
>>>> Core voltage is controlled through the SAW2 devices, one for each core.
>>>> The L2 has two regulators, vdd-mem and vdd-dig.
>>>>
>>>> Depenency: [1] for interconnect-clk implementation
>>>>
>>>> https://lore.kernel.org/linux-arm-msm/20230512001334.2983048-3-dmitry.baryshkov@linaro.org/
>>>>
>>>
>>
>> --
>> With best wishes
>> Dmitry
>>
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 03/18] dt-bindings: soc: qcom: qcom,saw2: define optional regulator node
2023-06-14 16:05 ` Krzysztof Kozlowski
@ 2023-06-14 22:49 ` Dmitry Baryshkov
2023-06-21 8:46 ` Krzysztof Kozlowski
0 siblings, 1 reply; 36+ messages in thread
From: Dmitry Baryshkov @ 2023-06-14 22:49 UTC (permalink / raw)
To: Krzysztof Kozlowski, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Ilia Lin, Viresh Kumar, Nishanth Menon, Stephen Boyd,
Michael Turquette, Rafael J. Wysocki
Cc: linux-arm-msm, devicetree, linux-pm, linux-clk, Christian Marangi
On 14/06/2023 19:05, Krzysztof Kozlowski wrote:
> On 12/06/2023 07:39, Dmitry Baryshkov wrote:
>> The SAW2 device can optionally provide a voltage regulator supplying the
>> CPU core, cluster or L2 cache. Describe it in the device bindings.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
>> .../devicetree/bindings/soc/qcom/qcom,saw2.yaml | 17 +++++++++++++++++
>> 1 file changed, 17 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml
>> index a016242367b9..b809a9cc0916 100644
>> --- a/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml
>> +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml
>> @@ -47,6 +47,10 @@ properties:
>> - description: Base address and size of the alias register region
>> minItems: 1
>>
>> + regulator:
>> + $ref: /schemas/regulator/regulator.yaml#
>
> There was such property in the binding (and DTS!) but a bool. Previous
> patch silently dropped it, so re-introducing it with different type is
> confusing.
Could you please propose a better name here? saw-regulator? Or maybe
regulator-saw? (as we might get regulator-avs at some point).
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 03/18] dt-bindings: soc: qcom: qcom,saw2: define optional regulator node
2023-06-14 22:49 ` Dmitry Baryshkov
@ 2023-06-21 8:46 ` Krzysztof Kozlowski
0 siblings, 0 replies; 36+ messages in thread
From: Krzysztof Kozlowski @ 2023-06-21 8:46 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Ilia Lin,
Viresh Kumar, Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki
Cc: linux-arm-msm, devicetree, linux-pm, linux-clk, Christian Marangi
On 15/06/2023 00:49, Dmitry Baryshkov wrote:
> On 14/06/2023 19:05, Krzysztof Kozlowski wrote:
>> On 12/06/2023 07:39, Dmitry Baryshkov wrote:
>>> The SAW2 device can optionally provide a voltage regulator supplying the
>>> CPU core, cluster or L2 cache. Describe it in the device bindings.
>>>
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>> ---
>>> .../devicetree/bindings/soc/qcom/qcom,saw2.yaml | 17 +++++++++++++++++
>>> 1 file changed, 17 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml
>>> index a016242367b9..b809a9cc0916 100644
>>> --- a/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml
>>> +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml
>>> @@ -47,6 +47,10 @@ properties:
>>> - description: Base address and size of the alias register region
>>> minItems: 1
>>>
>>> + regulator:
>>> + $ref: /schemas/regulator/regulator.yaml#
>>
>> There was such property in the binding (and DTS!) but a bool. Previous
>> patch silently dropped it, so re-introducing it with different type is
>> confusing.
>
> Could you please propose a better name here? saw-regulator? Or maybe
> regulator-saw? (as we might get regulator-avs at some point).
regulator name is OK for me, but any ABI change should be:
1. Clearly expressed with rationale,
2. Done probably in one DT commit, not two. IOW, first silently dropping
a property and then adding a new one like nothing happened is not good.
It should be clear that old property is wrong because foo bar and we
make it now different with breaking all the DTS because foo bar.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 01/18] dt-bindings: opp: opp-v2-kryo-cpu: support Qualcomm Krait SoCs
2023-06-14 20:11 ` Dmitry Baryshkov
@ 2023-06-21 8:51 ` Krzysztof Kozlowski
0 siblings, 0 replies; 36+ messages in thread
From: Krzysztof Kozlowski @ 2023-06-21 8:51 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Ilia Lin,
Viresh Kumar, Nishanth Menon, Stephen Boyd, Michael Turquette,
Rafael J. Wysocki
Cc: linux-arm-msm, devicetree, linux-pm, linux-clk, Christian Marangi
On 14/06/2023 22:11, Dmitry Baryshkov wrote:
>> Why?
>>
>>> + $ref: /schemas/types.yaml#/definitions/uint32
>>
>> You are changing the type. No. It should be fixed instead (enum applies
>> to items).
>
> Currenlty this bindings are only usable for msm8996/msm8996pro. As such
> we listed opp-supported-hw values that are applicable to this platform.
> This series adds support for apq8064 platform, which will add new items
> to this enum. I think it is not very sensible to list all of them here.
Sure, but this is uint32-matrix, so don't change the type to something else.
>
> However granted there is already a good enough base type definition, I
> think it would be better to drop the $ref, drop the enum, add ': true'
> (is it necessary if we have a description already?) and expand
> documentation.
Probably this should be constrained to only one value with:
items:
- items:
- description: foo bar
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 36+ messages in thread
end of thread, other threads:[~2023-06-21 8:51 UTC | newest]
Thread overview: 36+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-06-12 5:39 [PATCH 00/18] ARM: qcom: apq8064: support CPU frequency scaling Dmitry Baryshkov
2023-06-11 16:27 ` Christian Marangi
2023-06-12 14:20 ` Dmitry Baryshkov
2023-06-13 16:19 ` Christian Marangi
2023-06-14 20:18 ` Dmitry Baryshkov
2023-06-12 5:39 ` [PATCH 01/18] dt-bindings: opp: opp-v2-kryo-cpu: support Qualcomm Krait SoCs Dmitry Baryshkov
2023-06-14 16:01 ` Krzysztof Kozlowski
2023-06-14 20:11 ` Dmitry Baryshkov
2023-06-21 8:51 ` Krzysztof Kozlowski
2023-06-12 5:39 ` [PATCH 02/18] dt-bindings: soc: qcom: merge qcom,saw2.txt into qcom,spm.yaml Dmitry Baryshkov
2023-06-14 16:03 ` Krzysztof Kozlowski
2023-06-12 5:39 ` [PATCH 03/18] dt-bindings: soc: qcom: qcom,saw2: define optional regulator node Dmitry Baryshkov
2023-06-14 16:05 ` Krzysztof Kozlowski
2023-06-14 22:49 ` Dmitry Baryshkov
2023-06-21 8:46 ` Krzysztof Kozlowski
2023-06-12 5:39 ` [PATCH 04/18] dt-bindings: clock: qcom,krait-cc: Krait core clock controller Dmitry Baryshkov
[not found] ` <3ce1bd9b0cb23e4e60b093327e705d69.sboyd@kernel.org>
2023-06-12 22:33 ` Dmitry Baryshkov
2023-06-12 5:39 ` [PATCH 05/18] clk: qcom: krait-cc: rewrite driver to use clk_hw instead of clk Dmitry Baryshkov
2023-06-12 5:39 ` [PATCH 06/18] clk: qcom: krait-cc: export L2 clock as an interconnect Dmitry Baryshkov
2023-06-12 5:39 ` [PATCH 07/18] soc: qcom: spm: add support for voltage regulator Dmitry Baryshkov
2023-06-12 5:39 ` [PATCH 08/18] cpufreq: qcom-nvmem: also accept operating-points-v2-krait-cpu Dmitry Baryshkov
2023-06-12 5:39 ` [PATCH 09/18] cpufreq: qcom-nvmem: Add support for voltage scaling Dmitry Baryshkov
2023-06-12 5:39 ` [PATCH 10/18] cpufreq: qcom-nvmem: drop pvs_ver for format a fuses Dmitry Baryshkov
2023-06-12 5:39 ` [PATCH 11/18] cpufreq: qcom-nvmem: provide separate configuration data for apq8064 Dmitry Baryshkov
2023-06-12 5:39 ` [PATCH 12/18] ARM: dts: qcom: apq8064: rename SAW nodes to power-manager Dmitry Baryshkov
2023-06-12 5:39 ` [PATCH 13/18] ARM: dts: qcom: apq8064: declare SAW2 regulators Dmitry Baryshkov
2023-06-12 5:39 ` [PATCH 14/18] ARM: dts: qcom: apq8064: add simple CPUFreq support Dmitry Baryshkov
2023-06-12 5:39 ` [PATCH 15/18] ARM: dts: qcom: apq8064: provide voltage scaling tables Dmitry Baryshkov
2023-06-12 9:01 ` Stephan Gerhold
2023-06-12 13:33 ` Dmitry Baryshkov
2023-06-11 22:16 ` Christian Marangi
2023-06-12 13:59 ` Stephan Gerhold
2023-06-12 15:38 ` Dmitry Baryshkov
2023-06-12 5:39 ` [PATCH 16/18] ARM: dts: qcom: apq8064: enable passive CPU cooling Dmitry Baryshkov
2023-06-12 5:39 ` [PATCH 17/18] ARM: dts: qcom: apq8064-asus-nexus7-flo: constraint cpufreq regulators Dmitry Baryshkov
2023-06-12 5:39 ` [PATCH 18/18] ARM: dts: qcom: apq8064-ifc6410: " Dmitry Baryshkov
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).