* [PATCH v1 0/3] Update dt-bindings and sa2ul driver for AM64x SoCs @ 2021-03-08 20:20 Vaibhav Gupta 2021-03-08 20:20 ` [PATCH v1 1/3] dt-bindings: crypto: ti,sa2ul: Add new compatible for AM64 Vaibhav Gupta ` (2 more replies) 0 siblings, 3 replies; 12+ messages in thread From: Vaibhav Gupta @ 2021-03-08 20:20 UTC (permalink / raw) To: Herbert Xu, David S. Miller, Rob Herring Cc: Kishon Vijay Abraham, Sekhar Nori, Lokesh Vutla, Praneeth Bajjuri, Gowtham Tammana, linux-crypto, devicetree, linux-kernel From: Vaibhav Gupta <v_gupta@ti.com> This patch series aims to modify necessary files before an entry for sa2ul can be made in the respective am64 device tree. Peter Ujfalusi (3): dt-bindings: crypto: ti,sa2ul: Add new compatible for AM64 crypto: sa2ul: Support for per channel coherency crypto: sa2ul: Add support for AM64 .../devicetree/bindings/crypto/ti,sa2ul.yaml | 40 +++++- drivers/crypto/sa2ul.c | 133 ++++++++++++------ drivers/crypto/sa2ul.h | 4 + 3 files changed, 130 insertions(+), 47 deletions(-) -- 2.30.1 ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v1 1/3] dt-bindings: crypto: ti,sa2ul: Add new compatible for AM64 2021-03-08 20:20 [PATCH v1 0/3] Update dt-bindings and sa2ul driver for AM64x SoCs Vaibhav Gupta @ 2021-03-08 20:20 ` Vaibhav Gupta 2021-03-16 22:05 ` Rob Herring 2021-03-08 20:20 ` [PATCH v1 2/3] crypto: sa2ul: Support for per channel coherency Vaibhav Gupta 2021-03-08 20:20 ` [PATCH v1 3/3] crypto: sa2ul: Add support for AM64 Vaibhav Gupta 2 siblings, 1 reply; 12+ messages in thread From: Vaibhav Gupta @ 2021-03-08 20:20 UTC (permalink / raw) To: Herbert Xu, David S. Miller, Rob Herring Cc: Kishon Vijay Abraham, Sekhar Nori, Lokesh Vutla, Praneeth Bajjuri, Gowtham Tammana, linux-crypto, devicetree, linux-kernel, Peter Ujfalusi, Vaibhav Gupta From: Peter Ujfalusi <peter.ujfalusi@ti.com> Add the AM64 version of sa2ul to the compatible list. [v_gupta@ti.com: Conditional dma-coherent requirement, clocks] Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vaibhav Gupta <v_gupta@ti.com> --- .../devicetree/bindings/crypto/ti,sa2ul.yaml | 40 +++++++++++++++---- 1 file changed, 33 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/crypto/ti,sa2ul.yaml b/Documentation/devicetree/bindings/crypto/ti,sa2ul.yaml index 1d48ac712b23..6eb9acd564c2 100644 --- a/Documentation/devicetree/bindings/crypto/ti,sa2ul.yaml +++ b/Documentation/devicetree/bindings/crypto/ti,sa2ul.yaml @@ -14,6 +14,7 @@ properties: enum: - ti,j721e-sa2ul - ti,am654-sa2ul + - ti,am64-sa2ul reg: maxItems: 1 @@ -45,19 +46,44 @@ properties: description: Address translation for the possible RNG child node for SA2UL + clocks: + items: + - description: Clock used by PKA + - description: Main Input Clock + - description: Clock used by rng + + clock-names: + items: + - const: pka_in_clk + - const: x1_clk + - const: x2_clk + patternProperties: "^rng@[a-f0-9]+$": type: object description: Child RNG node for SA2UL -required: - - compatible - - reg - - power-domains - - dmas - - dma-names - - dma-coherent +if: + properties: + compatible: + const: ti,am64-sa2ul +then: + required: + - compatible + - reg + - power-domains + - dmas + - dma-names + +else: + required: + - compatible + - reg + - power-domains + - dmas + - dma-names + - dma-coherent additionalProperties: false -- 2.30.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v1 1/3] dt-bindings: crypto: ti,sa2ul: Add new compatible for AM64 2021-03-08 20:20 ` [PATCH v1 1/3] dt-bindings: crypto: ti,sa2ul: Add new compatible for AM64 Vaibhav Gupta @ 2021-03-16 22:05 ` Rob Herring 2021-03-17 4:16 ` Vaibhav Gupta 2021-04-13 9:15 ` [PATCH v2 0/3] Update dt-bindings and sa2ul driver for AM64x SoCs Vaibhav Gupta 0 siblings, 2 replies; 12+ messages in thread From: Rob Herring @ 2021-03-16 22:05 UTC (permalink / raw) To: Vaibhav Gupta Cc: Herbert Xu, David S. Miller, Kishon Vijay Abraham, Sekhar Nori, Lokesh Vutla, Praneeth Bajjuri, Gowtham Tammana, linux-crypto, devicetree, linux-kernel, Peter Ujfalusi, Vaibhav Gupta On Tue, Mar 09, 2021 at 01:50:03AM +0530, Vaibhav Gupta wrote: > From: Peter Ujfalusi <peter.ujfalusi@ti.com> > > Add the AM64 version of sa2ul to the compatible list. > > [v_gupta@ti.com: Conditional dma-coherent requirement, clocks] > Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> > Signed-off-by: Vaibhav Gupta <v_gupta@ti.com> > --- > .../devicetree/bindings/crypto/ti,sa2ul.yaml | 40 +++++++++++++++---- > 1 file changed, 33 insertions(+), 7 deletions(-) > > diff --git a/Documentation/devicetree/bindings/crypto/ti,sa2ul.yaml b/Documentation/devicetree/bindings/crypto/ti,sa2ul.yaml > index 1d48ac712b23..6eb9acd564c2 100644 > --- a/Documentation/devicetree/bindings/crypto/ti,sa2ul.yaml > +++ b/Documentation/devicetree/bindings/crypto/ti,sa2ul.yaml > @@ -14,6 +14,7 @@ properties: > enum: > - ti,j721e-sa2ul > - ti,am654-sa2ul > + - ti,am64-sa2ul > > reg: > maxItems: 1 > @@ -45,19 +46,44 @@ properties: > description: > Address translation for the possible RNG child node for SA2UL > > + clocks: > + items: > + - description: Clock used by PKA > + - description: Main Input Clock > + - description: Clock used by rng > + > + clock-names: > + items: > + - const: pka_in_clk > + - const: x1_clk > + - const: x2_clk > + > patternProperties: > "^rng@[a-f0-9]+$": > type: object > description: > Child RNG node for SA2UL > > -required: > - - compatible > - - reg > - - power-domains > - - dmas > - - dma-names > - - dma-coherent > +if: > + properties: > + compatible: > + const: ti,am64-sa2ul > +then: > + required: > + - compatible > + - reg > + - power-domains > + - dmas > + - dma-names > + > +else: > + required: > + - compatible > + - reg > + - power-domains > + - dmas > + - dma-names > + - dma-coherent The only difference is 'dma-coherent'. You can simplify the if/then to just that. ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v1 1/3] dt-bindings: crypto: ti,sa2ul: Add new compatible for AM64 2021-03-16 22:05 ` Rob Herring @ 2021-03-17 4:16 ` Vaibhav Gupta 2021-04-13 9:15 ` [PATCH v2 0/3] Update dt-bindings and sa2ul driver for AM64x SoCs Vaibhav Gupta 1 sibling, 0 replies; 12+ messages in thread From: Vaibhav Gupta @ 2021-03-17 4:16 UTC (permalink / raw) To: Rob Herring Cc: Herbert Xu, David S. Miller, Kishon Vijay Abraham, Sekhar Nori, Lokesh Vutla, Praneeth Bajjuri, Gowtham Tammana, linux-crypto, devicetree, linux-kernel, Peter Ujfalusi, Vaibhav Gupta On Tue, Mar 16, 2021 at 04:05:58PM -0600, Rob Herring wrote: > On Tue, Mar 09, 2021 at 01:50:03AM +0530, Vaibhav Gupta wrote: > > From: Peter Ujfalusi <peter.ujfalusi@ti.com> > > > > Add the AM64 version of sa2ul to the compatible list. > > > > [v_gupta@ti.com: Conditional dma-coherent requirement, clocks] > > Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> > > Signed-off-by: Vaibhav Gupta <v_gupta@ti.com> > > --- > > .../devicetree/bindings/crypto/ti,sa2ul.yaml | 40 +++++++++++++++---- > > 1 file changed, 33 insertions(+), 7 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/crypto/ti,sa2ul.yaml b/Documentation/devicetree/bindings/crypto/ti,sa2ul.yaml > > index 1d48ac712b23..6eb9acd564c2 100644 > > --- a/Documentation/devicetree/bindings/crypto/ti,sa2ul.yaml > > +++ b/Documentation/devicetree/bindings/crypto/ti,sa2ul.yaml > > @@ -14,6 +14,7 @@ properties: > > enum: > > - ti,j721e-sa2ul > > - ti,am654-sa2ul > > + - ti,am64-sa2ul > > > > reg: > > maxItems: 1 > > @@ -45,19 +46,44 @@ properties: > > description: > > Address translation for the possible RNG child node for SA2UL > > > > + clocks: > > + items: > > + - description: Clock used by PKA > > + - description: Main Input Clock > > + - description: Clock used by rng > > + > > + clock-names: > > + items: > > + - const: pka_in_clk > > + - const: x1_clk > > + - const: x2_clk > > + > > patternProperties: > > "^rng@[a-f0-9]+$": > > type: object > > description: > > Child RNG node for SA2UL > > > > -required: > > - - compatible > > - - reg > > - - power-domains > > - - dmas > > - - dma-names > > - - dma-coherent > > +if: > > + properties: > > + compatible: > > + const: ti,am64-sa2ul > > +then: > > + required: > > + - compatible > > + - reg > > + - power-domains > > + - dmas > > + - dma-names > > + > > +else: > > + required: > > + - compatible > > + - reg > > + - power-domains > > + - dmas > > + - dma-names > > + - dma-coherent > > The only difference is 'dma-coherent'. You can simplify the if/then to > just that. Hello Rob, I agree with your point. But with that case we will have to modify/append the 'required' list. Something like: if !(properties.compatible == 'ti,am64-sa2ul') required += dma-coherent I even tried to use anchors but that didn't help. I didn't find it even in examples. Any hint how to achieve that? Thanks, Vaibhav ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 0/3] Update dt-bindings and sa2ul driver for AM64x SoCs 2021-03-16 22:05 ` Rob Herring 2021-03-17 4:16 ` Vaibhav Gupta @ 2021-04-13 9:15 ` Vaibhav Gupta 2021-04-13 9:15 ` [PATCH v2 1/3] dt-bindings: crypto: ti,sa2ul: Add new compatible for AM64 Vaibhav Gupta ` (3 more replies) 1 sibling, 4 replies; 12+ messages in thread From: Vaibhav Gupta @ 2021-04-13 9:15 UTC (permalink / raw) To: Herbert Xu, David S. Miller, Rob Herring Cc: vaibhavgupta40, Kishon Vijay Abraham, Sekhar Nori, Lokesh Vutla, Praneeth Bajjuri, Gowtham Tammana, linux-crypto, devicetree, linux-kernel From: Vaibhav Gupta <v_gupta@ti.com> This patch series aims to modify necessary files before an entry for sa2ul can be made in the respective am64 device tree. v2? - Simplify the dt-binding changes. Peter Ujfalusi (3): dt-bindings: crypto: ti,sa2ul: Add new compatible for AM64 crypto: sa2ul: Support for per channel coherency crypto: sa2ul: Add support for AM64 .../devicetree/bindings/crypto/ti,sa2ul.yaml | 24 +++- drivers/crypto/sa2ul.c | 133 ++++++++++++------ drivers/crypto/sa2ul.h | 4 + 3 files changed, 120 insertions(+), 41 deletions(-) -- 2.31.0 ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 1/3] dt-bindings: crypto: ti,sa2ul: Add new compatible for AM64 2021-04-13 9:15 ` [PATCH v2 0/3] Update dt-bindings and sa2ul driver for AM64x SoCs Vaibhav Gupta @ 2021-04-13 9:15 ` Vaibhav Gupta 2021-04-13 16:30 ` Rob Herring 2021-04-13 9:15 ` [PATCH v2 2/3] crypto: sa2ul: Support for per channel coherency Vaibhav Gupta ` (2 subsequent siblings) 3 siblings, 1 reply; 12+ messages in thread From: Vaibhav Gupta @ 2021-04-13 9:15 UTC (permalink / raw) To: Herbert Xu, David S. Miller, Rob Herring Cc: vaibhavgupta40, Kishon Vijay Abraham, Sekhar Nori, Lokesh Vutla, Praneeth Bajjuri, Gowtham Tammana, linux-crypto, devicetree, linux-kernel From: Peter Ujfalusi <peter.ujfalusi@ti.com> Add the AM64 version of sa2ul to the compatible list. [v_gupta@ti.com: Conditional dma-coherent requirement, clocks] Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vaibhav Gupta <v_gupta@ti.com> --- .../devicetree/bindings/crypto/ti,sa2ul.yaml | 24 ++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/crypto/ti,sa2ul.yaml b/Documentation/devicetree/bindings/crypto/ti,sa2ul.yaml index 1d48ac712b23..a410d2cedde6 100644 --- a/Documentation/devicetree/bindings/crypto/ti,sa2ul.yaml +++ b/Documentation/devicetree/bindings/crypto/ti,sa2ul.yaml @@ -14,6 +14,7 @@ properties: enum: - ti,j721e-sa2ul - ti,am654-sa2ul + - ti,am64-sa2ul reg: maxItems: 1 @@ -45,6 +46,18 @@ properties: description: Address translation for the possible RNG child node for SA2UL + clocks: + items: + - description: Clock used by PKA + - description: Main Input Clock + - description: Clock used by rng + + clock-names: + items: + - const: pka_in_clk + - const: x1_clk + - const: x2_clk + patternProperties: "^rng@[a-f0-9]+$": type: object @@ -57,7 +70,16 @@ required: - power-domains - dmas - dma-names - - dma-coherent + +if: + properties: + compatible: + enum: + - ti,j721e-sa2ul + - ti,am654-sa2ul +then: + required: + - dma-coherent additionalProperties: false -- 2.31.0 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: crypto: ti,sa2ul: Add new compatible for AM64 2021-04-13 9:15 ` [PATCH v2 1/3] dt-bindings: crypto: ti,sa2ul: Add new compatible for AM64 Vaibhav Gupta @ 2021-04-13 16:30 ` Rob Herring 0 siblings, 0 replies; 12+ messages in thread From: Rob Herring @ 2021-04-13 16:30 UTC (permalink / raw) To: Vaibhav Gupta Cc: devicetree, Rob Herring, Herbert Xu, Kishon Vijay Abraham, Gowtham Tammana, linux-crypto, Praneeth Bajjuri, David S. Miller, Lokesh Vutla, linux-kernel, Sekhar Nori On Tue, 13 Apr 2021 14:45:57 +0530, Vaibhav Gupta wrote: > From: Peter Ujfalusi <peter.ujfalusi@ti.com> > > Add the AM64 version of sa2ul to the compatible list. > > [v_gupta@ti.com: Conditional dma-coherent requirement, clocks] > Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> > Signed-off-by: Vaibhav Gupta <v_gupta@ti.com> > --- > .../devicetree/bindings/crypto/ti,sa2ul.yaml | 24 ++++++++++++++++++- > 1 file changed, 23 insertions(+), 1 deletion(-) > Reviewed-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 2/3] crypto: sa2ul: Support for per channel coherency 2021-04-13 9:15 ` [PATCH v2 0/3] Update dt-bindings and sa2ul driver for AM64x SoCs Vaibhav Gupta 2021-04-13 9:15 ` [PATCH v2 1/3] dt-bindings: crypto: ti,sa2ul: Add new compatible for AM64 Vaibhav Gupta @ 2021-04-13 9:15 ` Vaibhav Gupta 2021-04-13 9:15 ` [PATCH v2 3/3] crypto: sa2ul: Add support for AM64 Vaibhav Gupta 2021-04-22 7:45 ` [PATCH v2 0/3] Update dt-bindings and sa2ul driver for AM64x SoCs Herbert Xu 3 siblings, 0 replies; 12+ messages in thread From: Vaibhav Gupta @ 2021-04-13 9:15 UTC (permalink / raw) To: Herbert Xu, David S. Miller, Rob Herring Cc: vaibhavgupta40, Kishon Vijay Abraham, Sekhar Nori, Lokesh Vutla, Praneeth Bajjuri, Gowtham Tammana, linux-crypto, devicetree, linux-kernel From: Peter Ujfalusi <peter.ujfalusi@ti.com> On AM64 the DMA channel for sa2ul can be configured to be coherent or non coherent via DT binding. Use the dmaengine_get_device_for_dma_api() to get the device pointer which should be used for with the dma_api to use matching dma_ops for the channel coherency/non coherency. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vaibhav Gupta <v_gupta@ti.com> --- drivers/crypto/sa2ul.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/crypto/sa2ul.c b/drivers/crypto/sa2ul.c index f300b0a5958a..6107bfea862d 100644 --- a/drivers/crypto/sa2ul.c +++ b/drivers/crypto/sa2ul.c @@ -1106,7 +1106,7 @@ static int sa_run(struct sa_req *req) else dma_rx = pdata->dma_rx1; - ddev = dma_rx->device->dev; + ddev = dmaengine_get_dma_device(pdata->dma_tx); rxd->ddev = ddev; memcpy(cmdl, sa_ctx->cmdl, sa_ctx->cmdl_size); -- 2.31.0 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v2 3/3] crypto: sa2ul: Add support for AM64 2021-04-13 9:15 ` [PATCH v2 0/3] Update dt-bindings and sa2ul driver for AM64x SoCs Vaibhav Gupta 2021-04-13 9:15 ` [PATCH v2 1/3] dt-bindings: crypto: ti,sa2ul: Add new compatible for AM64 Vaibhav Gupta 2021-04-13 9:15 ` [PATCH v2 2/3] crypto: sa2ul: Support for per channel coherency Vaibhav Gupta @ 2021-04-13 9:15 ` Vaibhav Gupta 2021-04-22 7:45 ` [PATCH v2 0/3] Update dt-bindings and sa2ul driver for AM64x SoCs Herbert Xu 3 siblings, 0 replies; 12+ messages in thread From: Vaibhav Gupta @ 2021-04-13 9:15 UTC (permalink / raw) To: Herbert Xu, David S. Miller, Rob Herring Cc: vaibhavgupta40, Kishon Vijay Abraham, Sekhar Nori, Lokesh Vutla, Praneeth Bajjuri, Gowtham Tammana, linux-crypto, devicetree, linux-kernel From: Peter Ujfalusi <peter.ujfalusi@ti.com> The sa2ul module in am64 have limited support for algorithms, and the priv and priv_id used on the platform is different compared to AM654 or j721e. Use match data to get the SoC specific information and use it throughout the driver. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vaibhav Gupta <v_gupta@ti.com> --- drivers/crypto/sa2ul.c | 131 +++++++++++++++++++++++++++++------------ drivers/crypto/sa2ul.h | 4 ++ 2 files changed, 96 insertions(+), 39 deletions(-) diff --git a/drivers/crypto/sa2ul.c b/drivers/crypto/sa2ul.c index 6107bfea862d..8a17ab8af444 100644 --- a/drivers/crypto/sa2ul.c +++ b/drivers/crypto/sa2ul.c @@ -69,8 +69,24 @@ /* Max Authentication tag size */ #define SA_MAX_AUTH_TAG_SZ 64 -#define PRIV_ID 0x1 -#define PRIV 0x1 +enum sa_algo_id { + SA_ALG_CBC_AES = 0, + SA_ALG_EBC_AES, + SA_ALG_CBC_DES3, + SA_ALG_ECB_DES3, + SA_ALG_SHA1, + SA_ALG_SHA256, + SA_ALG_SHA512, + SA_ALG_AUTHENC_SHA1_AES, + SA_ALG_AUTHENC_SHA256_AES, +}; + +struct sa_match_data { + u8 priv; + u8 priv_id; + u32 supported_algos; + bool skip_engine_control; +}; static struct device *sa_k3_dev; @@ -696,8 +712,9 @@ static void sa_dump_sc(u8 *buf, dma_addr_t dma_addr) } static -int sa_init_sc(struct sa_ctx_info *ctx, const u8 *enc_key, - u16 enc_key_sz, const u8 *auth_key, u16 auth_key_sz, +int sa_init_sc(struct sa_ctx_info *ctx, const struct sa_match_data *match_data, + const u8 *enc_key, u16 enc_key_sz, + const u8 *auth_key, u16 auth_key_sz, struct algo_data *ad, u8 enc, u32 *swinfo) { int enc_sc_offset = 0; @@ -732,8 +749,8 @@ int sa_init_sc(struct sa_ctx_info *ctx, const u8 *enc_key, sc_buf[SA_CTX_SCCTL_OWNER_OFFSET] = 0; memcpy(&sc_buf[2], &sc_id, 2); sc_buf[4] = 0x0; - sc_buf[5] = PRIV_ID; - sc_buf[6] = PRIV; + sc_buf[5] = match_data->priv_id; + sc_buf[6] = match_data->priv; sc_buf[7] = 0x0; /* Prepare context for encryption engine */ @@ -892,8 +909,8 @@ static int sa_cipher_setkey(struct crypto_skcipher *tfm, const u8 *key, return ret; /* Setup Encryption Security Context & Command label template */ - if (sa_init_sc(&ctx->enc, key, keylen, NULL, 0, ad, 1, - &ctx->enc.epib[1])) + if (sa_init_sc(&ctx->enc, ctx->dev_data->match_data, key, keylen, NULL, 0, + ad, 1, &ctx->enc.epib[1])) goto badkey; cmdl_len = sa_format_cmdl_gen(&cfg, @@ -905,8 +922,8 @@ static int sa_cipher_setkey(struct crypto_skcipher *tfm, const u8 *key, ctx->enc.cmdl_size = cmdl_len; /* Setup Decryption Security Context & Command label template */ - if (sa_init_sc(&ctx->dec, key, keylen, NULL, 0, ad, 0, - &ctx->dec.epib[1])) + if (sa_init_sc(&ctx->dec, ctx->dev_data->match_data, key, keylen, NULL, 0, + ad, 0, &ctx->dec.epib[1])) goto badkey; cfg.enc_eng_id = ad->enc_eng.eng_id; @@ -1446,9 +1463,10 @@ static int sa_sha_setup(struct sa_tfm_ctx *ctx, struct algo_data *ad) cfg.akey = NULL; cfg.akey_len = 0; + ctx->dev_data = dev_get_drvdata(sa_k3_dev); /* Setup Encryption Security Context & Command label template */ - if (sa_init_sc(&ctx->enc, NULL, 0, NULL, 0, ad, 0, - &ctx->enc.epib[1])) + if (sa_init_sc(&ctx->enc, ctx->dev_data->match_data, NULL, 0, NULL, 0, + ad, 0, &ctx->enc.epib[1])) goto badkey; cmdl_len = sa_format_cmdl_gen(&cfg, @@ -1716,6 +1734,7 @@ static int sa_cra_init_aead(struct crypto_aead *tfm, const char *hash, int ret; memzero_explicit(ctx, sizeof(*ctx)); + ctx->dev_data = data; ctx->shash = crypto_alloc_shash(hash, 0, CRYPTO_ALG_NEED_FALLBACK); if (IS_ERR(ctx->shash)) { @@ -1817,8 +1836,8 @@ static int sa_aead_setkey(struct crypto_aead *authenc, cfg.akey_len = keys.authkeylen; /* Setup Encryption Security Context & Command label template */ - if (sa_init_sc(&ctx->enc, keys.enckey, keys.enckeylen, - keys.authkey, keys.authkeylen, + if (sa_init_sc(&ctx->enc, ctx->dev_data->match_data, keys.enckey, + keys.enckeylen, keys.authkey, keys.authkeylen, ad, 1, &ctx->enc.epib[1])) return -EINVAL; @@ -1831,8 +1850,8 @@ static int sa_aead_setkey(struct crypto_aead *authenc, ctx->enc.cmdl_size = cmdl_len; /* Setup Decryption Security Context & Command label template */ - if (sa_init_sc(&ctx->dec, keys.enckey, keys.enckeylen, - keys.authkey, keys.authkeylen, + if (sa_init_sc(&ctx->dec, ctx->dev_data->match_data, keys.enckey, + keys.enckeylen, keys.authkey, keys.authkeylen, ad, 0, &ctx->dec.epib[1])) return -EINVAL; @@ -1950,7 +1969,7 @@ static int sa_aead_decrypt(struct aead_request *req) } static struct sa_alg_tmpl sa_algs[] = { - { + [SA_ALG_CBC_AES] = { .type = CRYPTO_ALG_TYPE_SKCIPHER, .alg.skcipher = { .base.cra_name = "cbc(aes)", @@ -1973,7 +1992,7 @@ static struct sa_alg_tmpl sa_algs[] = { .decrypt = sa_decrypt, } }, - { + [SA_ALG_EBC_AES] = { .type = CRYPTO_ALG_TYPE_SKCIPHER, .alg.skcipher = { .base.cra_name = "ecb(aes)", @@ -1995,7 +2014,7 @@ static struct sa_alg_tmpl sa_algs[] = { .decrypt = sa_decrypt, } }, - { + [SA_ALG_CBC_DES3] = { .type = CRYPTO_ALG_TYPE_SKCIPHER, .alg.skcipher = { .base.cra_name = "cbc(des3_ede)", @@ -2018,7 +2037,7 @@ static struct sa_alg_tmpl sa_algs[] = { .decrypt = sa_decrypt, } }, - { + [SA_ALG_ECB_DES3] = { .type = CRYPTO_ALG_TYPE_SKCIPHER, .alg.skcipher = { .base.cra_name = "ecb(des3_ede)", @@ -2040,7 +2059,7 @@ static struct sa_alg_tmpl sa_algs[] = { .decrypt = sa_decrypt, } }, - { + [SA_ALG_SHA1] = { .type = CRYPTO_ALG_TYPE_AHASH, .alg.ahash = { .halg.base = { @@ -2069,7 +2088,7 @@ static struct sa_alg_tmpl sa_algs[] = { .import = sa_sha_import, }, }, - { + [SA_ALG_SHA256] = { .type = CRYPTO_ALG_TYPE_AHASH, .alg.ahash = { .halg.base = { @@ -2098,7 +2117,7 @@ static struct sa_alg_tmpl sa_algs[] = { .import = sa_sha_import, }, }, - { + [SA_ALG_SHA512] = { .type = CRYPTO_ALG_TYPE_AHASH, .alg.ahash = { .halg.base = { @@ -2127,7 +2146,7 @@ static struct sa_alg_tmpl sa_algs[] = { .import = sa_sha_import, }, }, - { + [SA_ALG_AUTHENC_SHA1_AES] = { .type = CRYPTO_ALG_TYPE_AEAD, .alg.aead = { .base = { @@ -2154,7 +2173,7 @@ static struct sa_alg_tmpl sa_algs[] = { .decrypt = sa_aead_decrypt, }, }, - { + [SA_ALG_AUTHENC_SHA256_AES] = { .type = CRYPTO_ALG_TYPE_AEAD, .alg.aead = { .base = { @@ -2185,13 +2204,19 @@ static struct sa_alg_tmpl sa_algs[] = { }; /* Register the algorithms in crypto framework */ -static void sa_register_algos(const struct device *dev) +static void sa_register_algos(struct sa_crypto_data *dev_data) { + const struct sa_match_data *match_data = dev_data->match_data; + struct device *dev = dev_data->dev; char *alg_name; u32 type; int i, err; for (i = 0; i < ARRAY_SIZE(sa_algs); i++) { + /* Skip unsupported algos */ + if (!(match_data->supported_algos & BIT(i))) + continue; + type = sa_algs[i].type; if (type == CRYPTO_ALG_TYPE_SKCIPHER) { alg_name = sa_algs[i].alg.skcipher.base.cra_name; @@ -2329,14 +2354,39 @@ static int sa_link_child(struct device *dev, void *data) return 0; } +static struct sa_match_data am654_match_data = { + .priv = 1, + .priv_id = 1, + .supported_algos = GENMASK(SA_ALG_AUTHENC_SHA256_AES, 0), +}; + +static struct sa_match_data am64_match_data = { + .priv = 0, + .priv_id = 0, + .supported_algos = BIT(SA_ALG_CBC_AES) | + BIT(SA_ALG_EBC_AES) | + BIT(SA_ALG_SHA256) | + BIT(SA_ALG_SHA512) | + BIT(SA_ALG_AUTHENC_SHA256_AES), + .skip_engine_control = true, +}; + +static const struct of_device_id of_match[] = { + { .compatible = "ti,j721e-sa2ul", .data = &am654_match_data, }, + { .compatible = "ti,am654-sa2ul", .data = &am654_match_data, }, + { .compatible = "ti,am64-sa2ul", .data = &am64_match_data, }, + {}, +}; +MODULE_DEVICE_TABLE(of, of_match); + static int sa_ul_probe(struct platform_device *pdev) { + const struct of_device_id *match; struct device *dev = &pdev->dev; struct device_node *node = dev->of_node; struct resource *res; static void __iomem *saul_base; struct sa_crypto_data *dev_data; - u32 val; int ret; dev_data = devm_kzalloc(dev, sizeof(*dev_data), GFP_KERNEL); @@ -2362,18 +2412,28 @@ static int sa_ul_probe(struct platform_device *pdev) if (ret) goto disable_pm_runtime; + match = of_match_node(of_match, dev->of_node); + if (!match) { + dev_err(dev, "No compatible match found\n"); + return -ENODEV; + } + dev_data->match_data = match->data; + spin_lock_init(&dev_data->scid_lock); res = platform_get_resource(pdev, IORESOURCE_MEM, 0); saul_base = devm_ioremap_resource(dev, res); dev_data->base = saul_base; - val = SA_EEC_ENCSS_EN | SA_EEC_AUTHSS_EN | SA_EEC_CTXCACH_EN | - SA_EEC_CPPI_PORT_IN_EN | SA_EEC_CPPI_PORT_OUT_EN | - SA_EEC_TRNG_EN; - writel_relaxed(val, saul_base + SA_ENGINE_ENABLE_CONTROL); + if (!dev_data->match_data->skip_engine_control) { + u32 val = SA_EEC_ENCSS_EN | SA_EEC_AUTHSS_EN | SA_EEC_CTXCACH_EN | + SA_EEC_CPPI_PORT_IN_EN | SA_EEC_CPPI_PORT_OUT_EN | + SA_EEC_TRNG_EN; - sa_register_algos(dev); + writel_relaxed(val, saul_base + SA_ENGINE_ENABLE_CONTROL); + } + + sa_register_algos(dev_data); ret = of_platform_populate(node, NULL, NULL, &pdev->dev); if (ret) @@ -2419,13 +2479,6 @@ static int sa_ul_remove(struct platform_device *pdev) return 0; } -static const struct of_device_id of_match[] = { - {.compatible = "ti,j721e-sa2ul",}, - {.compatible = "ti,am654-sa2ul",}, - {}, -}; -MODULE_DEVICE_TABLE(of, of_match); - static struct platform_driver sa_ul_driver = { .probe = sa_ul_probe, .remove = sa_ul_remove, diff --git a/drivers/crypto/sa2ul.h b/drivers/crypto/sa2ul.h index f597ddecde34..ed66d1f111db 100644 --- a/drivers/crypto/sa2ul.h +++ b/drivers/crypto/sa2ul.h @@ -171,9 +171,12 @@ struct sa_tfm_ctx; #define SA_UNSAFE_DATA_SZ_MIN 240 #define SA_UNSAFE_DATA_SZ_MAX 256 +struct sa_match_data; + /** * struct sa_crypto_data - Crypto driver instance data * @base: Base address of the register space + * @soc_data: Pointer to SoC specific data * @pdev: Platform device pointer * @sc_pool: security context pool * @dev: Device pointer @@ -189,6 +192,7 @@ struct sa_tfm_ctx; */ struct sa_crypto_data { void __iomem *base; + const struct sa_match_data *match_data; struct platform_device *pdev; struct dma_pool *sc_pool; struct device *dev; -- 2.31.0 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v2 0/3] Update dt-bindings and sa2ul driver for AM64x SoCs 2021-04-13 9:15 ` [PATCH v2 0/3] Update dt-bindings and sa2ul driver for AM64x SoCs Vaibhav Gupta ` (2 preceding siblings ...) 2021-04-13 9:15 ` [PATCH v2 3/3] crypto: sa2ul: Add support for AM64 Vaibhav Gupta @ 2021-04-22 7:45 ` Herbert Xu 3 siblings, 0 replies; 12+ messages in thread From: Herbert Xu @ 2021-04-22 7:45 UTC (permalink / raw) To: Vaibhav Gupta Cc: David S. Miller, Rob Herring, Kishon Vijay Abraham, Sekhar Nori, Lokesh Vutla, Praneeth Bajjuri, Gowtham Tammana, linux-crypto, devicetree, linux-kernel On Tue, Apr 13, 2021 at 02:45:56PM +0530, Vaibhav Gupta wrote: > From: Vaibhav Gupta <v_gupta@ti.com> > > This patch series aims to modify necessary files before an entry for sa2ul > can be made in the respective am64 device tree. > > v2? > - Simplify the dt-binding changes. > > Peter Ujfalusi (3): > dt-bindings: crypto: ti,sa2ul: Add new compatible for AM64 > crypto: sa2ul: Support for per channel coherency > crypto: sa2ul: Add support for AM64 > > .../devicetree/bindings/crypto/ti,sa2ul.yaml | 24 +++- > drivers/crypto/sa2ul.c | 133 ++++++++++++------ > drivers/crypto/sa2ul.h | 4 + > 3 files changed, 120 insertions(+), 41 deletions(-) All applied. Thanks. -- Email: Herbert Xu <herbert@gondor.apana.org.au> Home Page: http://gondor.apana.org.au/~herbert/ PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v1 2/3] crypto: sa2ul: Support for per channel coherency 2021-03-08 20:20 [PATCH v1 0/3] Update dt-bindings and sa2ul driver for AM64x SoCs Vaibhav Gupta 2021-03-08 20:20 ` [PATCH v1 1/3] dt-bindings: crypto: ti,sa2ul: Add new compatible for AM64 Vaibhav Gupta @ 2021-03-08 20:20 ` Vaibhav Gupta 2021-03-08 20:20 ` [PATCH v1 3/3] crypto: sa2ul: Add support for AM64 Vaibhav Gupta 2 siblings, 0 replies; 12+ messages in thread From: Vaibhav Gupta @ 2021-03-08 20:20 UTC (permalink / raw) To: Herbert Xu, David S. Miller, Rob Herring Cc: Kishon Vijay Abraham, Sekhar Nori, Lokesh Vutla, Praneeth Bajjuri, Gowtham Tammana, linux-crypto, devicetree, linux-kernel, Peter Ujfalusi, Vaibhav Gupta From: Peter Ujfalusi <peter.ujfalusi@ti.com> On AM64 the DMA channel for sa2ul can be configured to be coherent or non coherent via DT binding. Use the dmaengine_get_device_for_dma_api() to get the device pointer which should be used for with the dma_api to use matching dma_ops for the channel coherency/non coherency. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vaibhav Gupta <v_gupta@ti.com> --- drivers/crypto/sa2ul.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/crypto/sa2ul.c b/drivers/crypto/sa2ul.c index f300b0a5958a..6107bfea862d 100644 --- a/drivers/crypto/sa2ul.c +++ b/drivers/crypto/sa2ul.c @@ -1106,7 +1106,7 @@ static int sa_run(struct sa_req *req) else dma_rx = pdata->dma_rx1; - ddev = dma_rx->device->dev; + ddev = dmaengine_get_dma_device(pdata->dma_tx); rxd->ddev = ddev; memcpy(cmdl, sa_ctx->cmdl, sa_ctx->cmdl_size); -- 2.30.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v1 3/3] crypto: sa2ul: Add support for AM64 2021-03-08 20:20 [PATCH v1 0/3] Update dt-bindings and sa2ul driver for AM64x SoCs Vaibhav Gupta 2021-03-08 20:20 ` [PATCH v1 1/3] dt-bindings: crypto: ti,sa2ul: Add new compatible for AM64 Vaibhav Gupta 2021-03-08 20:20 ` [PATCH v1 2/3] crypto: sa2ul: Support for per channel coherency Vaibhav Gupta @ 2021-03-08 20:20 ` Vaibhav Gupta 2 siblings, 0 replies; 12+ messages in thread From: Vaibhav Gupta @ 2021-03-08 20:20 UTC (permalink / raw) To: Herbert Xu, David S. Miller, Rob Herring Cc: Kishon Vijay Abraham, Sekhar Nori, Lokesh Vutla, Praneeth Bajjuri, Gowtham Tammana, linux-crypto, devicetree, linux-kernel, Peter Ujfalusi, Vaibhav Gupta From: Peter Ujfalusi <peter.ujfalusi@ti.com> The sa2ul module in am64 have limited support for algorithms, and the priv and priv_id used on the platform is different compared to AM654 or j721e. Use match data to get the SoC specific information and use it throughout the driver. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vaibhav Gupta <v_gupta@ti.com> --- drivers/crypto/sa2ul.c | 131 +++++++++++++++++++++++++++++------------ drivers/crypto/sa2ul.h | 4 ++ 2 files changed, 96 insertions(+), 39 deletions(-) diff --git a/drivers/crypto/sa2ul.c b/drivers/crypto/sa2ul.c index 6107bfea862d..8a17ab8af444 100644 --- a/drivers/crypto/sa2ul.c +++ b/drivers/crypto/sa2ul.c @@ -69,8 +69,24 @@ /* Max Authentication tag size */ #define SA_MAX_AUTH_TAG_SZ 64 -#define PRIV_ID 0x1 -#define PRIV 0x1 +enum sa_algo_id { + SA_ALG_CBC_AES = 0, + SA_ALG_EBC_AES, + SA_ALG_CBC_DES3, + SA_ALG_ECB_DES3, + SA_ALG_SHA1, + SA_ALG_SHA256, + SA_ALG_SHA512, + SA_ALG_AUTHENC_SHA1_AES, + SA_ALG_AUTHENC_SHA256_AES, +}; + +struct sa_match_data { + u8 priv; + u8 priv_id; + u32 supported_algos; + bool skip_engine_control; +}; static struct device *sa_k3_dev; @@ -696,8 +712,9 @@ static void sa_dump_sc(u8 *buf, dma_addr_t dma_addr) } static -int sa_init_sc(struct sa_ctx_info *ctx, const u8 *enc_key, - u16 enc_key_sz, const u8 *auth_key, u16 auth_key_sz, +int sa_init_sc(struct sa_ctx_info *ctx, const struct sa_match_data *match_data, + const u8 *enc_key, u16 enc_key_sz, + const u8 *auth_key, u16 auth_key_sz, struct algo_data *ad, u8 enc, u32 *swinfo) { int enc_sc_offset = 0; @@ -732,8 +749,8 @@ int sa_init_sc(struct sa_ctx_info *ctx, const u8 *enc_key, sc_buf[SA_CTX_SCCTL_OWNER_OFFSET] = 0; memcpy(&sc_buf[2], &sc_id, 2); sc_buf[4] = 0x0; - sc_buf[5] = PRIV_ID; - sc_buf[6] = PRIV; + sc_buf[5] = match_data->priv_id; + sc_buf[6] = match_data->priv; sc_buf[7] = 0x0; /* Prepare context for encryption engine */ @@ -892,8 +909,8 @@ static int sa_cipher_setkey(struct crypto_skcipher *tfm, const u8 *key, return ret; /* Setup Encryption Security Context & Command label template */ - if (sa_init_sc(&ctx->enc, key, keylen, NULL, 0, ad, 1, - &ctx->enc.epib[1])) + if (sa_init_sc(&ctx->enc, ctx->dev_data->match_data, key, keylen, NULL, 0, + ad, 1, &ctx->enc.epib[1])) goto badkey; cmdl_len = sa_format_cmdl_gen(&cfg, @@ -905,8 +922,8 @@ static int sa_cipher_setkey(struct crypto_skcipher *tfm, const u8 *key, ctx->enc.cmdl_size = cmdl_len; /* Setup Decryption Security Context & Command label template */ - if (sa_init_sc(&ctx->dec, key, keylen, NULL, 0, ad, 0, - &ctx->dec.epib[1])) + if (sa_init_sc(&ctx->dec, ctx->dev_data->match_data, key, keylen, NULL, 0, + ad, 0, &ctx->dec.epib[1])) goto badkey; cfg.enc_eng_id = ad->enc_eng.eng_id; @@ -1446,9 +1463,10 @@ static int sa_sha_setup(struct sa_tfm_ctx *ctx, struct algo_data *ad) cfg.akey = NULL; cfg.akey_len = 0; + ctx->dev_data = dev_get_drvdata(sa_k3_dev); /* Setup Encryption Security Context & Command label template */ - if (sa_init_sc(&ctx->enc, NULL, 0, NULL, 0, ad, 0, - &ctx->enc.epib[1])) + if (sa_init_sc(&ctx->enc, ctx->dev_data->match_data, NULL, 0, NULL, 0, + ad, 0, &ctx->enc.epib[1])) goto badkey; cmdl_len = sa_format_cmdl_gen(&cfg, @@ -1716,6 +1734,7 @@ static int sa_cra_init_aead(struct crypto_aead *tfm, const char *hash, int ret; memzero_explicit(ctx, sizeof(*ctx)); + ctx->dev_data = data; ctx->shash = crypto_alloc_shash(hash, 0, CRYPTO_ALG_NEED_FALLBACK); if (IS_ERR(ctx->shash)) { @@ -1817,8 +1836,8 @@ static int sa_aead_setkey(struct crypto_aead *authenc, cfg.akey_len = keys.authkeylen; /* Setup Encryption Security Context & Command label template */ - if (sa_init_sc(&ctx->enc, keys.enckey, keys.enckeylen, - keys.authkey, keys.authkeylen, + if (sa_init_sc(&ctx->enc, ctx->dev_data->match_data, keys.enckey, + keys.enckeylen, keys.authkey, keys.authkeylen, ad, 1, &ctx->enc.epib[1])) return -EINVAL; @@ -1831,8 +1850,8 @@ static int sa_aead_setkey(struct crypto_aead *authenc, ctx->enc.cmdl_size = cmdl_len; /* Setup Decryption Security Context & Command label template */ - if (sa_init_sc(&ctx->dec, keys.enckey, keys.enckeylen, - keys.authkey, keys.authkeylen, + if (sa_init_sc(&ctx->dec, ctx->dev_data->match_data, keys.enckey, + keys.enckeylen, keys.authkey, keys.authkeylen, ad, 0, &ctx->dec.epib[1])) return -EINVAL; @@ -1950,7 +1969,7 @@ static int sa_aead_decrypt(struct aead_request *req) } static struct sa_alg_tmpl sa_algs[] = { - { + [SA_ALG_CBC_AES] = { .type = CRYPTO_ALG_TYPE_SKCIPHER, .alg.skcipher = { .base.cra_name = "cbc(aes)", @@ -1973,7 +1992,7 @@ static struct sa_alg_tmpl sa_algs[] = { .decrypt = sa_decrypt, } }, - { + [SA_ALG_EBC_AES] = { .type = CRYPTO_ALG_TYPE_SKCIPHER, .alg.skcipher = { .base.cra_name = "ecb(aes)", @@ -1995,7 +2014,7 @@ static struct sa_alg_tmpl sa_algs[] = { .decrypt = sa_decrypt, } }, - { + [SA_ALG_CBC_DES3] = { .type = CRYPTO_ALG_TYPE_SKCIPHER, .alg.skcipher = { .base.cra_name = "cbc(des3_ede)", @@ -2018,7 +2037,7 @@ static struct sa_alg_tmpl sa_algs[] = { .decrypt = sa_decrypt, } }, - { + [SA_ALG_ECB_DES3] = { .type = CRYPTO_ALG_TYPE_SKCIPHER, .alg.skcipher = { .base.cra_name = "ecb(des3_ede)", @@ -2040,7 +2059,7 @@ static struct sa_alg_tmpl sa_algs[] = { .decrypt = sa_decrypt, } }, - { + [SA_ALG_SHA1] = { .type = CRYPTO_ALG_TYPE_AHASH, .alg.ahash = { .halg.base = { @@ -2069,7 +2088,7 @@ static struct sa_alg_tmpl sa_algs[] = { .import = sa_sha_import, }, }, - { + [SA_ALG_SHA256] = { .type = CRYPTO_ALG_TYPE_AHASH, .alg.ahash = { .halg.base = { @@ -2098,7 +2117,7 @@ static struct sa_alg_tmpl sa_algs[] = { .import = sa_sha_import, }, }, - { + [SA_ALG_SHA512] = { .type = CRYPTO_ALG_TYPE_AHASH, .alg.ahash = { .halg.base = { @@ -2127,7 +2146,7 @@ static struct sa_alg_tmpl sa_algs[] = { .import = sa_sha_import, }, }, - { + [SA_ALG_AUTHENC_SHA1_AES] = { .type = CRYPTO_ALG_TYPE_AEAD, .alg.aead = { .base = { @@ -2154,7 +2173,7 @@ static struct sa_alg_tmpl sa_algs[] = { .decrypt = sa_aead_decrypt, }, }, - { + [SA_ALG_AUTHENC_SHA256_AES] = { .type = CRYPTO_ALG_TYPE_AEAD, .alg.aead = { .base = { @@ -2185,13 +2204,19 @@ static struct sa_alg_tmpl sa_algs[] = { }; /* Register the algorithms in crypto framework */ -static void sa_register_algos(const struct device *dev) +static void sa_register_algos(struct sa_crypto_data *dev_data) { + const struct sa_match_data *match_data = dev_data->match_data; + struct device *dev = dev_data->dev; char *alg_name; u32 type; int i, err; for (i = 0; i < ARRAY_SIZE(sa_algs); i++) { + /* Skip unsupported algos */ + if (!(match_data->supported_algos & BIT(i))) + continue; + type = sa_algs[i].type; if (type == CRYPTO_ALG_TYPE_SKCIPHER) { alg_name = sa_algs[i].alg.skcipher.base.cra_name; @@ -2329,14 +2354,39 @@ static int sa_link_child(struct device *dev, void *data) return 0; } +static struct sa_match_data am654_match_data = { + .priv = 1, + .priv_id = 1, + .supported_algos = GENMASK(SA_ALG_AUTHENC_SHA256_AES, 0), +}; + +static struct sa_match_data am64_match_data = { + .priv = 0, + .priv_id = 0, + .supported_algos = BIT(SA_ALG_CBC_AES) | + BIT(SA_ALG_EBC_AES) | + BIT(SA_ALG_SHA256) | + BIT(SA_ALG_SHA512) | + BIT(SA_ALG_AUTHENC_SHA256_AES), + .skip_engine_control = true, +}; + +static const struct of_device_id of_match[] = { + { .compatible = "ti,j721e-sa2ul", .data = &am654_match_data, }, + { .compatible = "ti,am654-sa2ul", .data = &am654_match_data, }, + { .compatible = "ti,am64-sa2ul", .data = &am64_match_data, }, + {}, +}; +MODULE_DEVICE_TABLE(of, of_match); + static int sa_ul_probe(struct platform_device *pdev) { + const struct of_device_id *match; struct device *dev = &pdev->dev; struct device_node *node = dev->of_node; struct resource *res; static void __iomem *saul_base; struct sa_crypto_data *dev_data; - u32 val; int ret; dev_data = devm_kzalloc(dev, sizeof(*dev_data), GFP_KERNEL); @@ -2362,18 +2412,28 @@ static int sa_ul_probe(struct platform_device *pdev) if (ret) goto disable_pm_runtime; + match = of_match_node(of_match, dev->of_node); + if (!match) { + dev_err(dev, "No compatible match found\n"); + return -ENODEV; + } + dev_data->match_data = match->data; + spin_lock_init(&dev_data->scid_lock); res = platform_get_resource(pdev, IORESOURCE_MEM, 0); saul_base = devm_ioremap_resource(dev, res); dev_data->base = saul_base; - val = SA_EEC_ENCSS_EN | SA_EEC_AUTHSS_EN | SA_EEC_CTXCACH_EN | - SA_EEC_CPPI_PORT_IN_EN | SA_EEC_CPPI_PORT_OUT_EN | - SA_EEC_TRNG_EN; - writel_relaxed(val, saul_base + SA_ENGINE_ENABLE_CONTROL); + if (!dev_data->match_data->skip_engine_control) { + u32 val = SA_EEC_ENCSS_EN | SA_EEC_AUTHSS_EN | SA_EEC_CTXCACH_EN | + SA_EEC_CPPI_PORT_IN_EN | SA_EEC_CPPI_PORT_OUT_EN | + SA_EEC_TRNG_EN; - sa_register_algos(dev); + writel_relaxed(val, saul_base + SA_ENGINE_ENABLE_CONTROL); + } + + sa_register_algos(dev_data); ret = of_platform_populate(node, NULL, NULL, &pdev->dev); if (ret) @@ -2419,13 +2479,6 @@ static int sa_ul_remove(struct platform_device *pdev) return 0; } -static const struct of_device_id of_match[] = { - {.compatible = "ti,j721e-sa2ul",}, - {.compatible = "ti,am654-sa2ul",}, - {}, -}; -MODULE_DEVICE_TABLE(of, of_match); - static struct platform_driver sa_ul_driver = { .probe = sa_ul_probe, .remove = sa_ul_remove, diff --git a/drivers/crypto/sa2ul.h b/drivers/crypto/sa2ul.h index f597ddecde34..ed66d1f111db 100644 --- a/drivers/crypto/sa2ul.h +++ b/drivers/crypto/sa2ul.h @@ -171,9 +171,12 @@ struct sa_tfm_ctx; #define SA_UNSAFE_DATA_SZ_MIN 240 #define SA_UNSAFE_DATA_SZ_MAX 256 +struct sa_match_data; + /** * struct sa_crypto_data - Crypto driver instance data * @base: Base address of the register space + * @soc_data: Pointer to SoC specific data * @pdev: Platform device pointer * @sc_pool: security context pool * @dev: Device pointer @@ -189,6 +192,7 @@ struct sa_tfm_ctx; */ struct sa_crypto_data { void __iomem *base; + const struct sa_match_data *match_data; struct platform_device *pdev; struct dma_pool *sc_pool; struct device *dev; -- 2.30.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
end of thread, other threads:[~2021-04-22 7:45 UTC | newest] Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-03-08 20:20 [PATCH v1 0/3] Update dt-bindings and sa2ul driver for AM64x SoCs Vaibhav Gupta 2021-03-08 20:20 ` [PATCH v1 1/3] dt-bindings: crypto: ti,sa2ul: Add new compatible for AM64 Vaibhav Gupta 2021-03-16 22:05 ` Rob Herring 2021-03-17 4:16 ` Vaibhav Gupta 2021-04-13 9:15 ` [PATCH v2 0/3] Update dt-bindings and sa2ul driver for AM64x SoCs Vaibhav Gupta 2021-04-13 9:15 ` [PATCH v2 1/3] dt-bindings: crypto: ti,sa2ul: Add new compatible for AM64 Vaibhav Gupta 2021-04-13 16:30 ` Rob Herring 2021-04-13 9:15 ` [PATCH v2 2/3] crypto: sa2ul: Support for per channel coherency Vaibhav Gupta 2021-04-13 9:15 ` [PATCH v2 3/3] crypto: sa2ul: Add support for AM64 Vaibhav Gupta 2021-04-22 7:45 ` [PATCH v2 0/3] Update dt-bindings and sa2ul driver for AM64x SoCs Herbert Xu 2021-03-08 20:20 ` [PATCH v1 2/3] crypto: sa2ul: Support for per channel coherency Vaibhav Gupta 2021-03-08 20:20 ` [PATCH v1 3/3] crypto: sa2ul: Add support for AM64 Vaibhav Gupta
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