* [PATCH 1/3] crypto: ixp4xx: convert to platform driver @ 2021-05-10 21:36 Linus Walleij 2021-05-10 21:36 ` [PATCH 2/3] crypto: ixp4xx: Add DT bindings Linus Walleij ` (2 more replies) 0 siblings, 3 replies; 6+ messages in thread From: Linus Walleij @ 2021-05-10 21:36 UTC (permalink / raw) To: linux-crypto, Herbert Xu, David S . Miller Cc: linux-arm-kernel, Imre Kaloz, Krzysztof Halasa, Arnd Bergmann, Linus Walleij From: Arnd Bergmann <arnd@arndb.de> The ixp4xx_crypto driver traditionally registers a bare platform device without attaching it to a driver, and detects the hardware at module init time by reading an SoC specific hardware register. Change this to the conventional method of registering the platform device from the platform code itself when the device is present, turning the module_init/module_exit functions into probe/release driver callbacks. This enables compile-testing as well as potentially having ixp4xx coexist with other ARMv5 platforms in the same kernel in the future. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> --- Herbert, David: I am looking for an ACK to take this into the ARM SoC tree as we want to change more stuff in the machine at the same time that we want to resolve there. --- arch/arm/mach-ixp4xx/common.c | 26 ++++++++++++++++++++++++ drivers/crypto/Kconfig | 3 ++- drivers/crypto/ixp4xx_crypto.c | 37 ++++++++++++---------------------- 3 files changed, 41 insertions(+), 25 deletions(-) diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c index 000f672a94c9..007a44412e24 100644 --- a/arch/arm/mach-ixp4xx/common.c +++ b/arch/arm/mach-ixp4xx/common.c @@ -233,12 +233,38 @@ static struct platform_device *ixp46x_devices[] __initdata = { unsigned long ixp4xx_exp_bus_size; EXPORT_SYMBOL(ixp4xx_exp_bus_size); +static struct platform_device_info ixp_dev_info __initdata = { + .name = "ixp4xx_crypto", + .id = 0, + .dma_mask = DMA_BIT_MASK(32), +}; + +static int __init ixp_crypto_register(void) +{ + struct platform_device *pdev; + + if (!(~(*IXP4XX_EXP_CFG2) & (IXP4XX_FEATURE_HASH | + IXP4XX_FEATURE_AES | IXP4XX_FEATURE_DES))) { + printk(KERN_ERR "ixp_crypto: No HW crypto available\n"); + return -ENODEV; + } + + pdev = platform_device_register_full(&ixp_dev_info); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + + return 0; +} + void __init ixp4xx_sys_init(void) { ixp4xx_exp_bus_size = SZ_16M; platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices)); + if (IS_ENABLED(CONFIG_CRYPTO_DEV_IXP4XX)) + ixp_crypto_register(); + if (cpu_is_ixp46x()) { int region; diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 9a4c275a1335..aa389e741876 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -324,7 +324,8 @@ config CRYPTO_DEV_TALITOS2 config CRYPTO_DEV_IXP4XX tristate "Driver for IXP4xx crypto hardware acceleration" - depends on ARCH_IXP4XX && IXP4XX_QMGR && IXP4XX_NPE + depends on IXP4XX_QMGR && IXP4XX_NPE + depends on ARCH_IXP4XX || COMPILE_TEST select CRYPTO_LIB_DES select CRYPTO_AEAD select CRYPTO_AUTHENC diff --git a/drivers/crypto/ixp4xx_crypto.c b/drivers/crypto/ixp4xx_crypto.c index 0616e369522e..879b93927e2a 100644 --- a/drivers/crypto/ixp4xx_crypto.c +++ b/drivers/crypto/ixp4xx_crypto.c @@ -224,8 +224,6 @@ static dma_addr_t crypt_phys; static int support_aes = 1; -#define DRIVER_NAME "ixp4xx_crypto" - static struct platform_device *pdev; static inline dma_addr_t crypt_virt2phys(struct crypt_ctl *virt) @@ -432,11 +430,6 @@ static int init_ixp_crypto(struct device *dev) int ret = -ENODEV; u32 msg[2] = { 0, 0 }; - if (! ( ~(*IXP4XX_EXP_CFG2) & (IXP4XX_FEATURE_HASH | - IXP4XX_FEATURE_AES | IXP4XX_FEATURE_DES))) { - printk(KERN_ERR "ixp_crypto: No HW crypto available\n"); - return ret; - } npe_c = npe_request(NPE_ID); if (!npe_c) return ret; @@ -1364,26 +1357,17 @@ static struct ixp_aead_alg ixp4xx_aeads[] = { #define IXP_POSTFIX "-ixp4xx" -static const struct platform_device_info ixp_dev_info __initdata = { - .name = DRIVER_NAME, - .id = 0, - .dma_mask = DMA_BIT_MASK(32), -}; - -static int __init ixp_module_init(void) +static int ixp_crypto_probe(struct platform_device *_pdev) { int num = ARRAY_SIZE(ixp4xx_algos); int i, err; - pdev = platform_device_register_full(&ixp_dev_info); - if (IS_ERR(pdev)) - return PTR_ERR(pdev); + pdev = _pdev; err = init_ixp_crypto(&pdev->dev); - if (err) { - platform_device_unregister(pdev); + if (err) return err; - } + for (i=0; i< num; i++) { struct skcipher_alg *cra = &ixp4xx_algos[i].crypto; @@ -1456,7 +1440,7 @@ static int __init ixp_module_init(void) return 0; } -static void __exit ixp_module_exit(void) +static int ixp_crypto_remove(struct platform_device *pdev) { int num = ARRAY_SIZE(ixp4xx_algos); int i; @@ -1471,11 +1455,16 @@ static void __exit ixp_module_exit(void) crypto_unregister_skcipher(&ixp4xx_algos[i].crypto); } release_ixp_crypto(&pdev->dev); - platform_device_unregister(pdev); + + return 0; } -module_init(ixp_module_init); -module_exit(ixp_module_exit); +static struct platform_driver ixp_crypto_driver = { + .probe = ixp_crypto_probe, + .remove = ixp_crypto_remove, + .driver = { .name = "ixp4xx_crypto" }, +}; +module_platform_driver(ixp_crypto_driver); MODULE_LICENSE("GPL"); MODULE_AUTHOR("Christian Hohnstaedt <chohnstaedt@innominate.com>"); -- 2.30.2 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/3] crypto: ixp4xx: Add DT bindings 2021-05-10 21:36 [PATCH 1/3] crypto: ixp4xx: convert to platform driver Linus Walleij @ 2021-05-10 21:36 ` Linus Walleij 2021-05-11 13:40 ` Rob Herring 2021-05-11 16:16 ` Rob Herring 2021-05-10 21:36 ` [PATCH 3/3] crypto: ixp4xx: Add device tree support Linus Walleij 2021-05-11 7:57 ` [PATCH 1/3] crypto: ixp4xx: convert to platform driver Corentin Labbe 2 siblings, 2 replies; 6+ messages in thread From: Linus Walleij @ 2021-05-10 21:36 UTC (permalink / raw) To: linux-crypto, Herbert Xu, David S . Miller Cc: linux-arm-kernel, Imre Kaloz, Krzysztof Halasa, Arnd Bergmann, Linus Walleij, devicetree This adds device tree bindings for the ixp4xx crypto engine. Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org> --- Herbert, David: This can be applied separately once we are happy with the bindings, alternatively it can be merged with the support code into ARM SoC. --- .../bindings/crypto/intel,ixp4xx-crypto.yaml | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml diff --git a/Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml b/Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml new file mode 100644 index 000000000000..28d75f4f9a76 --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2018 Linaro Ltd. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/crypto/intel,ixp4xx-crypto.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Intel IXP4xx cryptographic engine + +maintainers: + - Linus Walleij <linus.walleij@linaro.org> + +description: | + The Intel IXP4xx cryptographic engine makes use of the IXP4xx NPE + (Network Processing Engine). Since it is not a device on its own + it is defined as a subnode of the NPE, if crypto support is + available on the platform. + +properties: + compatible: + const: intel,ixp4xx-crypto + + intel,npe-handle: + $ref: '/schemas/types.yaml#/definitions/phandle-array' + maxItems: 1 + description: phandle to the NPE this ethernet instance is using + and the instance to use in the second cell + + queue-rx: + $ref: '/schemas/types.yaml#/definitions/phandle-array' + maxItems: 1 + description: phandle to the RX queue on the NPE + + queue-txready: + $ref: '/schemas/types.yaml#/definitions/phandle-array' + maxItems: 1 + description: phandle to the TX READY queue on the NPE + +required: + - compatible + - intel,npe-handle + - queue-rx + - queue-txready + +additionalProperties: false + +examples: + - | + npe: npe@c8006000 { + compatible = "intel,ixp4xx-network-processing-engine"; + reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>; + + crypto { + compatible = "intel,ixp4xx-crypto"; + intel,npe-handle = <&npe 2>; + queue-rx = <&qmgr 30>; + queue-txready = <&qmgr 29>; + }; + }; -- 2.30.2 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 2/3] crypto: ixp4xx: Add DT bindings 2021-05-10 21:36 ` [PATCH 2/3] crypto: ixp4xx: Add DT bindings Linus Walleij @ 2021-05-11 13:40 ` Rob Herring 2021-05-11 16:16 ` Rob Herring 1 sibling, 0 replies; 6+ messages in thread From: Rob Herring @ 2021-05-11 13:40 UTC (permalink / raw) To: Linus Walleij Cc: linux-crypto, devicetree, David S . Miller, Arnd Bergmann, Imre Kaloz, linux-arm-kernel, Herbert Xu, Krzysztof Halasa On Mon, 10 May 2021 23:36:33 +0200, Linus Walleij wrote: > This adds device tree bindings for the ixp4xx crypto engine. > > Cc: devicetree@vger.kernel.org > Signed-off-by: Linus Walleij <linus.walleij@linaro.org> > --- > Herbert, David: This can be applied separately once we are > happy with the bindings, alternatively it can be merged > with the support code into ARM SoC. > --- > .../bindings/crypto/intel,ixp4xx-crypto.yaml | 59 +++++++++++++++++++ > 1 file changed, 59 insertions(+) > create mode 100644 Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.example.dt.yaml: npe@c8006000: 'crypto' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml See https://patchwork.ozlabs.org/patch/1476741 This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit. ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/3] crypto: ixp4xx: Add DT bindings 2021-05-10 21:36 ` [PATCH 2/3] crypto: ixp4xx: Add DT bindings Linus Walleij 2021-05-11 13:40 ` Rob Herring @ 2021-05-11 16:16 ` Rob Herring 1 sibling, 0 replies; 6+ messages in thread From: Rob Herring @ 2021-05-11 16:16 UTC (permalink / raw) To: Linus Walleij Cc: linux-crypto, Herbert Xu, David S . Miller, linux-arm-kernel, Imre Kaloz, Krzysztof Halasa, Arnd Bergmann, devicetree On Mon, May 10, 2021 at 11:36:33PM +0200, Linus Walleij wrote: > This adds device tree bindings for the ixp4xx crypto engine. > > Cc: devicetree@vger.kernel.org > Signed-off-by: Linus Walleij <linus.walleij@linaro.org> > --- > Herbert, David: This can be applied separately once we are > happy with the bindings, alternatively it can be merged > with the support code into ARM SoC. > --- > .../bindings/crypto/intel,ixp4xx-crypto.yaml | 59 +++++++++++++++++++ > 1 file changed, 59 insertions(+) > create mode 100644 Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml > > diff --git a/Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml b/Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml > new file mode 100644 > index 000000000000..28d75f4f9a76 > --- /dev/null > +++ b/Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml > @@ -0,0 +1,59 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +# Copyright 2018 Linaro Ltd. > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/crypto/intel,ixp4xx-crypto.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: Intel IXP4xx cryptographic engine > + > +maintainers: > + - Linus Walleij <linus.walleij@linaro.org> > + > +description: | > + The Intel IXP4xx cryptographic engine makes use of the IXP4xx NPE > + (Network Processing Engine). Since it is not a device on its own > + it is defined as a subnode of the NPE, if crypto support is > + available on the platform. > + > +properties: > + compatible: > + const: intel,ixp4xx-crypto > + > + intel,npe-handle: > + $ref: '/schemas/types.yaml#/definitions/phandle-array' > + maxItems: 1 > + description: phandle to the NPE this ethernet instance is using > + and the instance to use in the second cell > + > + queue-rx: > + $ref: '/schemas/types.yaml#/definitions/phandle-array' > + maxItems: 1 > + description: phandle to the RX queue on the NPE > + > + queue-txready: > + $ref: '/schemas/types.yaml#/definitions/phandle-array' > + maxItems: 1 > + description: phandle to the TX READY queue on the NPE > + > +required: > + - compatible > + - intel,npe-handle > + - queue-rx > + - queue-txready > + > +additionalProperties: false > + > +examples: > + - | > + npe: npe@c8006000 { > + compatible = "intel,ixp4xx-network-processing-engine"; > + reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>; > + > + crypto { The parent schema needs to define 'crypto' and have a ref to this schema. I'd put the example there rather than piecemeal. > + compatible = "intel,ixp4xx-crypto"; > + intel,npe-handle = <&npe 2>; A bit redundant to have a phandle to the parent. > + queue-rx = <&qmgr 30>; > + queue-txready = <&qmgr 29>; > + }; > + }; > -- > 2.30.2 > ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 3/3] crypto: ixp4xx: Add device tree support 2021-05-10 21:36 [PATCH 1/3] crypto: ixp4xx: convert to platform driver Linus Walleij 2021-05-10 21:36 ` [PATCH 2/3] crypto: ixp4xx: Add DT bindings Linus Walleij @ 2021-05-10 21:36 ` Linus Walleij 2021-05-11 7:57 ` [PATCH 1/3] crypto: ixp4xx: convert to platform driver Corentin Labbe 2 siblings, 0 replies; 6+ messages in thread From: Linus Walleij @ 2021-05-10 21:36 UTC (permalink / raw) To: linux-crypto, Herbert Xu, David S . Miller Cc: linux-arm-kernel, Imre Kaloz, Krzysztof Halasa, Arnd Bergmann, Linus Walleij This makes the IXP4xx driver probe from the device tree and retrieve the NPE and two queue manager handled used to process crypto from the device tree. As the crypto engine is topologically a part of the NPE hardware, we augment the NPE driver to spawn the crypto engine as a child. The platform data probe path is going away in due time, for now it is an isolated else clause. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> --- Herbert, David: I am looking for an ACK to take this into the ARM SoC tree as follow-on to the refactoring into a platform device. --- drivers/crypto/ixp4xx_crypto.c | 105 ++++++++++++++++++++++++-------- drivers/soc/ixp4xx/ixp4xx-npe.c | 8 +++ 2 files changed, 86 insertions(+), 27 deletions(-) diff --git a/drivers/crypto/ixp4xx_crypto.c b/drivers/crypto/ixp4xx_crypto.c index 879b93927e2a..49d3454280b6 100644 --- a/drivers/crypto/ixp4xx_crypto.c +++ b/drivers/crypto/ixp4xx_crypto.c @@ -15,6 +15,7 @@ #include <linux/spinlock.h> #include <linux/gfp.h> #include <linux/module.h> +#include <linux/of.h> #include <crypto/ctr.h> #include <crypto/internal/des.h> @@ -71,15 +72,11 @@ #define MOD_AES256 (0x0a00 | KEYLEN_256) #define MAX_IVLEN 16 -#define NPE_ID 2 /* NPE C */ #define NPE_QLEN 16 /* Space for registering when the first * NPE_QLEN crypt_ctl are busy */ #define NPE_QLEN_TOTAL 64 -#define SEND_QID 29 -#define RECV_QID 30 - #define CTL_FLAG_UNUSED 0x0000 #define CTL_FLAG_USED 0x1000 #define CTL_FLAG_PERFORM_ABLK 0x0001 @@ -216,6 +213,8 @@ static const struct ix_hash_algo hash_alg_sha1 = { }; static struct npe *npe_c; +static unsigned int send_qid; +static unsigned int recv_qid; static struct dma_pool *buffer_pool = NULL; static struct dma_pool *ctx_pool = NULL; @@ -417,7 +416,7 @@ static void crypto_done_action(unsigned long arg) int i; for(i=0; i<4; i++) { - dma_addr_t phys = qmgr_get_entry(RECV_QID); + dma_addr_t phys = qmgr_get_entry(recv_qid); if (!phys) return; one_packet(phys); @@ -427,10 +426,52 @@ static void crypto_done_action(unsigned long arg) static int init_ixp_crypto(struct device *dev) { - int ret = -ENODEV; + struct device_node *np = dev->of_node; u32 msg[2] = { 0, 0 }; + int ret = -ENODEV; + unsigned int npe_id; + + dev_info(dev, "probing...\n"); + + /* Locate the NPE and queue manager to use from the phandle in the device tree */ + if (IS_ENABLED(CONFIG_OF) && np) { + struct of_phandle_args queue_spec; + struct of_phandle_args npe_spec; + + ret = of_parse_phandle_with_fixed_args(np, "intel,npe-handle", 1, 0, + &npe_spec); + if (ret) { + dev_err(dev, "no NPE engine specified\n"); + return -ENODEV; + } + npe_id = npe_spec.args[0]; + + ret = of_parse_phandle_with_fixed_args(np, "queue-rx", 1, 0, + &queue_spec); + if (ret) { + dev_err(dev, "no rx queue phandle\n"); + return -ENODEV; + } + recv_qid = queue_spec.args[0]; + + ret = of_parse_phandle_with_fixed_args(np, "queue-txready", 1, 0, + &queue_spec); + if (ret) { + dev_err(dev, "no txready queue phandle\n"); + return -ENODEV; + } + send_qid = queue_spec.args[0]; + } else { + /* + * Hardcoded engine when using platform data, this goes away + * when we switch to using DT only. + */ + npe_id = 2; + send_qid = 29; + recv_qid = 30; + } - npe_c = npe_request(NPE_ID); + npe_c = npe_request(npe_id); if (!npe_c) return ret; @@ -479,20 +520,20 @@ static int init_ixp_crypto(struct device *dev) if (!ctx_pool) { goto err; } - ret = qmgr_request_queue(SEND_QID, NPE_QLEN_TOTAL, 0, 0, + ret = qmgr_request_queue(send_qid, NPE_QLEN_TOTAL, 0, 0, "ixp_crypto:out", NULL); if (ret) goto err; - ret = qmgr_request_queue(RECV_QID, NPE_QLEN, 0, 0, + ret = qmgr_request_queue(recv_qid, NPE_QLEN, 0, 0, "ixp_crypto:in", NULL); if (ret) { - qmgr_release_queue(SEND_QID); + qmgr_release_queue(send_qid); goto err; } - qmgr_set_irq(RECV_QID, QUEUE_IRQ_SRC_NOT_EMPTY, irqhandler, NULL); + qmgr_set_irq(recv_qid, QUEUE_IRQ_SRC_NOT_EMPTY, irqhandler, NULL); tasklet_init(&crypto_done_tasklet, crypto_done_action, 0); - qmgr_enable_irq(RECV_QID); + qmgr_enable_irq(recv_qid); return 0; npe_error: @@ -508,11 +549,11 @@ static int init_ixp_crypto(struct device *dev) static void release_ixp_crypto(struct device *dev) { - qmgr_disable_irq(RECV_QID); + qmgr_disable_irq(recv_qid); tasklet_kill(&crypto_done_tasklet); - qmgr_release_queue(SEND_QID); - qmgr_release_queue(RECV_QID); + qmgr_release_queue(send_qid); + qmgr_release_queue(recv_qid); dma_pool_destroy(ctx_pool); dma_pool_destroy(buffer_pool); @@ -645,8 +686,8 @@ static int register_chain_var(struct crypto_tfm *tfm, u8 xpad, u32 target, buf->phys_addr = pad_phys; atomic_inc(&ctx->configuring); - qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt)); - BUG_ON(qmgr_stat_overflow(SEND_QID)); + qmgr_put_entry(send_qid, crypt_virt2phys(crypt)); + BUG_ON(qmgr_stat_overflow(send_qid)); return 0; } @@ -720,8 +761,8 @@ static int gen_rev_aes_key(struct crypto_tfm *tfm) crypt->ctl_flags |= CTL_FLAG_GEN_REVAES; atomic_inc(&ctx->configuring); - qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt)); - BUG_ON(qmgr_stat_overflow(SEND_QID)); + qmgr_put_entry(send_qid, crypt_virt2phys(crypt)); + BUG_ON(qmgr_stat_overflow(send_qid)); return 0; } @@ -872,7 +913,7 @@ static int ablk_perform(struct skcipher_request *req, int encrypt) gfp_t flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL : GFP_ATOMIC; - if (qmgr_stat_full(SEND_QID)) + if (qmgr_stat_full(send_qid)) return -EAGAIN; if (atomic_read(&ctx->configuring)) return -EAGAIN; @@ -916,8 +957,8 @@ static int ablk_perform(struct skcipher_request *req, int encrypt) req_ctx->src = src_hook.next; crypt->src_buf = src_hook.phys_next; crypt->ctl_flags |= CTL_FLAG_PERFORM_ABLK; - qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt)); - BUG_ON(qmgr_stat_overflow(SEND_QID)); + qmgr_put_entry(send_qid, crypt_virt2phys(crypt)); + BUG_ON(qmgr_stat_overflow(send_qid)); return -EINPROGRESS; free_buf_src: @@ -980,7 +1021,7 @@ static int aead_perform(struct aead_request *req, int encrypt, enum dma_data_direction src_direction = DMA_BIDIRECTIONAL; unsigned int lastlen; - if (qmgr_stat_full(SEND_QID)) + if (qmgr_stat_full(send_qid)) return -EAGAIN; if (atomic_read(&ctx->configuring)) return -EAGAIN; @@ -1064,8 +1105,8 @@ static int aead_perform(struct aead_request *req, int encrypt, } crypt->ctl_flags |= CTL_FLAG_PERFORM_AEAD; - qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt)); - BUG_ON(qmgr_stat_overflow(SEND_QID)); + qmgr_put_entry(send_qid, crypt_virt2phys(crypt)); + BUG_ON(qmgr_stat_overflow(send_qid)); return -EINPROGRESS; free_buf_dst: @@ -1359,12 +1400,13 @@ static struct ixp_aead_alg ixp4xx_aeads[] = { static int ixp_crypto_probe(struct platform_device *_pdev) { + struct device *dev = &_pdev->dev; int num = ARRAY_SIZE(ixp4xx_algos); int i, err; pdev = _pdev; - err = init_ixp_crypto(&pdev->dev); + err = init_ixp_crypto(dev); if (err) return err; @@ -1458,11 +1500,20 @@ static int ixp_crypto_remove(struct platform_device *pdev) return 0; } +static const struct of_device_id ixp4xx_crypto_of_match[] = { + { + .compatible = "intel,ixp4xx-crypto", + }, + {}, +}; static struct platform_driver ixp_crypto_driver = { .probe = ixp_crypto_probe, .remove = ixp_crypto_remove, - .driver = { .name = "ixp4xx_crypto" }, + .driver = { + .name = "ixp4xx_crypto", + .of_match_table = ixp4xx_crypto_of_match, + }, }; module_platform_driver(ixp_crypto_driver); diff --git a/drivers/soc/ixp4xx/ixp4xx-npe.c b/drivers/soc/ixp4xx/ixp4xx-npe.c index ec90b44fa0cd..e9e56f926e2d 100644 --- a/drivers/soc/ixp4xx/ixp4xx-npe.c +++ b/drivers/soc/ixp4xx/ixp4xx-npe.c @@ -18,6 +18,7 @@ #include <linux/kernel.h> #include <linux/module.h> #include <linux/of.h> +#include <linux/of_platform.h> #include <linux/platform_device.h> #include <linux/soc/ixp4xx/npe.h> @@ -679,7 +680,9 @@ static int ixp4xx_npe_probe(struct platform_device *pdev) { int i, found = 0; struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; struct resource *res; + int ret; for (i = 0; i < NPE_COUNT; i++) { struct npe *npe = &npe_tab[i]; @@ -711,6 +714,11 @@ static int ixp4xx_npe_probe(struct platform_device *pdev) if (!found) return -ENODEV; + + /* Spawn crypto subdevice if using device tree */ + if (IS_ENABLED(CONFIG_OF) && np) + devm_of_platform_populate(dev); + return 0; } -- 2.30.2 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/3] crypto: ixp4xx: convert to platform driver 2021-05-10 21:36 [PATCH 1/3] crypto: ixp4xx: convert to platform driver Linus Walleij 2021-05-10 21:36 ` [PATCH 2/3] crypto: ixp4xx: Add DT bindings Linus Walleij 2021-05-10 21:36 ` [PATCH 3/3] crypto: ixp4xx: Add device tree support Linus Walleij @ 2021-05-11 7:57 ` Corentin Labbe 2 siblings, 0 replies; 6+ messages in thread From: Corentin Labbe @ 2021-05-11 7:57 UTC (permalink / raw) To: Linus Walleij Cc: linux-crypto, Herbert Xu, David S . Miller, linux-arm-kernel, Imre Kaloz, Krzysztof Halasa, Arnd Bergmann Le Mon, May 10, 2021 at 11:36:32PM +0200, Linus Walleij a écrit : > From: Arnd Bergmann <arnd@arndb.de> > > The ixp4xx_crypto driver traditionally registers a bare platform > device without attaching it to a driver, and detects the hardware > at module init time by reading an SoC specific hardware register. > > Change this to the conventional method of registering the platform > device from the platform code itself when the device is present, > turning the module_init/module_exit functions into probe/release > driver callbacks. > > This enables compile-testing as well as potentially having ixp4xx > coexist with other ARMv5 platforms in the same kernel in the future. > > Signed-off-by: Arnd Bergmann <arnd@arndb.de> > Signed-off-by: Linus Walleij <linus.walleij@linaro.org> > --- > Herbert, David: I am looking for an ACK to take this > into the ARM SoC tree as we want to change more stuff in > the machine at the same time that we want to resolve > there. > --- > arch/arm/mach-ixp4xx/common.c | 26 ++++++++++++++++++++++++ > drivers/crypto/Kconfig | 3 ++- > drivers/crypto/ixp4xx_crypto.c | 37 ++++++++++++---------------------- > 3 files changed, 41 insertions(+), 25 deletions(-) > Hello With minor editing I successfully added this series on top of my fix series https://lore.kernel.org/patchwork/cover/1421865/ With the following patch, I successfully booted my epbx100 board and the crypto driver loaded. --- a/arch/arm/boot/dts/intel-ixp4xx.dtsi +++ b/arch/arm/boot/dts/intel-ixp4xx.dtsi @@ -61,9 +61,16 @@ timer@c8005000 { interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; }; - npe@c8006000 { + npe: npe@c8006000 { compatible = "intel,ixp4xx-network-processing-engine"; reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>; + + crypto { + compatible = "intel,ixp4xx-crypto"; + intel,npe-handle = <&npe 2>; + queue-rx = <&qmgr 30>; + queue-txready = <&qmgr 29>; + }; }; }; }; So you could add Tested-by: Corentin Labbe <clabbe@baylibre.com> Thanks ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-05-12 21:08 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-05-10 21:36 [PATCH 1/3] crypto: ixp4xx: convert to platform driver Linus Walleij 2021-05-10 21:36 ` [PATCH 2/3] crypto: ixp4xx: Add DT bindings Linus Walleij 2021-05-11 13:40 ` Rob Herring 2021-05-11 16:16 ` Rob Herring 2021-05-10 21:36 ` [PATCH 3/3] crypto: ixp4xx: Add device tree support Linus Walleij 2021-05-11 7:57 ` [PATCH 1/3] crypto: ixp4xx: convert to platform driver Corentin Labbe
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