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From: Dan Williams <dan.j.williams@intel.com>
To: linux-cxl@vger.kernel.org
Cc: vishal.l.verma@intel.com, dave.jiang@intel.com,
	ira.weiny@intel.com, alison.schofield@intel.com
Subject: [ndctl PATCH 6/6] cxl/test: Validate switch port settings in cxl-region-sysfs.sh
Date: Fri, 05 Aug 2022 13:38:26 -0700	[thread overview]
Message-ID: <165973190625.1528532.12244196912617964754.stgit@dwillia2-xfh.jf.intel.com> (raw)
In-Reply-To: <165973187080.1528532.8097010788284626448.stgit@dwillia2-xfh.jf.intel.com>

A recent kernel fix to add the missing update of endpoint decoder HPA range
settings regressed switch decoder HPA range settings. Add validation for
switch port settings to avoid regressions like that going forward.

Signed-off-by: Dan Williams <dan.j.williams@intel.com>
---
 test/cxl-region-sysfs.sh |   32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/test/cxl-region-sysfs.sh b/test/cxl-region-sysfs.sh
index 110e03709e39..ae0f55653814 100644
--- a/test/cxl-region-sysfs.sh
+++ b/test/cxl-region-sysfs.sh
@@ -112,6 +112,38 @@ do
 	[ $res -ne $region_base ] && err "$LINENO: decoder: $i base: $res region_base: $region_base"
 done
 
+# validate all switch decoders have the correct settings
+nr_switches=$((nr_targets/2))
+nr_host_bridges=$((nr_switches/2))
+nr_switch_decoders=$((nr_switches + nr_host_bridges))
+
+json=$($CXL list -D -r $region -d switch)
+readarray -t switch_decoders < <(echo $json | jq -r ".[].decoder")
+
+[ ${#switch_decoders[@]} -ne $nr_switch_decoders ] && err \
+"$LINENO: expected $nr_switch_decoders got ${#switch_decoders[@]} switch decoders"
+
+for i in ${switch_decoders[@]}
+do
+	decoder=$(echo $json | jq -r ".[] | select(.decoder == \"$i\")")
+	id=${i#decoder}
+	port_id=${id%.*}
+	depth=$($CXL list -p $port_id -S | jq -r ".[].depth")
+	iw=$(echo $decoder | jq -r ".interleave_ways")
+	ig=$(echo $decoder | jq -r ".interleave_granularity")
+
+	[ $iw -ne 2 ] && err "$LINENO: decoder: $i iw: $iw targets: 2"
+	[ $ig -ne $((r_ig << depth)) ] && err \
+	"$LINENO: decoder: $i ig: $ig switch_ig: $((r_ig << depth))"
+
+	res=$(echo $decoder | jq -r ".resource")
+	sz=$(echo $decoder | jq -r ".size")
+	[ $sz -ne $region_size ] && err \
+	"$LINENO: decoder: $i sz: $sz region_size: $region_size"
+	[ $res -ne $region_base ] && err \
+	"$LINENO: decoder: $i base: $res region_base: $region_base"
+done
+
 # walk up the topology and commit all decoders
 echo 1 > /sys/bus/cxl/devices/$region/commit
 


  parent reply	other threads:[~2022-08-05 20:38 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-05 20:37 [ndctl PATCH 0/6] cxl/test: Add more region ABI validation Dan Williams
2022-08-05 20:37 ` [ndctl PATCH 1/6] cxl/test: Validate endpoint interleave geometry Dan Williams
2022-08-05 20:38 ` [ndctl PATCH 2/6] cxl/list: Add interleave parameters to decoder listings Dan Williams
2022-08-05 20:38 ` [ndctl PATCH 3/6] cxl/list: Add region " Dan Williams
2022-08-05 20:38 ` [ndctl PATCH 4/6] cxl/list: Filter decoders by region Dan Williams
2022-08-05 20:38 ` [ndctl PATCH 5/6] cxl/list: Add 'depth' to port listings Dan Williams
2022-08-05 20:38 ` Dan Williams [this message]
2022-09-20 21:19 ` [ndctl PATCH 0/6] cxl/test: Add more region ABI validation Dave Jiang

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