ACPI Working Group Code First ECR for a new CXL Root Object

ACPI Working Group Code First ECR for a new CXL Root Object

[Verma, Vishal L]

This is a public RFC of an ACPI proposal to add a new CXL Root Object
that indicates the presence of a CXL hierarchy. The proposal is being
made in the new 'Code First' workflow of the ACPI Spec Working Group.
The subject matter here has been explored in previously posted patches
to QEMU[1] as well as Linux[2]. These patches have served as a proof-of-
concept test vehicle to help ensure that the proposal works in practice.
The cover letter in series [2] goes into additional detail (section
titled 'ACPI0017') for the reasoning behind the proposal, and what is
needed beyond what's described in the CXL 2.0 spec.

The change proposal that follows is in markdown format.

[1]: https://lore.kernel.org/qemu-devel/20201111054724.794888-1-ben.widawsky@intel.com/
[2]: https://lore.kernel.org/linux-cxl/20201111054356.793390-1-ben.widawsky@intel.com/

----

# Title: Add CXL Root Object _HID

# Status: Draft

# Document: ACPI Specification 6.4

# License
SPDX-License Identifier: CC-BY-4.0

# Submitter:
* Sponsor: Vishal Verma, Intel
* Creators/Contributors:
    * Chet Douglas, Intel
    * Ben Widawsky, Intel
    * Dan Williams, Intel
    * Vishal Verma, Intel

# Summary of the Change
Add “Compute Express Link Root Object” enumeration value to the ACPI
Device IDs Table (5.160).

# Benefits of the Change
Compute Express Link (CXL) is a new high-speed CPU-to-Device and CPU-to-
Memory interconnect. The new ACPI Device ID represents a singleton
device that allows the OSPM to trigger the enumeration of the CXL.mem
address space, and indicates the presence of cross Host Bridge
(ACPI0016) interleaved CXL.mem resources.

# Impact of the Change
One new row added to the ACPI Device IDs table (5.160).

# References
* Compute Express Link Specification v2.0,
<https://www.computeexpresslink.org/>

# Detailed Description of the Change

Add “Compute Express Link Root Object” enumeration device

### 5.6.7 Device Class-Specific Objects

Most device objects are controlled through generic objects and  ...

Table 5.160 ACPI Device IDs

| Value | Description |
| :--- | :---: | :---: | :--------------------------- |
| .. | .. |
| ACPI0017 | **Compute Express Link Root Object:** This device
represents the root of a CXL capable device hierarchy. It shall be
present whenever the platform allows OSPM to dynamically assign CXL
endpoints to a platform address space. |

## Special Instructions

Re: ACPI Working Group Code First ECR for a new CXL Root Object

[Verma, Vishal L]

On Thu, 2020-12-03 at 20:12 +0000, Verma, Vishal L wrote:
> This is a public RFC of an ACPI proposal to add a new CXL Root Object
> that indicates the presence of a CXL hierarchy. The proposal is being
> made in the new 'Code First' workflow of the ACPI Spec Working Group.
> The subject matter here has been explored in previously posted patches
> to QEMU[1] as well as Linux[2]. These patches have served as a proof-of-
> concept test vehicle to help ensure that the proposal works in practice.
> The cover letter in series [2] goes into additional detail (section
> titled 'ACPI0017') for the reasoning behind the proposal, and what is
> needed beyond what's described in the CXL 2.0 spec.
> 
> The change proposal that follows is in markdown format.
> 
> [1]: https://lore.kernel.org/qemu-devel/20201111054724.794888-1-ben.widawsky@intel.com/
> [2]: https://lore.kernel.org/linux-cxl/20201111054356.793390-1-ben.widawsky@intel.com/
> 
> ----
> 
> # Title: Add CXL Root Object _HID
> 
> # Status: Draft

This ECR was approved in the ASWG today without any modifications, and
this content can be expected to be present in the next release of the
specification.

> 
> # Document: ACPI Specification 6.4
> 
> # License
> SPDX-License Identifier: CC-BY-4.0
> 
> # Submitter:
> * Sponsor: Vishal Verma, Intel
> * Creators/Contributors:
>     * Chet Douglas, Intel
>     * Ben Widawsky, Intel
>     * Dan Williams, Intel
>     * Vishal Verma, Intel
> 
> # Summary of the Change
> Add “Compute Express Link Root Object” enumeration value to the ACPI
> Device IDs Table (5.160).
> 
> # Benefits of the Change
> Compute Express Link (CXL) is a new high-speed CPU-to-Device and CPU-to-
> Memory interconnect. The new ACPI Device ID represents a singleton
> device that allows the OSPM to trigger the enumeration of the CXL.mem
> address space, and indicates the presence of cross Host Bridge
> (ACPI0016) interleaved CXL.mem resources.
> 
> # Impact of the Change
> One new row added to the ACPI Device IDs table (5.160).
> 
> # References
> * Compute Express Link Specification v2.0,
> <https://www.computeexpresslink.org/>
> 
> # Detailed Description of the Change
> 
> Add “Compute Express Link Root Object” enumeration device
> 
> ### 5.6.7 Device Class-Specific Objects
> 
> Most device objects are controlled through generic objects and  ...
> 
> Table 5.160 ACPI Device IDs
> 
> > Value | Description |
> > :--- | :---: | :---: | :--------------------------- |
> > .. | .. |
> > ACPI0017 | **Compute Express Link Root Object:** This device
> represents the root of a CXL capable device hierarchy. It shall be
> present whenever the platform allows OSPM to dynamically assign CXL
> endpoints to a platform address space. |
> 
> ## Special Instructions

Re: ACPI Working Group Code First ECR for a new CXL Root Object

[Ben Widawsky]

On 21-01-14 19:17:52, Verma, Vishal L wrote:
> On Thu, 2020-12-03 at 20:12 +0000, Verma, Vishal L wrote:
> > This is a public RFC of an ACPI proposal to add a new CXL Root Object
> > that indicates the presence of a CXL hierarchy. The proposal is being
> > made in the new 'Code First' workflow of the ACPI Spec Working Group.
> > The subject matter here has been explored in previously posted patches
> > to QEMU[1] as well as Linux[2]. These patches have served as a proof-of-
> > concept test vehicle to help ensure that the proposal works in practice.
> > The cover letter in series [2] goes into additional detail (section
> > titled 'ACPI0017') for the reasoning behind the proposal, and what is
> > needed beyond what's described in the CXL 2.0 spec.
> >
> > The change proposal that follows is in markdown format.
> >
> > [1]: https://lore.kernel.org/qemu-devel/20201111054724.794888-1-ben.widawsky@intel.com/
> > [2]: https://lore.kernel.org/linux-cxl/20201111054356.793390-1-ben.widawsky@intel.com/
> >
> > ----
> >
> > # Title: Add CXL Root Object _HID
> >
> > # Status: Draft
> 
> This ECR was approved in the ASWG today without any modifications, and
> this content can be expected to be present in the next release of the
> specification.
> 

Nice job Vishal!

> >
> > # Document: ACPI Specification 6.4
> >
> > # License
> > SPDX-License Identifier: CC-BY-4.0
> >
> > # Submitter:
> > * Sponsor: Vishal Verma, Intel
> > * Creators/Contributors:
> >     * Chet Douglas, Intel
> >     * Ben Widawsky, Intel
> >     * Dan Williams, Intel
> >     * Vishal Verma, Intel
> >
> > # Summary of the Change
> > Add “Compute Express Link Root Object” enumeration value to the ACPI
> > Device IDs Table (5.160).
> >
> > # Benefits of the Change
> > Compute Express Link (CXL) is a new high-speed CPU-to-Device and CPU-to-
> > Memory interconnect. The new ACPI Device ID represents a singleton
> > device that allows the OSPM to trigger the enumeration of the CXL.mem
> > address space, and indicates the presence of cross Host Bridge
> > (ACPI0016) interleaved CXL.mem resources.
> >
> > # Impact of the Change
> > One new row added to the ACPI Device IDs table (5.160).
> >
> > # References
> > * Compute Express Link Specification v2.0,
> > <https://www.computeexpresslink.org/>
> >
> > # Detailed Description of the Change
> >
> > Add “Compute Express Link Root Object” enumeration device
> >
> > ### 5.6.7 Device Class-Specific Objects
> >
> > Most device objects are controlled through generic objects and  ...
> >
> > Table 5.160 ACPI Device IDs
> >
> > > Value | Description |
> > > :--- | :---: | :---: | :--------------------------- |
> > > .. | .. |
> > > ACPI0017 | **Compute Express Link Root Object:** This device
> > represents the root of a CXL capable device hierarchy. It shall be
> > present whenever the platform allows OSPM to dynamically assign CXL
> > endpoints to a platform address space. |
> >
> > ## Special Instructions
>