* [PATCH] cxl/hdm: Fix decoder count calculation
@ 2021-06-10 21:53 Ben Widawsky
2021-06-10 22:00 ` Dan Williams
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Ben Widawsky @ 2021-06-10 21:53 UTC (permalink / raw)
To: linux-cxl, Dan Williams; +Cc: Ben Widawsky, Jonathan Cameron, Ira Weiny
The decoder count in the HDM decoder capability structure is an encoded
field. As defined in the spec:
Decoder Count: Reports the number of memory address decoders implemented
by the component.
0 – 1 Decoder
1 – 2 Decoders
2 – 4 Decoders
3 – 6 Decoders
4 – 8 Decoders
5 – 10 DecodersAll other values are reserved
Nothing is actually fixed by this as nothing actually used this mapping
yet.
Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Ira Weiny <ira.weiny@intel.com>
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
---
drivers/cxl/core.c | 3 ++-
drivers/cxl/cxl.h | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/cxl/core.c b/drivers/cxl/core.c
index cda09a9cd98e..92db02fe7aa8 100644
--- a/drivers/cxl/core.c
+++ b/drivers/cxl/core.c
@@ -666,7 +666,8 @@ void cxl_probe_component_regs(struct device *dev, void __iomem *base,
hdr = readl(register_block);
- decoder_cnt = FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, hdr);
+ decoder_cnt =
+ cxl_hdm_decoder_count(FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, hdr));
length = 0x20 * decoder_cnt + 0x10;
map->hdm_decoder.valid = true;
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 1ffc5e07e24d..f0dff7d96286 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -35,6 +35,7 @@
/* HDM decoders CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure */
#define CXL_HDM_DECODER_CAP_OFFSET 0x0
#define CXL_HDM_DECODER_COUNT_MASK GENMASK(3, 0)
+#define cxl_hdm_decoder_count(bits) ((bits) == 0 ? 1 : (bits) * 2)
#define CXL_HDM_DECODER_TARGET_COUNT_MASK GENMASK(7, 4)
#define CXL_HDM_DECODER0_BASE_LOW_OFFSET 0x10
#define CXL_HDM_DECODER0_BASE_HIGH_OFFSET 0x14
--
2.32.0
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH] cxl/hdm: Fix decoder count calculation
2021-06-10 21:53 [PATCH] cxl/hdm: Fix decoder count calculation Ben Widawsky
@ 2021-06-10 22:00 ` Dan Williams
2021-06-11 10:37 ` Jonathan Cameron
2021-06-11 19:01 ` [PATCH v2] " Ben Widawsky
2 siblings, 0 replies; 5+ messages in thread
From: Dan Williams @ 2021-06-10 22:00 UTC (permalink / raw)
To: Ben Widawsky; +Cc: linux-cxl, Jonathan Cameron, Ira Weiny
On Thu, Jun 10, 2021 at 2:53 PM Ben Widawsky <ben.widawsky@intel.com> wrote:
>
> The decoder count in the HDM decoder capability structure is an encoded
> field. As defined in the spec:
>
> Decoder Count: Reports the number of memory address decoders implemented
> by the component.
> 0 – 1 Decoder
> 1 – 2 Decoders
> 2 – 4 Decoders
> 3 – 6 Decoders
> 4 – 8 Decoders
> 5 – 10 DecodersAll other values are reserved
>
> Nothing is actually fixed by this as nothing actually used this mapping
> yet.
>
> Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Cc: Ira Weiny <ira.weiny@intel.com>
> Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
> ---
> drivers/cxl/core.c | 3 ++-
> drivers/cxl/cxl.h | 1 +
> 2 files changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/cxl/core.c b/drivers/cxl/core.c
> index cda09a9cd98e..92db02fe7aa8 100644
> --- a/drivers/cxl/core.c
> +++ b/drivers/cxl/core.c
> @@ -666,7 +666,8 @@ void cxl_probe_component_regs(struct device *dev, void __iomem *base,
>
> hdr = readl(register_block);
>
> - decoder_cnt = FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, hdr);
> + decoder_cnt =
> + cxl_hdm_decoder_count(FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, hdr));
How about make it a static inline helper that takes @hdr and move the
FIELD_GET inside there to save some indentation?
I still think it warrants a Fixes: tag, the commit ids in cxl.git/next
are stable.
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] cxl/hdm: Fix decoder count calculation
2021-06-10 21:53 [PATCH] cxl/hdm: Fix decoder count calculation Ben Widawsky
2021-06-10 22:00 ` Dan Williams
@ 2021-06-11 10:37 ` Jonathan Cameron
2021-06-11 19:01 ` [PATCH v2] " Ben Widawsky
2 siblings, 0 replies; 5+ messages in thread
From: Jonathan Cameron @ 2021-06-11 10:37 UTC (permalink / raw)
To: Ben Widawsky; +Cc: linux-cxl, Dan Williams, Ira Weiny
On Thu, 10 Jun 2021 14:53:32 -0700
Ben Widawsky <ben.widawsky@intel.com> wrote:
> The decoder count in the HDM decoder capability structure is an encoded
> field. As defined in the spec:
>
> Decoder Count: Reports the number of memory address decoders implemented
> by the component.
> 0 – 1 Decoder
> 1 – 2 Decoders
> 2 – 4 Decoders
> 3 – 6 Decoders
> 4 – 8 Decoders
> 5 – 10 DecodersAll other values are reserved
>
> Nothing is actually fixed by this as nothing actually used this mapping
> yet.
>
> Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Cc: Ira Weiny <ira.weiny@intel.com>
> Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
lgtm.
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
> drivers/cxl/core.c | 3 ++-
> drivers/cxl/cxl.h | 1 +
> 2 files changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/cxl/core.c b/drivers/cxl/core.c
> index cda09a9cd98e..92db02fe7aa8 100644
> --- a/drivers/cxl/core.c
> +++ b/drivers/cxl/core.c
> @@ -666,7 +666,8 @@ void cxl_probe_component_regs(struct device *dev, void __iomem *base,
>
> hdr = readl(register_block);
>
> - decoder_cnt = FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, hdr);
> + decoder_cnt =
> + cxl_hdm_decoder_count(FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, hdr));
> length = 0x20 * decoder_cnt + 0x10;
>
> map->hdm_decoder.valid = true;
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index 1ffc5e07e24d..f0dff7d96286 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -35,6 +35,7 @@
> /* HDM decoders CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure */
> #define CXL_HDM_DECODER_CAP_OFFSET 0x0
> #define CXL_HDM_DECODER_COUNT_MASK GENMASK(3, 0)
> +#define cxl_hdm_decoder_count(bits) ((bits) == 0 ? 1 : (bits) * 2)
> #define CXL_HDM_DECODER_TARGET_COUNT_MASK GENMASK(7, 4)
> #define CXL_HDM_DECODER0_BASE_LOW_OFFSET 0x10
> #define CXL_HDM_DECODER0_BASE_HIGH_OFFSET 0x14
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2] cxl/hdm: Fix decoder count calculation
2021-06-10 21:53 [PATCH] cxl/hdm: Fix decoder count calculation Ben Widawsky
2021-06-10 22:00 ` Dan Williams
2021-06-11 10:37 ` Jonathan Cameron
@ 2021-06-11 19:01 ` Ben Widawsky
2021-06-11 19:08 ` Dan Williams
2 siblings, 1 reply; 5+ messages in thread
From: Ben Widawsky @ 2021-06-11 19:01 UTC (permalink / raw)
To: linux-cxl, Dan Williams; +Cc: Ben Widawsky, Ira Weiny, Jonathan Cameron
The decoder count in the HDM decoder capability structure is an encoded
field. As defined in the spec:
Decoder Count: Reports the number of memory address decoders implemented
by the component.
0 – 1 Decoder
1 – 2 Decoders
2 – 4 Decoders
3 – 6 Decoders
4 – 8 Decoders
5 – 10 Decoders
All other values are reserved
Nothing is actually fixed by this as nothing actually used this mapping
yet.
Cc: Ira Weiny <ira.weiny@intel.com>
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
---
v2:
- Minor whitespace cleanup in commit message.
- Move value decoder to inline function. (Dan)
- Rework value decoding logic to be more concise.
---
drivers/cxl/core.c | 2 +-
drivers/cxl/cxl.h | 7 +++++++
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/cxl/core.c b/drivers/cxl/core.c
index 6db660249cea..49744ad885de 100644
--- a/drivers/cxl/core.c
+++ b/drivers/cxl/core.c
@@ -603,7 +603,7 @@ void cxl_probe_component_regs(struct device *dev, void __iomem *base,
hdr = readl(register_block);
- decoder_cnt = FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, hdr);
+ decoder_cnt = cxl_hdm_decoder_count(hdr);
length = 0x20 * decoder_cnt + 0x10;
map->hdm_decoder.valid = true;
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 3f9a6f7b05db..f1e52487c644 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -42,6 +42,13 @@
#define CXL_HDM_DECODER0_SIZE_HIGH_OFFSET 0x1c
#define CXL_HDM_DECODER0_CTRL_OFFSET 0x20
+static inline int cxl_hdm_decoder_count(u32 cap_hdr)
+{
+ int val = FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, cap_hdr);
+
+ return val ? val * 2 : 1;
+}
+
/* CXL 2.0 8.2.8.1 Device Capabilities Array Register */
#define CXLDEV_CAP_ARRAY_OFFSET 0x0
#define CXLDEV_CAP_ARRAY_CAP_ID 0
--
2.32.0
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH v2] cxl/hdm: Fix decoder count calculation
2021-06-11 19:01 ` [PATCH v2] " Ben Widawsky
@ 2021-06-11 19:08 ` Dan Williams
0 siblings, 0 replies; 5+ messages in thread
From: Dan Williams @ 2021-06-11 19:08 UTC (permalink / raw)
To: Ben Widawsky; +Cc: linux-cxl, Ira Weiny, Jonathan Cameron
On Fri, Jun 11, 2021 at 12:01 PM Ben Widawsky <ben.widawsky@intel.com> wrote:
>
> The decoder count in the HDM decoder capability structure is an encoded
> field. As defined in the spec:
>
> Decoder Count: Reports the number of memory address decoders implemented
> by the component.
> 0 – 1 Decoder
> 1 – 2 Decoders
> 2 – 4 Decoders
> 3 – 6 Decoders
> 4 – 8 Decoders
> 5 – 10 Decoders
> All other values are reserved
>
> Nothing is actually fixed by this as nothing actually used this mapping
> yet.
I'll still add the Fixes tag because the original commit is broken
even if the impact of fixing this bug is moot in the near term.
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2021-06-11 19:09 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-06-10 21:53 [PATCH] cxl/hdm: Fix decoder count calculation Ben Widawsky
2021-06-10 22:00 ` Dan Williams
2021-06-11 10:37 ` Jonathan Cameron
2021-06-11 19:01 ` [PATCH v2] " Ben Widawsky
2021-06-11 19:08 ` Dan Williams
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).