From: Ben Widawsky <ben.widawsky@intel.com>
To: linux-cxl@vger.kernel.org
Cc: Ben Widawsky <ben.widawsky@intel.com>,
Alison Schofield <alison.schofield@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Jonathan Cameron <Jonathan.Cameron@Huawei.com>,
Vishal Verma <vishal.l.verma@intel.com>
Subject: [RFC PATCH 5/5] cxl/mem: Check that the device is CXL.mem capable
Date: Thu, 17 Jun 2021 17:52:00 -0700 [thread overview]
Message-ID: <20210618005200.997804-6-ben.widawsky@intel.com> (raw)
In-Reply-To: <20210618005200.997804-1-ben.widawsky@intel.com>
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
---
drivers/cxl/mem.c | 18 ++++++++++++++++++
drivers/cxl/pci.h | 5 ++++-
2 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
index cbf18df24109..7f26937c7151 100644
--- a/drivers/cxl/mem.c
+++ b/drivers/cxl/mem.c
@@ -4,6 +4,7 @@
#include <linux/module.h>
#include <linux/pci.h>
#include "mem.h"
+#include "pci.h"
/**
* DOC: cxl mem
@@ -41,14 +42,31 @@ static int cxl_memdev_probe(struct device *dev)
{
struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
struct cxl_mem *cxlm = cxlmd->cxlm;
+ struct pci_dev *pdev = cxlm->pdev;
struct device *pdev_parent = cxlm->pdev->dev.parent;
struct device *port_dev;
+ int pcie_dvsec;
+ u16 dvsec_ctrl;
port_dev =
bus_find_device(&cxl_bus_type, NULL, pdev_parent, port_match);
if (!port_dev)
return -ENODEV;
+ pcie_dvsec = cxl_mem_dvsec(pdev, PCI_DVSEC_ID_PCIE_DVSEC_CXL_DVSEC_ID);
+ if (!pcie_dvsec) {
+ dev_err(dev, "Unable to determine CXL protocol support");
+ return -ENODEV;
+ }
+
+ pci_read_config_word(pdev,
+ pcie_dvsec + PCI_DVSEC_ID_CXL_PCIE_CTRL_OFFSET,
+ &dvsec_ctrl);
+ if (!(dvsec_ctrl & CXL_PCIE_MEM_ENABLE)) {
+ dev_err(dev, "CXL.cache protocol not supported on device");
+ return -ENODEV;
+ }
+
return 0;
}
diff --git a/drivers/cxl/pci.h b/drivers/cxl/pci.h
index 0d6f50f725bc..ee26bc8c2ec8 100644
--- a/drivers/cxl/pci.h
+++ b/drivers/cxl/pci.h
@@ -11,7 +11,10 @@
*/
#define PCI_DVSEC_HEADER1_LENGTH_MASK GENMASK(31, 20)
#define PCI_DVSEC_VENDOR_ID_CXL 0x1E98
-#define PCI_DVSEC_ID_CXL 0x0
+
+#define PCI_DVSEC_ID_PCIE_DVSEC_CXL_DVSEC_ID 0x0
+#define PCI_DVSEC_ID_CXL_PCIE_CTRL_OFFSET 0xC
+#define CXL_PCIE_MEM_ENABLE BIT(2)
#define PCI_DVSEC_ID_CXL_REGLOC_DVSEC_ID 0x8
#define PCI_DVSEC_ID_CXL_REGLOC_BLOCK1_OFFSET 0xC
--
2.32.0
next prev parent reply other threads:[~2021-06-18 0:52 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-18 0:51 [RFC PATCH 0/5] Introduce memdev driver Ben Widawsky
2021-06-18 0:51 ` [RFC PATCH 1/5] cxl/region: Only allow CXL capable targets Ben Widawsky
2021-06-18 14:08 ` Jonathan Cameron
2021-06-18 0:51 ` [RFC PATCH 2/5] cxl/mem: Introduce CXL mem driver Ben Widawsky
2021-06-18 0:51 ` [RFC PATCH 3/5] cxl/memdev: Determine CXL.mem capability Ben Widawsky
2021-06-18 14:14 ` Jonathan Cameron
2021-06-18 0:51 ` [RFC PATCH 4/5] cxl/pci: Export CXL DVSEC functionality Ben Widawsky
2021-06-18 15:00 ` Dan Williams
2021-06-18 0:52 ` Ben Widawsky [this message]
2021-06-18 14:24 ` [RFC PATCH 5/5] cxl/mem: Check that the device is CXL.mem capable Jonathan Cameron
2021-06-18 14:27 ` [RFC PATCH 0/5] Introduce memdev driver Jonathan Cameron
2021-06-30 17:49 ` Dan Williams
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