Re: [RFC PATCH 5/5] cxl/mem: Check that the device is CXL.mem capable

From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Ben Widawsky <ben.widawsky@intel.com>
Cc: <linux-cxl@vger.kernel.org>,
	Alison Schofield <alison.schofield@intel.com>,
	Dan Williams <dan.j.williams@intel.com>,
	"Ira Weiny" <ira.weiny@intel.com>,
	Vishal Verma <vishal.l.verma@intel.com>
Subject: Re: [RFC PATCH 5/5] cxl/mem: Check that the device is CXL.mem capable
Date: Fri, 18 Jun 2021 15:24:30 +0100	[thread overview]
Message-ID: <20210618152430.00001c60@Huawei.com> (raw)
In-Reply-To: <20210618005200.997804-6-ben.widawsky@intel.com>

On Thu, 17 Jun 2021 17:52:00 -0700
Ben Widawsky <ben.widawsky@intel.com> wrote:

> Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
> ---
>  drivers/cxl/mem.c | 18 ++++++++++++++++++
>  drivers/cxl/pci.h |  5 ++++-
>  2 files changed, 22 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
> index cbf18df24109..7f26937c7151 100644
> --- a/drivers/cxl/mem.c
> +++ b/drivers/cxl/mem.c
> @@ -4,6 +4,7 @@
>  #include <linux/module.h>
>  #include <linux/pci.h>
>  #include "mem.h"
> +#include "pci.h"
>  
>  /**
>   * DOC: cxl mem
> @@ -41,14 +42,31 @@ static int cxl_memdev_probe(struct device *dev)
>  {
>  	struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
>  	struct cxl_mem *cxlm = cxlmd->cxlm;
> +	struct pci_dev *pdev = cxlm->pdev;
>  	struct device *pdev_parent = cxlm->pdev->dev.parent;
>  	struct device *port_dev;
> +	int pcie_dvsec;
> +	u16 dvsec_ctrl;
>  
>  	port_dev =
>  		bus_find_device(&cxl_bus_type, NULL, pdev_parent, port_match);
>  	if (!port_dev)
>  		return -ENODEV;
>  
> +	pcie_dvsec = cxl_mem_dvsec(pdev, PCI_DVSEC_ID_PCIE_DVSEC_CXL_DVSEC_ID);
> +	if (!pcie_dvsec) {
> +		dev_err(dev, "Unable to determine CXL protocol support");
> +		return -ENODEV;
> +	}
> +
> +	pci_read_config_word(pdev,
> +			     pcie_dvsec + PCI_DVSEC_ID_CXL_PCIE_CTRL_OFFSET,
> +			     &dvsec_ctrl);
> +	if (!(dvsec_ctrl & CXL_PCIE_MEM_ENABLE)) {

Checking control rather than capability?  If you want to know if it supports
it read the bit in register at offset 0x0a

If there is a good reason to see if it's turned on, then document that
with a comment here somewhere and change the error message appropriately.

> +		dev_err(dev, "CXL.cache protocol not supported on device");
> +		return -ENODEV;
> +	}
> +
>  	return 0;
>  }
>  
> diff --git a/drivers/cxl/pci.h b/drivers/cxl/pci.h
> index 0d6f50f725bc..ee26bc8c2ec8 100644
> --- a/drivers/cxl/pci.h
> +++ b/drivers/cxl/pci.h
> @@ -11,7 +11,10 @@
>   */
>  #define PCI_DVSEC_HEADER1_LENGTH_MASK	GENMASK(31, 20)
>  #define PCI_DVSEC_VENDOR_ID_CXL		0x1E98
> -#define PCI_DVSEC_ID_CXL		0x0
> +
> +#define PCI_DVSEC_ID_PCIE_DVSEC_CXL_DVSEC_ID	0x0

????  That's a non obvious bit of naming!

> +#define PCI_DVSEC_ID_CXL_PCIE_CTRL_OFFSET	0xC
> +#define   CXL_PCIE_MEM_ENABLE			BIT(2)
>  
>  #define PCI_DVSEC_ID_CXL_REGLOC_DVSEC_ID	0x8
>  #define PCI_DVSEC_ID_CXL_REGLOC_BLOCK1_OFFSET	0xC