From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: qemu-devel@nongnu.org, "Alex Bennée" <alex.bennee@linaro.org>,
"Marcel Apfelbaum" <marcel@redhat.com>,
"Michael S . Tsirkin" <mst@redhat.com>,
"Igor Mammedov" <imammedo@redhat.com>
Cc: linux-cxl@vger.kernel.org,
"Ben Widawsky" <ben.widawsky@intel.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
linuxarm@huawei.com,
"Shameerali Kolothum Thodi"
<shameerali.kolothum.thodi@huawei.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Saransh Gupta1" <saransh@ibm.com>,
"Shreyas Shah" <shreyas.shah@elastics.cloud>,
"Chris Browy" <cbrowy@avery-design.com>,
"Samarth Saxena" <samarths@cadence.com>,
"Dan Williams" <dan.j.williams@intel.com>
Subject: [PATCH v5 42/43] qtest/cxl: Add very basic sanity tests
Date: Wed, 2 Feb 2022 14:10:36 +0000 [thread overview]
Message-ID: <20220202141037.17352-43-Jonathan.Cameron@huawei.com> (raw)
In-Reply-To: <20220202141037.17352-1-Jonathan.Cameron@huawei.com>
From: Ben Widawsky <ben.widawsky@intel.com>
Simple 'does it boot tests' with up to
2x PXB host bridge, each with 2x CXL RP and each of those with
a Type 3 memory device. Single CFMWS to interleave across the
two HBs and ultimate the 4 devices.
More complete tests may be possible but CXL interleave setup
is complex so a lot of steps will be needed.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Co-developed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
tests/qtest/cxl-test.c | 151 ++++++++++++++++++++++++++++++++++++++++
tests/qtest/meson.build | 4 ++
2 files changed, 155 insertions(+)
create mode 100644 tests/qtest/cxl-test.c
diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl-test.c
new file mode 100644
index 0000000000..a50c0c6de4
--- /dev/null
+++ b/tests/qtest/cxl-test.c
@@ -0,0 +1,151 @@
+/*
+ * QTest testcase for CXL
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "libqtest-single.h"
+
+#define QEMU_PXB_CMD "-machine q35,cxl=on " \
+ "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 " \
+ "-cxl-fixed-memory-window targets=cxl.0,size=4G "
+
+#define QEMU_2PXB_CMD "-machine q35,cxl=on " \
+ "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 " \
+ "-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 " \
+ "-cxl-fixed-memory-window targets=cxl.0,targets=cxl.1,size=4G "
+
+#define QEMU_RP "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 "
+
+/* Dual ports on first pxb */
+#define QEMU_2RP "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 " \
+ "-device cxl-rp,id=rp1,bus=cxl.0,chassis=0,slot=1 "
+
+/* Dual ports on each of the pxb instances */
+#define QEMU_4RP "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 " \
+ "-device cxl-rp,id=rp1,bus=cxl.0,chassis=0,slot=1 " \
+ "-device cxl-rp,id=rp2,bus=cxl.1,chassis=0,slot=2 " \
+ "-device cxl-rp,id=rp3,bus=cxl.1,chassis=0,slot=3 "
+
+#define QEMU_T3D "-object memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M " \
+ "-device cxl-type3,bus=rp0,memdev=cxl-mem0,id=cxl-pmem0,size=256M "
+
+#define QEMU_2T3D "-object memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M " \
+ "-device cxl-type3,bus=rp0,memdev=cxl-mem0,id=cxl-pmem0,size=256M " \
+ "-object memory-backend-file,id=cxl-mem1,mem-path=%s,size=256M " \
+ "-device cxl-type3,bus=rp1,memdev=cxl-mem1,id=cxl-pmem1,size=256M "
+
+#define QEMU_4T3D "-object memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M " \
+ "-device cxl-type3,bus=rp0,memdev=cxl-mem0,id=cxl-pmem0,size=256M " \
+ "-object memory-backend-file,id=cxl-mem1,mem-path=%s,size=256M " \
+ "-device cxl-type3,bus=rp1,memdev=cxl-mem1,id=cxl-pmem1,size=256M " \
+ "-object memory-backend-file,id=cxl-mem2,mem-path=%s,size=256M " \
+ "-device cxl-type3,bus=rp2,memdev=cxl-mem2,id=cxl-pmem2,size=256M " \
+ "-object memory-backend-file,id=cxl-mem3,mem-path=%s,size=256M " \
+ "-device cxl-type3,bus=rp3,memdev=cxl-mem3,id=cxl-pmem3,size=256M "
+
+static void cxl_basic_hb(void)
+{
+ qtest_start("-machine q35,cxl=on");
+ qtest_end();
+}
+
+static void cxl_basic_pxb(void)
+{
+ qtest_start("-machine q35,cxl=on -device pxb-cxl,bus=pcie.0");
+ qtest_end();
+}
+
+static void cxl_pxb_with_window(void)
+{
+ qtest_start(QEMU_PXB_CMD);
+ qtest_end();
+}
+
+static void cxl_2pxb_with_window(void)
+{
+ qtest_start(QEMU_2PXB_CMD);
+ qtest_end();
+}
+
+static void cxl_root_port(void)
+{
+ qtest_start(QEMU_PXB_CMD QEMU_RP);
+ qtest_end();
+}
+
+static void cxl_2root_port(void)
+{
+ qtest_start(QEMU_PXB_CMD QEMU_2RP);
+ qtest_end();
+}
+
+static void cxl_t3d(void)
+{
+ GString *cmdline;
+ char template[] = "/tmp/cxl-test-XXXXXX";
+ const char *tmpfs;
+
+ tmpfs = mkdtemp(template);
+
+ cmdline = g_string_new(NULL);
+ g_string_printf(cmdline, QEMU_PXB_CMD QEMU_RP QEMU_T3D, tmpfs);
+
+ qtest_start(cmdline->str);
+ qtest_end();
+
+ g_string_free(cmdline, TRUE);
+}
+
+static void cxl_1pxb_2rp_2t3d(void)
+{
+ GString *cmdline;
+ char template[] = "/tmp/cxl-test-XXXXXX";
+ const char *tmpfs;
+
+ tmpfs = mkdtemp(template);
+
+ cmdline = g_string_new(NULL);
+ g_string_printf(cmdline, QEMU_PXB_CMD QEMU_2RP QEMU_2T3D, tmpfs, tmpfs);
+
+ qtest_start(cmdline->str);
+ qtest_end();
+
+ g_string_free(cmdline, TRUE);
+}
+
+static void cxl_2pxb_4rp_4t3d(void)
+{
+ GString *cmdline;
+ char template[] = "/tmp/cxl-test-XXXXXX";
+ const char *tmpfs;
+
+ tmpfs = mkdtemp(template);
+
+ cmdline = g_string_new(NULL);
+ g_string_printf(cmdline, QEMU_2PXB_CMD QEMU_4RP QEMU_4T3D,
+ tmpfs, tmpfs, tmpfs, tmpfs);
+
+ qtest_start(cmdline->str);
+ qtest_end();
+
+ g_string_free(cmdline, TRUE);
+}
+
+int main(int argc, char **argv)
+{
+ g_test_init(&argc, &argv, NULL);
+
+ qtest_add_func("/pci/cxl/basic_hostbridge", cxl_basic_hb);
+ qtest_add_func("/pci/cxl/basic_pxb", cxl_basic_pxb);
+ qtest_add_func("/pci/cxl/pxb_with_window", cxl_pxb_with_window);
+ qtest_add_func("/pci/cxl/pxb_x2_with_window", cxl_2pxb_with_window);
+ qtest_add_func("/pci/cxl/rp", cxl_root_port);
+ qtest_add_func("/pci/cxl/rp_x2", cxl_2root_port);
+ qtest_add_func("/pci/cxl/type3_device", cxl_t3d);
+ qtest_add_func("/pci/cxl/rp_x2_type3_x2", cxl_1pxb_2rp_2t3d);
+ qtest_add_func("/pci/cxl/pxb_x2_root_port_x4_type3_x4", cxl_2pxb_4rp_4t3d);
+ return g_test_run();
+}
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index 842b1df420..52a7bbe177 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -41,6 +41,9 @@ qtests_pci = \
(config_all_devices.has_key('CONFIG_VGA') ? ['display-vga-test'] : []) + \
(config_all_devices.has_key('CONFIG_IVSHMEM_DEVICE') ? ['ivshmem-test'] : [])
+qtests_cxl = \
+ (config_all_devices.has_key('CONFIG_CXL') ? ['cxl-test'] : [])
+
qtests_i386 = \
(slirp.found() ? ['pxe-test', 'test-netfilter'] : []) + \
(config_host.has_key('CONFIG_POSIX') ? ['test-filter-mirror'] : []) + \
@@ -74,6 +77,7 @@ qtests_i386 = \
slirp.found() ? ['virtio-net-failover'] : []) + \
(unpack_edk2_blobs ? ['bios-tables-test'] : []) + \
qtests_pci + \
+ qtests_cxl + \
['fdc-test',
'ide-test',
'hd-geo-test',
--
2.32.0
next prev parent reply other threads:[~2022-02-02 14:32 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-02 14:09 [PATCH v5 00/43] CXl 2.0 emulation Support Jonathan Cameron
2022-02-02 14:09 ` [PATCH v5 01/43] hw/pci/cxl: Add a CXL component type (interface) Jonathan Cameron
2022-02-02 14:09 ` [PATCH v5 02/43] hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5) Jonathan Cameron
2022-02-02 14:09 ` [PATCH v5 03/43] MAINTAINERS: Add entry for Compute Express Link Emulation Jonathan Cameron
2022-02-02 14:09 ` [PATCH v5 04/43] hw/cxl/device: Introduce a CXL device (8.2.8) Jonathan Cameron
2022-02-02 14:09 ` [PATCH v5 05/43] hw/cxl/device: Implement the CAP array (8.2.8.1-2) Jonathan Cameron
2022-02-02 14:10 ` [PATCH v5 06/43] hw/cxl/device: Implement basic mailbox (8.2.8.4) Jonathan Cameron
2022-02-02 14:10 ` [PATCH v5 07/43] hw/cxl/device: Add memory device utilities Jonathan Cameron
2022-02-02 14:10 ` [PATCH v5 08/43] hw/cxl/device: Add cheap EVENTS implementation (8.2.9.1) Jonathan Cameron
2022-02-02 14:10 ` [PATCH v5 09/43] hw/cxl/device: Timestamp implementation (8.2.9.3) Jonathan Cameron
2022-02-02 14:10 ` [PATCH v5 10/43] hw/cxl/device: Add log commands (8.2.9.4) + CEL Jonathan Cameron
2022-02-02 14:10 ` [PATCH v5 11/43] hw/pxb: Use a type for realizing expanders Jonathan Cameron
2022-02-02 14:10 ` [PATCH v5 12/43] hw/pci/cxl: Create a CXL bus type Jonathan Cameron
2022-02-02 14:10 ` [PATCH v5 13/43] hw/pxb: Allow creation of a CXL PXB (host bridge) Jonathan Cameron
2022-02-02 14:10 ` [PATCH v5 14/43] tests/acpi: allow DSDT.viot table changes Jonathan Cameron
2022-02-02 14:10 ` [PATCH v5 15/43] acpi/pci: Consolidate host bridge setup Jonathan Cameron
2022-02-02 14:10 ` [PATCH v5 16/43] tests/acpi: Add update DSDT.viot Jonathan Cameron
2022-02-04 14:01 ` Michael S. Tsirkin
2022-02-07 15:10 ` Igor Mammedov
2022-02-07 18:19 ` Jonathan Cameron
2022-02-02 14:10 ` [PATCH v5 17/43] cxl: Machine level control on whether CXL support is enabled Jonathan Cameron
2022-02-02 14:10 ` [PATCH v5 18/43] hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142) Jonathan Cameron
2022-02-02 14:10 ` [PATCH v5 19/43] hw/cxl/rp: Add a root port Jonathan Cameron
2022-02-02 14:10 ` [PATCH v5 20/43] hw/cxl/device: Add a memory device (8.2.8.5) Jonathan Cameron
2022-02-11 15:50 ` Ben Widawsky
2022-02-11 16:45 ` Jonathan Cameron
2022-02-11 16:52 ` Ben Widawsky
2022-02-02 14:10 ` [PATCH v5 21/43] hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12) Jonathan Cameron
2022-02-02 14:10 ` [PATCH v5 22/43] acpi/cxl: Add _OSC implementation (9.14.2) Jonathan Cameron
2022-02-02 14:10 ` [PATCH v5 23/43] tests/acpi: allow CEDT table addition Jonathan Cameron
2022-02-02 14:10 ` [PATCH v5 24/43] acpi/cxl: Create the CEDT (9.14.1) Jonathan Cameron
2022-02-02 14:10 ` [PATCH v5 25/43] hw/cxl/device: Add some trivial commands Jonathan Cameron
2022-02-02 14:10 ` [PATCH v5 26/43] hw/cxl/device: Plumb real Label Storage Area (LSA) sizing Jonathan Cameron
2022-02-02 14:10 ` [PATCH v5 27/43] hw/cxl/device: Implement get/set Label Storage Area (LSA) Jonathan Cameron
2022-02-02 14:10 ` [PATCH v5 28/43] hw/cxl/component: Add utils for interleave parameter encoding/decoding Jonathan Cameron
2022-02-02 14:10 ` [PATCH v5 29/43] hw/cxl/host: Add support for CXL Fixed Memory Windows Jonathan Cameron
2022-02-02 14:10 ` [PATCH v5 30/43] acpi/cxl: Introduce CFMWS structures in CEDT Jonathan Cameron
2022-02-02 14:10 ` [PATCH v5 31/43] hw/pci-host/gpex-acpi: Add support for dsdt construction for pxb-cxl Jonathan Cameron
2022-02-02 14:10 ` [PATCH v5 32/43] pci/pcie_port: Add pci_find_port_by_pn() Jonathan Cameron
2022-02-02 14:10 ` [PATCH v5 33/43] CXL/cxl_component: Add cxl_get_hb_cstate() Jonathan Cameron
2022-02-02 14:10 ` [PATCH v5 34/43] mem/cxl_type3: Add read and write functions for associated hostmem Jonathan Cameron
2022-02-02 14:10 ` [PATCH v5 35/43] cxl/cxl-host: Add memops for CFMWS region Jonathan Cameron
2022-02-02 14:10 ` [PATCH v5 36/43] arm/virt: Allow virt/CEDT creation Jonathan Cameron
2022-02-02 14:10 ` [PATCH v5 37/43] hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxl Jonathan Cameron
2022-02-02 14:10 ` [PATCH v5 38/43] RFC: softmmu/memory: Add ops to memory_region_ram_init_from_file Jonathan Cameron
2022-02-02 14:10 ` [PATCH v5 39/43] hw/cxl/component Add a dumb HDM decoder handler Jonathan Cameron
2022-02-02 14:10 ` [PATCH v5 40/43] i386/pc: Enable CXL fixed memory windows Jonathan Cameron
2022-02-02 14:10 ` [PATCH v5 41/43] qtest/acpi: Add reference CEDT tables Jonathan Cameron
2022-02-02 14:10 ` Jonathan Cameron [this message]
2022-02-02 14:10 ` [PATCH v5 43/43] scripts/device-crash-test: Add exception for pxb-cxl Jonathan Cameron
2022-02-04 14:03 ` [PATCH v5 00/43] CXl 2.0 emulation Support Michael S. Tsirkin
2022-02-04 14:27 ` Michael S. Tsirkin
2022-02-04 18:23 ` Jonathan Cameron
2022-02-07 14:20 ` Jonathan Cameron
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