* [PATCH v5 0/8] hw/cxl: RAS error emulation and injection
@ 2023-02-21 15:21 Jonathan Cameron
2023-02-21 15:21 ` [PATCH v5 1/8] hw/pci/aer: Implement PCI_ERR_UNCOR_MASK register Jonathan Cameron
` (7 more replies)
0 siblings, 8 replies; 27+ messages in thread
From: Jonathan Cameron @ 2023-02-21 15:21 UTC (permalink / raw)
To: qemu-devel, Michael Tsirkin
Cc: Ben Widawsky, linux-cxl, linuxarm, Ira Weiny, Gregory Price,
Philippe Mathieu-Daudé,
Mike Maslenkin, Dave Jiang, Markus Armbruster
v5: thanks to Dave Jiang for review.
- Spell out Implementation Defined.
- Pick up Dave's tags - thanks!
v4:
In response to similar feedback on poison injection series (Markus Armbruster).
- More detailed documentation in cxl.json
- Based on tag in format suggested by Markus.
Based on series "[PATCH v4 00/10] hw/cxl: CXL emulation cleanups and minor fixes for upstream"
Based on: Message-Id: 20230206172816.8201-1-Jonathan.Cameron@huawei.com
v3 cover letter.
CXL error reporting is complex. This series only covers the protocol
related errors reported via PCIe AER - Ira Weiny has posted support for
Event log based injection and I will post an update of Poison list injection
shortly. My proposal is to upstream this one first, followed by Ira's Event
Log series, then finally the Poison List handling. That is based on likely
order of Linux kernel support (the support for this type of error reporting
went in during the recent merge window, the others are still under review).
Note we may propose other non error related features in between!
In order to test the kernel support for RAS error handling, I previously
provided this series via gitlab, enabling David Jiang's kernel patches
to be tested.
Now that Linux kernel support is upstream, this series is proposing the
support for upstream inclusion in QEMU. Note that support for Multiple
Header Recording has been added to QEMU the meantime and a kernel
patch to use that feature sent out.
https://lore.kernel.org/linux-cxl/20230113154058.16227-1-Jonathan.Cameron@huawei.com/T/#t
There are two generic PCI AER precursor feature additions.
1) The PCI_ERR_UCOR_MASK register has not been implemented until now
and is necessary for correct emulation.
2) The routing for AER errors, via existing AER error injection, only
covered one of two paths given in the PCIe base specification,
unfortunately not the one used by the Linux kernel CXL support.
The use of MSI for the CXL root ports, both makes sense from the point
of view of how it may well be implemented, and works around the documented
lack of PCI interrupt routing in i386/q35. I have a hack that lets
us correctly route those interrupts but don't currently plan to post it.
The actual CXL error injection uses a new QMP interface as documented
in the final patch description. The existing AER error injection
internals are reused though it's HMP interface is not.
Injection via QMP:
{ "execute": "qmp_capabilities" }
...
{ "execute": "cxl-inject-uncorrectable-errors",
"arguments": {
"path": "/machine/peripheral/cxl-pmem0",
"errors": [
{
"type": "cache-address-parity",
"header": [ 3, 4]
},
{
"type": "cache-data-parity",
"header": [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31]
},
{
"type": "internal",
"header": [ 1, 2, 4]
}
]
}}
...
{ "execute": "cxl-inject-correctable-error",
"arguments": {
"path": "/machine/peripheral/cxl-pmem0",
"type": "physical"
} }
Jonathan Cameron (8):
hw/pci/aer: Implement PCI_ERR_UNCOR_MASK register
hw/pci/aer: Add missing routing for AER errors
hw/pci-bridge/cxl_root_port: Wire up AER
hw/pci-bridge/cxl_root_port: Wire up MSI
hw/mem/cxl-type3: Add AER extended capability
hw/cxl: Fix endian issues in CXL RAS capability defaults / masks
hw/pci/aer: Make PCIE AER error injection facility available for other
emulation to use.
hw/mem/cxl_type3: Add CXL RAS Error Injection Support.
hw/cxl/cxl-component-utils.c | 20 ++-
hw/mem/cxl_type3.c | 294 +++++++++++++++++++++++++++++++++
hw/mem/cxl_type3_stubs.c | 10 ++
hw/mem/meson.build | 2 +
hw/pci-bridge/cxl_root_port.c | 64 +++++++
hw/pci/pci-internal.h | 1 -
hw/pci/pcie_aer.c | 14 +-
include/hw/cxl/cxl_component.h | 26 +++
include/hw/cxl/cxl_device.h | 11 ++
include/hw/pci/pcie_aer.h | 1 +
include/hw/pci/pcie_regs.h | 3 +
qapi/cxl.json | 118 +++++++++++++
qapi/meson.build | 1 +
qapi/qapi-schema.json | 1 +
14 files changed, 555 insertions(+), 11 deletions(-)
create mode 100644 hw/mem/cxl_type3_stubs.c
create mode 100644 qapi/cxl.json
--
2.37.2
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v5 1/8] hw/pci/aer: Implement PCI_ERR_UNCOR_MASK register
2023-02-21 15:21 [PATCH v5 0/8] hw/cxl: RAS error emulation and injection Jonathan Cameron
@ 2023-02-21 15:21 ` Jonathan Cameron
2023-02-21 15:21 ` [PATCH v5 2/8] hw/pci/aer: Add missing routing for AER errors Jonathan Cameron
` (6 subsequent siblings)
7 siblings, 0 replies; 27+ messages in thread
From: Jonathan Cameron @ 2023-02-21 15:21 UTC (permalink / raw)
To: qemu-devel, Michael Tsirkin
Cc: Ben Widawsky, linux-cxl, linuxarm, Ira Weiny, Gregory Price,
Philippe Mathieu-Daudé,
Mike Maslenkin, Dave Jiang, Markus Armbruster
This register in AER should be both writeable and should
have a default value with a couple of the errors masked
including the Uncorrectable Internal Error used by CXL for
it's error reporting.
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
hw/pci/pcie_aer.c | 4 ++++
include/hw/pci/pcie_regs.h | 3 +++
2 files changed, 7 insertions(+)
diff --git a/hw/pci/pcie_aer.c b/hw/pci/pcie_aer.c
index 9a19be44ae..909e027d99 100644
--- a/hw/pci/pcie_aer.c
+++ b/hw/pci/pcie_aer.c
@@ -112,6 +112,10 @@ int pcie_aer_init(PCIDevice *dev, uint8_t cap_ver, uint16_t offset,
pci_set_long(dev->w1cmask + offset + PCI_ERR_UNCOR_STATUS,
PCI_ERR_UNC_SUPPORTED);
+ pci_set_long(dev->config + offset + PCI_ERR_UNCOR_MASK,
+ PCI_ERR_UNC_MASK_DEFAULT);
+ pci_set_long(dev->wmask + offset + PCI_ERR_UNCOR_MASK,
+ PCI_ERR_UNC_SUPPORTED);
pci_set_long(dev->config + offset + PCI_ERR_UNCOR_SEVER,
PCI_ERR_UNC_SEVERITY_DEFAULT);
diff --git a/include/hw/pci/pcie_regs.h b/include/hw/pci/pcie_regs.h
index 963dc2e170..6ec4785448 100644
--- a/include/hw/pci/pcie_regs.h
+++ b/include/hw/pci/pcie_regs.h
@@ -155,6 +155,9 @@ typedef enum PCIExpLinkWidth {
PCI_ERR_UNC_ATOP_EBLOCKED | \
PCI_ERR_UNC_TLP_PRF_BLOCKED)
+#define PCI_ERR_UNC_MASK_DEFAULT (PCI_ERR_UNC_INTN | \
+ PCI_ERR_UNC_TLP_PRF_BLOCKED)
+
#define PCI_ERR_UNC_SEVERITY_DEFAULT (PCI_ERR_UNC_DLP | \
PCI_ERR_UNC_SDN | \
PCI_ERR_UNC_FCP | \
--
2.37.2
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v5 2/8] hw/pci/aer: Add missing routing for AER errors
2023-02-21 15:21 [PATCH v5 0/8] hw/cxl: RAS error emulation and injection Jonathan Cameron
2023-02-21 15:21 ` [PATCH v5 1/8] hw/pci/aer: Implement PCI_ERR_UNCOR_MASK register Jonathan Cameron
@ 2023-02-21 15:21 ` Jonathan Cameron
2023-02-21 15:21 ` [PATCH v5 3/8] hw/pci-bridge/cxl_root_port: Wire up AER Jonathan Cameron
` (5 subsequent siblings)
7 siblings, 0 replies; 27+ messages in thread
From: Jonathan Cameron @ 2023-02-21 15:21 UTC (permalink / raw)
To: qemu-devel, Michael Tsirkin
Cc: Ben Widawsky, linux-cxl, linuxarm, Ira Weiny, Gregory Price,
Philippe Mathieu-Daudé,
Mike Maslenkin, Dave Jiang, Markus Armbruster
PCIe r6.0 Figure 6-3 "Pseudo Logic Diagram for Selected Error Message Control
and Status Bits" includes a right hand branch under "All PCI Express devices"
that allows for messages to be generated or sent onwards without SERR#
being set as long as the appropriate per error class bit in the PCIe
Device Control Register is set.
Implement that branch thus enabling routing of ERR_COR, ERR_NONFATAL
and ERR_FATAL under OSes that set these bits appropriately (e.g. Linux)
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
hw/pci/pcie_aer.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/hw/pci/pcie_aer.c b/hw/pci/pcie_aer.c
index 909e027d99..103667c368 100644
--- a/hw/pci/pcie_aer.c
+++ b/hw/pci/pcie_aer.c
@@ -192,8 +192,16 @@ static void pcie_aer_update_uncor_status(PCIDevice *dev)
static bool
pcie_aer_msg_alldev(PCIDevice *dev, const PCIEAERMsg *msg)
{
+ uint16_t devctl = pci_get_word(dev->config + dev->exp.exp_cap +
+ PCI_EXP_DEVCTL);
if (!(pcie_aer_msg_is_uncor(msg) &&
- (pci_get_word(dev->config + PCI_COMMAND) & PCI_COMMAND_SERR))) {
+ (pci_get_word(dev->config + PCI_COMMAND) & PCI_COMMAND_SERR)) &&
+ !((msg->severity == PCI_ERR_ROOT_CMD_NONFATAL_EN) &&
+ (devctl & PCI_EXP_DEVCTL_NFERE)) &&
+ !((msg->severity == PCI_ERR_ROOT_CMD_COR_EN) &&
+ (devctl & PCI_EXP_DEVCTL_CERE)) &&
+ !((msg->severity == PCI_ERR_ROOT_CMD_FATAL_EN) &&
+ (devctl & PCI_EXP_DEVCTL_FERE))) {
return false;
}
--
2.37.2
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v5 3/8] hw/pci-bridge/cxl_root_port: Wire up AER
2023-02-21 15:21 [PATCH v5 0/8] hw/cxl: RAS error emulation and injection Jonathan Cameron
2023-02-21 15:21 ` [PATCH v5 1/8] hw/pci/aer: Implement PCI_ERR_UNCOR_MASK register Jonathan Cameron
2023-02-21 15:21 ` [PATCH v5 2/8] hw/pci/aer: Add missing routing for AER errors Jonathan Cameron
@ 2023-02-21 15:21 ` Jonathan Cameron
2023-02-21 15:21 ` [PATCH v5 4/8] hw/pci-bridge/cxl_root_port: Wire up MSI Jonathan Cameron
` (4 subsequent siblings)
7 siblings, 0 replies; 27+ messages in thread
From: Jonathan Cameron @ 2023-02-21 15:21 UTC (permalink / raw)
To: qemu-devel, Michael Tsirkin
Cc: Ben Widawsky, linux-cxl, linuxarm, Ira Weiny, Gregory Price,
Philippe Mathieu-Daudé,
Mike Maslenkin, Dave Jiang, Markus Armbruster
We are missing necessary config write handling for AER emulation in
the CXL root port. Add it based on pcie_root_port.c
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
hw/pci-bridge/cxl_root_port.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c
index 6664783974..00195257f7 100644
--- a/hw/pci-bridge/cxl_root_port.c
+++ b/hw/pci-bridge/cxl_root_port.c
@@ -187,12 +187,15 @@ static void cxl_rp_write_config(PCIDevice *d, uint32_t address, uint32_t val,
int len)
{
uint16_t slt_ctl, slt_sta;
+ uint32_t root_cmd =
+ pci_get_long(d->config + d->exp.aer_cap + PCI_ERR_ROOT_COMMAND);
pcie_cap_slot_get(d, &slt_ctl, &slt_sta);
pci_bridge_write_config(d, address, val, len);
pcie_cap_flr_write_config(d, address, val, len);
pcie_cap_slot_write_config(d, slt_ctl, slt_sta, address, val, len);
pcie_aer_write_config(d, address, val, len);
+ pcie_aer_root_write_config(d, address, val, len, root_cmd);
cxl_rp_dvsec_write_config(d, address, val, len);
}
--
2.37.2
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v5 4/8] hw/pci-bridge/cxl_root_port: Wire up MSI
2023-02-21 15:21 [PATCH v5 0/8] hw/cxl: RAS error emulation and injection Jonathan Cameron
` (2 preceding siblings ...)
2023-02-21 15:21 ` [PATCH v5 3/8] hw/pci-bridge/cxl_root_port: Wire up AER Jonathan Cameron
@ 2023-02-21 15:21 ` Jonathan Cameron
2023-02-21 15:21 ` [PATCH v5 5/8] hw/mem/cxl-type3: Add AER extended capability Jonathan Cameron
` (3 subsequent siblings)
7 siblings, 0 replies; 27+ messages in thread
From: Jonathan Cameron @ 2023-02-21 15:21 UTC (permalink / raw)
To: qemu-devel, Michael Tsirkin
Cc: Ben Widawsky, linux-cxl, linuxarm, Ira Weiny, Gregory Price,
Philippe Mathieu-Daudé,
Mike Maslenkin, Dave Jiang, Markus Armbruster
Done to avoid fixing ACPI route description of traditional PCI interrupts on q35
and because we should probably move with the times anyway.
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
hw/pci-bridge/cxl_root_port.c | 61 +++++++++++++++++++++++++++++++++++
1 file changed, 61 insertions(+)
diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c
index 00195257f7..7dfd20aa67 100644
--- a/hw/pci-bridge/cxl_root_port.c
+++ b/hw/pci-bridge/cxl_root_port.c
@@ -22,6 +22,7 @@
#include "qemu/range.h"
#include "hw/pci/pci_bridge.h"
#include "hw/pci/pcie_port.h"
+#include "hw/pci/msi.h"
#include "hw/qdev-properties.h"
#include "hw/sysbus.h"
#include "qapi/error.h"
@@ -29,6 +30,10 @@
#define CXL_ROOT_PORT_DID 0x7075
+#define CXL_RP_MSI_OFFSET 0x60
+#define CXL_RP_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_MASKBIT
+#define CXL_RP_MSI_NR_VECTOR 2
+
/* Copied from the gen root port which we derive */
#define GEN_PCIE_ROOT_PORT_AER_OFFSET 0x100
#define GEN_PCIE_ROOT_PORT_ACS_OFFSET \
@@ -47,6 +52,49 @@ typedef struct CXLRootPort {
#define TYPE_CXL_ROOT_PORT "cxl-rp"
DECLARE_INSTANCE_CHECKER(CXLRootPort, CXL_ROOT_PORT, TYPE_CXL_ROOT_PORT)
+/*
+ * If two MSI vector are allocated, Advanced Error Interrupt Message Number
+ * is 1. otherwise 0.
+ * 17.12.5.10 RPERRSTS, 32:27 bit Advanced Error Interrupt Message Number.
+ */
+static uint8_t cxl_rp_aer_vector(const PCIDevice *d)
+{
+ switch (msi_nr_vectors_allocated(d)) {
+ case 1:
+ return 0;
+ case 2:
+ return 1;
+ case 4:
+ case 8:
+ case 16:
+ case 32:
+ default:
+ break;
+ }
+ abort();
+ return 0;
+}
+
+static int cxl_rp_interrupts_init(PCIDevice *d, Error **errp)
+{
+ int rc;
+
+ rc = msi_init(d, CXL_RP_MSI_OFFSET, CXL_RP_MSI_NR_VECTOR,
+ CXL_RP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
+ CXL_RP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT,
+ errp);
+ if (rc < 0) {
+ assert(rc == -ENOTSUP);
+ }
+
+ return rc;
+}
+
+static void cxl_rp_interrupts_uninit(PCIDevice *d)
+{
+ msi_uninit(d);
+}
+
static void latch_registers(CXLRootPort *crp)
{
uint32_t *reg_state = crp->cxl_cstate.crb.cache_mem_registers;
@@ -183,6 +231,15 @@ static void cxl_rp_dvsec_write_config(PCIDevice *dev, uint32_t addr,
}
}
+static void cxl_rp_aer_vector_update(PCIDevice *d)
+{
+ PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(d);
+
+ if (rpc->aer_vector) {
+ pcie_aer_root_set_vector(d, rpc->aer_vector(d));
+ }
+}
+
static void cxl_rp_write_config(PCIDevice *d, uint32_t address, uint32_t val,
int len)
{
@@ -192,6 +249,7 @@ static void cxl_rp_write_config(PCIDevice *d, uint32_t address, uint32_t val,
pcie_cap_slot_get(d, &slt_ctl, &slt_sta);
pci_bridge_write_config(d, address, val, len);
+ cxl_rp_aer_vector_update(d);
pcie_cap_flr_write_config(d, address, val, len);
pcie_cap_slot_write_config(d, slt_ctl, slt_sta, address, val, len);
pcie_aer_write_config(d, address, val, len);
@@ -220,6 +278,9 @@ static void cxl_root_port_class_init(ObjectClass *oc, void *data)
rpc->aer_offset = GEN_PCIE_ROOT_PORT_AER_OFFSET;
rpc->acs_offset = GEN_PCIE_ROOT_PORT_ACS_OFFSET;
+ rpc->aer_vector = cxl_rp_aer_vector;
+ rpc->interrupts_init = cxl_rp_interrupts_init;
+ rpc->interrupts_uninit = cxl_rp_interrupts_uninit;
dc->hotpluggable = false;
}
--
2.37.2
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v5 5/8] hw/mem/cxl-type3: Add AER extended capability
2023-02-21 15:21 [PATCH v5 0/8] hw/cxl: RAS error emulation and injection Jonathan Cameron
` (3 preceding siblings ...)
2023-02-21 15:21 ` [PATCH v5 4/8] hw/pci-bridge/cxl_root_port: Wire up MSI Jonathan Cameron
@ 2023-02-21 15:21 ` Jonathan Cameron
2023-02-21 15:21 ` [PATCH v5 6/8] hw/cxl: Fix endian issues in CXL RAS capability defaults / masks Jonathan Cameron
` (2 subsequent siblings)
7 siblings, 0 replies; 27+ messages in thread
From: Jonathan Cameron @ 2023-02-21 15:21 UTC (permalink / raw)
To: qemu-devel, Michael Tsirkin
Cc: Ben Widawsky, linux-cxl, linuxarm, Ira Weiny, Gregory Price,
Philippe Mathieu-Daudé,
Mike Maslenkin, Dave Jiang, Markus Armbruster
This enables AER error injection to function as expected.
It is intended as a building block in enabling CXL RAS error injection
in the following patches.
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
hw/mem/cxl_type3.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index 217a5e639b..6cdd988d1d 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -250,6 +250,7 @@ static void ct3d_config_write(PCIDevice *pci_dev, uint32_t addr, uint32_t val,
pcie_doe_write_config(&ct3d->doe_cdat, addr, val, size);
pci_default_write_config(pci_dev, addr, val, size);
+ pcie_aer_write_config(pci_dev, addr, val, size);
}
/*
@@ -452,8 +453,19 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp)
cxl_cstate->cdat.free_cdat_table = ct3_free_cdat_table;
cxl_cstate->cdat.private = ct3d;
cxl_doe_cdat_init(cxl_cstate, errp);
+
+ pcie_cap_deverr_init(pci_dev);
+ /* Leave a bit of room for expansion */
+ rc = pcie_aer_init(pci_dev, PCI_ERR_VER, 0x200, PCI_ERR_SIZEOF, NULL);
+ if (rc) {
+ goto err_release_cdat;
+ }
+
return;
+err_release_cdat:
+ cxl_doe_cdat_release(cxl_cstate);
+ g_free(regs->special_ops);
err_address_space_free:
address_space_destroy(&ct3d->hostmem_as);
return;
@@ -465,6 +477,7 @@ static void ct3_exit(PCIDevice *pci_dev)
CXLComponentState *cxl_cstate = &ct3d->cxl_cstate;
ComponentRegisters *regs = &cxl_cstate->crb;
+ pcie_aer_exit(pci_dev);
cxl_doe_cdat_release(cxl_cstate);
g_free(regs->special_ops);
address_space_destroy(&ct3d->hostmem_as);
--
2.37.2
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v5 6/8] hw/cxl: Fix endian issues in CXL RAS capability defaults / masks
2023-02-21 15:21 [PATCH v5 0/8] hw/cxl: RAS error emulation and injection Jonathan Cameron
` (4 preceding siblings ...)
2023-02-21 15:21 ` [PATCH v5 5/8] hw/mem/cxl-type3: Add AER extended capability Jonathan Cameron
@ 2023-02-21 15:21 ` Jonathan Cameron
2023-02-21 22:06 ` Philippe Mathieu-Daudé
2023-02-21 15:21 ` [PATCH v5 7/8] hw/pci/aer: Make PCIE AER error injection facility available for other emulation to use Jonathan Cameron
2023-02-21 15:21 ` [PATCH v5 8/8] hw/mem/cxl_type3: Add CXL RAS Error Injection Support Jonathan Cameron
7 siblings, 1 reply; 27+ messages in thread
From: Jonathan Cameron @ 2023-02-21 15:21 UTC (permalink / raw)
To: qemu-devel, Michael Tsirkin
Cc: Ben Widawsky, linux-cxl, linuxarm, Ira Weiny, Gregory Price,
Philippe Mathieu-Daudé,
Mike Maslenkin, Dave Jiang, Markus Armbruster
As these are about to be modified, fix the endian handle for
this set of registers rather than making it worse.
Note that CXL is currently only supported in QEMU on
x86 (arm64 patches out of tree) so we aren't going to yet hit
an problems with big endian. However it is good to avoid making
things worse for that support in the future.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
---
hw/cxl/cxl-component-utils.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c
index 3edd303a33..737b4764b9 100644
--- a/hw/cxl/cxl-component-utils.c
+++ b/hw/cxl/cxl-component-utils.c
@@ -141,17 +141,17 @@ static void ras_init_common(uint32_t *reg_state, uint32_t *write_msk)
* Error status is RW1C but given bits are not yet set, it can
* be handled as RO.
*/
- reg_state[R_CXL_RAS_UNC_ERR_STATUS] = 0;
+ stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_STATUS, 0);
/* Bits 12-13 and 17-31 reserved in CXL 2.0 */
- reg_state[R_CXL_RAS_UNC_ERR_MASK] = 0x1cfff;
- write_msk[R_CXL_RAS_UNC_ERR_MASK] = 0x1cfff;
- reg_state[R_CXL_RAS_UNC_ERR_SEVERITY] = 0x1cfff;
- write_msk[R_CXL_RAS_UNC_ERR_SEVERITY] = 0x1cfff;
- reg_state[R_CXL_RAS_COR_ERR_STATUS] = 0;
- reg_state[R_CXL_RAS_COR_ERR_MASK] = 0x7f;
- write_msk[R_CXL_RAS_COR_ERR_MASK] = 0x7f;
+ stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_MASK, 0x1cfff);
+ stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_MASK, 0x1cfff);
+ stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_SEVERITY, 0x1cfff);
+ stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_SEVERITY, 0x1cfff);
+ stl_le_p(reg_state + R_CXL_RAS_COR_ERR_STATUS, 0);
+ stl_le_p(reg_state + R_CXL_RAS_COR_ERR_MASK, 0x7f);
+ stl_le_p(write_msk + R_CXL_RAS_COR_ERR_MASK, 0x7f);
/* CXL switches and devices must set */
- reg_state[R_CXL_RAS_ERR_CAP_CTRL] = 0x00;
+ stl_le_p(reg_state + R_CXL_RAS_ERR_CAP_CTRL, 0x00);
}
static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk,
--
2.37.2
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v5 7/8] hw/pci/aer: Make PCIE AER error injection facility available for other emulation to use.
2023-02-21 15:21 [PATCH v5 0/8] hw/cxl: RAS error emulation and injection Jonathan Cameron
` (5 preceding siblings ...)
2023-02-21 15:21 ` [PATCH v5 6/8] hw/cxl: Fix endian issues in CXL RAS capability defaults / masks Jonathan Cameron
@ 2023-02-21 15:21 ` Jonathan Cameron
2023-02-21 22:08 ` Philippe Mathieu-Daudé
2023-02-21 15:21 ` [PATCH v5 8/8] hw/mem/cxl_type3: Add CXL RAS Error Injection Support Jonathan Cameron
7 siblings, 1 reply; 27+ messages in thread
From: Jonathan Cameron @ 2023-02-21 15:21 UTC (permalink / raw)
To: qemu-devel, Michael Tsirkin
Cc: Ben Widawsky, linux-cxl, linuxarm, Ira Weiny, Gregory Price,
Philippe Mathieu-Daudé,
Mike Maslenkin, Dave Jiang, Markus Armbruster
This infrastructure will be reused for CXL RAS error injection
in patches that follow.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
---
hw/pci/pci-internal.h | 1 -
include/hw/pci/pcie_aer.h | 1 +
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/pci/pci-internal.h b/hw/pci/pci-internal.h
index 2ea356bdf5..a7d6d8a732 100644
--- a/hw/pci/pci-internal.h
+++ b/hw/pci/pci-internal.h
@@ -20,6 +20,5 @@ void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
int pcie_aer_parse_error_string(const char *error_name,
uint32_t *status, bool *correctable);
-int pcie_aer_inject_error(PCIDevice *dev, const PCIEAERErr *err);
#endif
diff --git a/include/hw/pci/pcie_aer.h b/include/hw/pci/pcie_aer.h
index 65e71d98fe..1234fdc4e2 100644
--- a/include/hw/pci/pcie_aer.h
+++ b/include/hw/pci/pcie_aer.h
@@ -100,4 +100,5 @@ void pcie_aer_root_write_config(PCIDevice *dev,
uint32_t addr, uint32_t val, int len,
uint32_t root_cmd_prev);
+int pcie_aer_inject_error(PCIDevice *dev, const PCIEAERErr *err);
#endif /* QEMU_PCIE_AER_H */
--
2.37.2
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v5 8/8] hw/mem/cxl_type3: Add CXL RAS Error Injection Support.
2023-02-21 15:21 [PATCH v5 0/8] hw/cxl: RAS error emulation and injection Jonathan Cameron
` (6 preceding siblings ...)
2023-02-21 15:21 ` [PATCH v5 7/8] hw/pci/aer: Make PCIE AER error injection facility available for other emulation to use Jonathan Cameron
@ 2023-02-21 15:21 ` Jonathan Cameron
2023-02-21 15:48 ` Dave Jiang
` (2 more replies)
7 siblings, 3 replies; 27+ messages in thread
From: Jonathan Cameron @ 2023-02-21 15:21 UTC (permalink / raw)
To: qemu-devel, Michael Tsirkin
Cc: Ben Widawsky, linux-cxl, linuxarm, Ira Weiny, Gregory Price,
Philippe Mathieu-Daudé,
Mike Maslenkin, Dave Jiang, Markus Armbruster
CXL uses PCI AER Internal errors to signal to the host that an error has
occurred. The host can then read more detailed status from the CXL RAS
capability.
For uncorrectable errors: support multiple injection in one operation
as this is needed to reliably test multiple header logging support in an
OS. The equivalent feature doesn't exist for correctable errors, so only
one error need be injected at a time.
Note:
- Header content needs to be manually specified in a fashion that
matches the specification for what can be in the header for each
error type.
Injection via QMP:
{ "execute": "qmp_capabilities" }
...
{ "execute": "cxl-inject-uncorrectable-errors",
"arguments": {
"path": "/machine/peripheral/cxl-pmem0",
"errors": [
{
"type": "cache-address-parity",
"header": [ 3, 4]
},
{
"type": "cache-data-parity",
"header": [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31]
},
{
"type": "internal",
"header": [ 1, 2, 4]
}
]
}}
...
{ "execute": "cxl-inject-correctable-error",
"arguments": {
"path": "/machine/peripheral/cxl-pmem0",
"type": "physical"
} }
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
v5: (Thanks to Dave Jiang for review)
- Spell out Implementation Defined (previously typo as Imdef which did
not help)
v4:
- Improved QMP help text wth more detail (following request in review
of the Poison injection series)
---
hw/cxl/cxl-component-utils.c | 4 +-
hw/mem/cxl_type3.c | 281 +++++++++++++++++++++++++++++++++
hw/mem/cxl_type3_stubs.c | 10 ++
hw/mem/meson.build | 2 +
include/hw/cxl/cxl_component.h | 26 +++
include/hw/cxl/cxl_device.h | 11 ++
qapi/cxl.json | 118 ++++++++++++++
qapi/meson.build | 1 +
qapi/qapi-schema.json | 1 +
9 files changed, 453 insertions(+), 1 deletion(-)
diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c
index 737b4764b9..b665d4f565 100644
--- a/hw/cxl/cxl-component-utils.c
+++ b/hw/cxl/cxl-component-utils.c
@@ -142,16 +142,18 @@ static void ras_init_common(uint32_t *reg_state, uint32_t *write_msk)
* be handled as RO.
*/
stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_STATUS, 0);
+ stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_STATUS, 0x1cfff);
/* Bits 12-13 and 17-31 reserved in CXL 2.0 */
stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_MASK, 0x1cfff);
stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_MASK, 0x1cfff);
stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_SEVERITY, 0x1cfff);
stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_SEVERITY, 0x1cfff);
stl_le_p(reg_state + R_CXL_RAS_COR_ERR_STATUS, 0);
+ stl_le_p(write_msk + R_CXL_RAS_COR_ERR_STATUS, 0x7f);
stl_le_p(reg_state + R_CXL_RAS_COR_ERR_MASK, 0x7f);
stl_le_p(write_msk + R_CXL_RAS_COR_ERR_MASK, 0x7f);
/* CXL switches and devices must set */
- stl_le_p(reg_state + R_CXL_RAS_ERR_CAP_CTRL, 0x00);
+ stl_le_p(reg_state + R_CXL_RAS_ERR_CAP_CTRL, 0x200);
}
static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk,
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index 6cdd988d1d..abe60b362c 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -1,6 +1,7 @@
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu/error-report.h"
+#include "qapi/qapi-commands-cxl.h"
#include "hw/mem/memory-device.h"
#include "hw/mem/pc-dimm.h"
#include "hw/pci/pci.h"
@@ -323,6 +324,66 @@ static void hdm_decoder_commit(CXLType3Dev *ct3d, int which)
ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, COMMITTED, 1);
}
+static int ct3d_qmp_uncor_err_to_cxl(CxlUncorErrorType qmp_err)
+{
+ switch (qmp_err) {
+ case CXL_UNCOR_ERROR_TYPE_CACHE_DATA_PARITY:
+ return CXL_RAS_UNC_ERR_CACHE_DATA_PARITY;
+ case CXL_UNCOR_ERROR_TYPE_CACHE_ADDRESS_PARITY:
+ return CXL_RAS_UNC_ERR_CACHE_ADDRESS_PARITY;
+ case CXL_UNCOR_ERROR_TYPE_CACHE_BE_PARITY:
+ return CXL_RAS_UNC_ERR_CACHE_BE_PARITY;
+ case CXL_UNCOR_ERROR_TYPE_CACHE_DATA_ECC:
+ return CXL_RAS_UNC_ERR_CACHE_DATA_ECC;
+ case CXL_UNCOR_ERROR_TYPE_MEM_DATA_PARITY:
+ return CXL_RAS_UNC_ERR_MEM_DATA_PARITY;
+ case CXL_UNCOR_ERROR_TYPE_MEM_ADDRESS_PARITY:
+ return CXL_RAS_UNC_ERR_MEM_ADDRESS_PARITY;
+ case CXL_UNCOR_ERROR_TYPE_MEM_BE_PARITY:
+ return CXL_RAS_UNC_ERR_MEM_BE_PARITY;
+ case CXL_UNCOR_ERROR_TYPE_MEM_DATA_ECC:
+ return CXL_RAS_UNC_ERR_MEM_DATA_ECC;
+ case CXL_UNCOR_ERROR_TYPE_REINIT_THRESHOLD:
+ return CXL_RAS_UNC_ERR_REINIT_THRESHOLD;
+ case CXL_UNCOR_ERROR_TYPE_RSVD_ENCODING:
+ return CXL_RAS_UNC_ERR_RSVD_ENCODING;
+ case CXL_UNCOR_ERROR_TYPE_POISON_RECEIVED:
+ return CXL_RAS_UNC_ERR_POISON_RECEIVED;
+ case CXL_UNCOR_ERROR_TYPE_RECEIVER_OVERFLOW:
+ return CXL_RAS_UNC_ERR_RECEIVER_OVERFLOW;
+ case CXL_UNCOR_ERROR_TYPE_INTERNAL:
+ return CXL_RAS_UNC_ERR_INTERNAL;
+ case CXL_UNCOR_ERROR_TYPE_CXL_IDE_TX:
+ return CXL_RAS_UNC_ERR_CXL_IDE_TX;
+ case CXL_UNCOR_ERROR_TYPE_CXL_IDE_RX:
+ return CXL_RAS_UNC_ERR_CXL_IDE_RX;
+ default:
+ return -EINVAL;
+ }
+}
+
+static int ct3d_qmp_cor_err_to_cxl(CxlCorErrorType qmp_err)
+{
+ switch (qmp_err) {
+ case CXL_COR_ERROR_TYPE_CACHE_DATA_ECC:
+ return CXL_RAS_COR_ERR_CACHE_DATA_ECC;
+ case CXL_COR_ERROR_TYPE_MEM_DATA_ECC:
+ return CXL_RAS_COR_ERR_MEM_DATA_ECC;
+ case CXL_COR_ERROR_TYPE_CRC_THRESHOLD:
+ return CXL_RAS_COR_ERR_CRC_THRESHOLD;
+ case CXL_COR_ERROR_TYPE_RETRY_THRESHOLD:
+ return CXL_RAS_COR_ERR_RETRY_THRESHOLD;
+ case CXL_COR_ERROR_TYPE_CACHE_POISON_RECEIVED:
+ return CXL_RAS_COR_ERR_CACHE_POISON_RECEIVED;
+ case CXL_COR_ERROR_TYPE_MEM_POISON_RECEIVED:
+ return CXL_RAS_COR_ERR_MEM_POISON_RECEIVED;
+ case CXL_COR_ERROR_TYPE_PHYSICAL:
+ return CXL_RAS_COR_ERR_PHYSICAL;
+ default:
+ return -EINVAL;
+ }
+}
+
static void ct3d_reg_write(void *opaque, hwaddr offset, uint64_t value,
unsigned size)
{
@@ -341,6 +402,83 @@ static void ct3d_reg_write(void *opaque, hwaddr offset, uint64_t value,
should_commit = FIELD_EX32(value, CXL_HDM_DECODER0_CTRL, COMMIT);
which_hdm = 0;
break;
+ case A_CXL_RAS_UNC_ERR_STATUS:
+ {
+ uint32_t capctrl = ldl_le_p(cache_mem + R_CXL_RAS_ERR_CAP_CTRL);
+ uint32_t fe = FIELD_EX32(capctrl, CXL_RAS_ERR_CAP_CTRL, FIRST_ERROR_POINTER);
+ CXLError *cxl_err;
+ uint32_t unc_err;
+
+ /*
+ * If single bit written that corresponds to the first error
+ * pointer being cleared, update the status and header log.
+ */
+ if (!QTAILQ_EMPTY(&ct3d->error_list)) {
+ if ((1 << fe) ^ value) {
+ CXLError *cxl_next;
+ /*
+ * Software is using wrong flow for multiple header recording
+ * Following behavior in PCIe r6.0 and assuming multiple
+ * header support. Implementation defined choice to clear all
+ * matching records if more than one bit set - which corresponds
+ * closest to behavior of hardware not capable of multiple
+ * header recording.
+ */
+ QTAILQ_FOREACH_SAFE(cxl_err, &ct3d->error_list, node, cxl_next) {
+ if ((1 << cxl_err->type) & value) {
+ QTAILQ_REMOVE(&ct3d->error_list, cxl_err, node);
+ g_free(cxl_err);
+ }
+ }
+ } else {
+ /* Done with previous FE, so drop from list */
+ cxl_err = QTAILQ_FIRST(&ct3d->error_list);
+ QTAILQ_REMOVE(&ct3d->error_list, cxl_err, node);
+ g_free(cxl_err);
+ }
+
+ /*
+ * If there is another FE, then put that in place and update
+ * the header log
+ */
+ if (!QTAILQ_EMPTY(&ct3d->error_list)) {
+ uint32_t *header_log = &cache_mem[R_CXL_RAS_ERR_HEADER0];
+ int i;
+
+ cxl_err = QTAILQ_FIRST(&ct3d->error_list);
+ for (i = 0; i < CXL_RAS_ERR_HEADER_NUM; i++) {
+ stl_le_p(header_log + i, cxl_err->header[i]);
+ }
+ capctrl = FIELD_DP32(capctrl, CXL_RAS_ERR_CAP_CTRL,
+ FIRST_ERROR_POINTER, cxl_err->type);
+ } else {
+ /*
+ * If no more errors, then follow recomendation of PCI spec
+ * r6.0 6.2.4.2 to set the first error pointer to a status
+ * bit that will never be used.
+ */
+ capctrl = FIELD_DP32(capctrl, CXL_RAS_ERR_CAP_CTRL,
+ FIRST_ERROR_POINTER,
+ CXL_RAS_UNC_ERR_CXL_UNUSED);
+ }
+ stl_le_p((uint8_t *)cache_mem + A_CXL_RAS_ERR_CAP_CTRL, capctrl);
+ }
+ unc_err = 0;
+ QTAILQ_FOREACH(cxl_err, &ct3d->error_list, node) {
+ unc_err |= 1 << cxl_err->type;
+ }
+ stl_le_p((uint8_t *)cache_mem + offset, unc_err);
+
+ return;
+ }
+ case A_CXL_RAS_COR_ERR_STATUS:
+ {
+ uint32_t rw1c = value;
+ uint32_t temp = ldl_le_p((uint8_t *)cache_mem + offset);
+ temp &= ~rw1c;
+ stl_le_p((uint8_t *)cache_mem + offset, temp);
+ return;
+ }
default:
break;
}
@@ -404,6 +542,8 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp)
unsigned short msix_num = 1;
int i, rc;
+ QTAILQ_INIT(&ct3d->error_list);
+
if (!cxl_setup_memory(ct3d, errp)) {
return;
}
@@ -631,6 +771,147 @@ static void set_lsa(CXLType3Dev *ct3d, const void *buf, uint64_t size,
*/
}
+/* For uncorrectable errors include support for multiple header recording */
+void qmp_cxl_inject_uncorrectable_errors(const char *path,
+ CXLUncorErrorRecordList *errors,
+ Error **errp)
+{
+ Object *obj = object_resolve_path(path, NULL);
+ static PCIEAERErr err = {};
+ CXLType3Dev *ct3d;
+ CXLError *cxl_err;
+ uint32_t *reg_state;
+ uint32_t unc_err;
+ bool first;
+
+ if (!obj) {
+ error_setg(errp, "Unable to resolve path");
+ return;
+ }
+
+ if (!object_dynamic_cast(obj, TYPE_CXL_TYPE3)) {
+ error_setg(errp, "Path does not point to a CXL type 3 device");
+ return;
+ }
+
+ err.status = PCI_ERR_UNC_INTN;
+ err.source_id = pci_requester_id(PCI_DEVICE(obj));
+ err.flags = 0;
+
+ ct3d = CXL_TYPE3(obj);
+
+ first = QTAILQ_EMPTY(&ct3d->error_list);
+ reg_state = ct3d->cxl_cstate.crb.cache_mem_registers;
+ while (errors) {
+ uint32List *header = errors->value->header;
+ uint8_t header_count = 0;
+ int cxl_err_code;
+
+ cxl_err_code = ct3d_qmp_uncor_err_to_cxl(errors->value->type);
+ if (cxl_err_code < 0) {
+ error_setg(errp, "Unknown error code");
+ return;
+ }
+
+ /* If the error is masked, nothing to do here */
+ if (!((1 << cxl_err_code) &
+ ~ldl_le_p(reg_state + R_CXL_RAS_UNC_ERR_MASK))) {
+ errors = errors->next;
+ continue;
+ }
+
+ cxl_err = g_malloc0(sizeof(*cxl_err));
+ if (!cxl_err) {
+ return;
+ }
+
+ cxl_err->type = cxl_err_code;
+ while (header && header_count < 32) {
+ cxl_err->header[header_count++] = header->value;
+ header = header->next;
+ }
+ if (header_count > 32) {
+ error_setg(errp, "Header must be 32 DWORD or less");
+ return;
+ }
+ QTAILQ_INSERT_TAIL(&ct3d->error_list, cxl_err, node);
+
+ errors = errors->next;
+ }
+
+ if (first && !QTAILQ_EMPTY(&ct3d->error_list)) {
+ uint32_t *cache_mem = ct3d->cxl_cstate.crb.cache_mem_registers;
+ uint32_t capctrl = ldl_le_p(cache_mem + R_CXL_RAS_ERR_CAP_CTRL);
+ uint32_t *header_log = &cache_mem[R_CXL_RAS_ERR_HEADER0];
+ int i;
+
+ cxl_err = QTAILQ_FIRST(&ct3d->error_list);
+ for (i = 0; i < CXL_RAS_ERR_HEADER_NUM; i++) {
+ stl_le_p(header_log + i, cxl_err->header[i]);
+ }
+
+ capctrl = FIELD_DP32(capctrl, CXL_RAS_ERR_CAP_CTRL,
+ FIRST_ERROR_POINTER, cxl_err->type);
+ stl_le_p(cache_mem + R_CXL_RAS_ERR_CAP_CTRL, capctrl);
+ }
+
+ unc_err = 0;
+ QTAILQ_FOREACH(cxl_err, &ct3d->error_list, node) {
+ unc_err |= (1 << cxl_err->type);
+ }
+ if (!unc_err) {
+ return;
+ }
+
+ stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_STATUS, unc_err);
+ pcie_aer_inject_error(PCI_DEVICE(obj), &err);
+
+ return;
+}
+
+void qmp_cxl_inject_correctable_error(const char *path, CxlCorErrorType type,
+ Error **errp)
+{
+ static PCIEAERErr err = {};
+ Object *obj = object_resolve_path(path, NULL);
+ CXLType3Dev *ct3d;
+ uint32_t *reg_state;
+ uint32_t cor_err;
+ int cxl_err_type;
+
+ if (!obj) {
+ error_setg(errp, "Unable to resolve path");
+ return;
+ }
+ if (!object_dynamic_cast(obj, TYPE_CXL_TYPE3)) {
+ error_setg(errp, "Path does not point to a CXL type 3 device");
+ return;
+ }
+
+ err.status = PCI_ERR_COR_INTERNAL;
+ err.source_id = pci_requester_id(PCI_DEVICE(obj));
+ err.flags = PCIE_AER_ERR_IS_CORRECTABLE;
+
+ ct3d = CXL_TYPE3(obj);
+ reg_state = ct3d->cxl_cstate.crb.cache_mem_registers;
+ cor_err = ldl_le_p(reg_state + R_CXL_RAS_COR_ERR_STATUS);
+
+ cxl_err_type = ct3d_qmp_cor_err_to_cxl(type);
+ if (cxl_err_type < 0) {
+ error_setg(errp, "Invalid COR error");
+ return;
+ }
+ /* If the error is masked, nothting to do here */
+ if (!((1 << cxl_err_type) & ~ldl_le_p(reg_state + R_CXL_RAS_COR_ERR_MASK))) {
+ return;
+ }
+
+ cor_err |= (1 << cxl_err_type);
+ stl_le_p(reg_state + R_CXL_RAS_COR_ERR_STATUS, cor_err);
+
+ pcie_aer_inject_error(PCI_DEVICE(obj), &err);
+}
+
static void ct3_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
diff --git a/hw/mem/cxl_type3_stubs.c b/hw/mem/cxl_type3_stubs.c
new file mode 100644
index 0000000000..b6b51ced54
--- /dev/null
+++ b/hw/mem/cxl_type3_stubs.c
@@ -0,0 +1,10 @@
+
+#include "qemu/osdep.h"
+#include "qapi/qapi-commands-cxl.h"
+
+void qmp_cxl_inject_uncorrectable_errors(const char *path,
+ CXLUncorErrorRecordList *errors,
+ Error **errp) {}
+
+void qmp_cxl_inject_correctable_error(const char *path, CxlCorErrorType type,
+ Error **errp) {}
diff --git a/hw/mem/meson.build b/hw/mem/meson.build
index 609b2b36fc..56c2618b84 100644
--- a/hw/mem/meson.build
+++ b/hw/mem/meson.build
@@ -4,6 +4,8 @@ mem_ss.add(when: 'CONFIG_DIMM', if_true: files('pc-dimm.c'))
mem_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_mc.c'))
mem_ss.add(when: 'CONFIG_NVDIMM', if_true: files('nvdimm.c'))
mem_ss.add(when: 'CONFIG_CXL_MEM_DEVICE', if_true: files('cxl_type3.c'))
+softmmu_ss.add(when: 'CONFIG_CXL_MEM_DEVICE', if_false: files('cxl_type3_stubs.c'))
+softmmu_ss.add(when: 'CONFIG_ALL', if_true: files('cxl_type3_stubs.c'))
softmmu_ss.add_all(when: 'CONFIG_MEM_DEVICE', if_true: mem_ss)
diff --git a/include/hw/cxl/cxl_component.h b/include/hw/cxl/cxl_component.h
index 692d7a5507..ec4203b83f 100644
--- a/include/hw/cxl/cxl_component.h
+++ b/include/hw/cxl/cxl_component.h
@@ -65,11 +65,37 @@ CXLx_CAPABILITY_HEADER(SNOOP, 0x14)
#define CXL_RAS_REGISTERS_OFFSET 0x80
#define CXL_RAS_REGISTERS_SIZE 0x58
REG32(CXL_RAS_UNC_ERR_STATUS, CXL_RAS_REGISTERS_OFFSET)
+#define CXL_RAS_UNC_ERR_CACHE_DATA_PARITY 0
+#define CXL_RAS_UNC_ERR_CACHE_ADDRESS_PARITY 1
+#define CXL_RAS_UNC_ERR_CACHE_BE_PARITY 2
+#define CXL_RAS_UNC_ERR_CACHE_DATA_ECC 3
+#define CXL_RAS_UNC_ERR_MEM_DATA_PARITY 4
+#define CXL_RAS_UNC_ERR_MEM_ADDRESS_PARITY 5
+#define CXL_RAS_UNC_ERR_MEM_BE_PARITY 6
+#define CXL_RAS_UNC_ERR_MEM_DATA_ECC 7
+#define CXL_RAS_UNC_ERR_REINIT_THRESHOLD 8
+#define CXL_RAS_UNC_ERR_RSVD_ENCODING 9
+#define CXL_RAS_UNC_ERR_POISON_RECEIVED 10
+#define CXL_RAS_UNC_ERR_RECEIVER_OVERFLOW 11
+#define CXL_RAS_UNC_ERR_INTERNAL 14
+#define CXL_RAS_UNC_ERR_CXL_IDE_TX 15
+#define CXL_RAS_UNC_ERR_CXL_IDE_RX 16
+#define CXL_RAS_UNC_ERR_CXL_UNUSED 63 /* Magic value */
REG32(CXL_RAS_UNC_ERR_MASK, CXL_RAS_REGISTERS_OFFSET + 0x4)
REG32(CXL_RAS_UNC_ERR_SEVERITY, CXL_RAS_REGISTERS_OFFSET + 0x8)
REG32(CXL_RAS_COR_ERR_STATUS, CXL_RAS_REGISTERS_OFFSET + 0xc)
+#define CXL_RAS_COR_ERR_CACHE_DATA_ECC 0
+#define CXL_RAS_COR_ERR_MEM_DATA_ECC 1
+#define CXL_RAS_COR_ERR_CRC_THRESHOLD 2
+#define CXL_RAS_COR_ERR_RETRY_THRESHOLD 3
+#define CXL_RAS_COR_ERR_CACHE_POISON_RECEIVED 4
+#define CXL_RAS_COR_ERR_MEM_POISON_RECEIVED 5
+#define CXL_RAS_COR_ERR_PHYSICAL 6
REG32(CXL_RAS_COR_ERR_MASK, CXL_RAS_REGISTERS_OFFSET + 0x10)
REG32(CXL_RAS_ERR_CAP_CTRL, CXL_RAS_REGISTERS_OFFSET + 0x14)
+ FIELD(CXL_RAS_ERR_CAP_CTRL, FIRST_ERROR_POINTER, 0, 6)
+REG32(CXL_RAS_ERR_HEADER0, CXL_RAS_REGISTERS_OFFSET + 0x18)
+#define CXL_RAS_ERR_HEADER_NUM 32
/* Offset 0x18 - 0x58 reserved for RAS logs */
/* 8.2.5.10 - CXL Security Capability Structure */
diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
index 7e5ad65c1d..d589f78202 100644
--- a/include/hw/cxl/cxl_device.h
+++ b/include/hw/cxl/cxl_device.h
@@ -232,6 +232,14 @@ REG64(CXL_MEM_DEV_STS, 0)
FIELD(CXL_MEM_DEV_STS, MBOX_READY, 4, 1)
FIELD(CXL_MEM_DEV_STS, RESET_NEEDED, 5, 3)
+typedef struct CXLError {
+ QTAILQ_ENTRY(CXLError) node;
+ int type; /* Error code as per FE definition */
+ uint32_t header[32];
+} CXLError;
+
+typedef QTAILQ_HEAD(, CXLError) CXLErrorList;
+
struct CXLType3Dev {
/* Private */
PCIDevice parent_obj;
@@ -248,6 +256,9 @@ struct CXLType3Dev {
/* DOE */
DOECap doe_cdat;
+
+ /* Error injection */
+ CXLErrorList error_list;
};
#define TYPE_CXL_TYPE3 "cxl-type3"
diff --git a/qapi/cxl.json b/qapi/cxl.json
new file mode 100644
index 0000000000..ac7e167fa2
--- /dev/null
+++ b/qapi/cxl.json
@@ -0,0 +1,118 @@
+# -*- Mode: Python -*-
+# vim: filetype=python
+
+##
+# = CXL devices
+##
+
+##
+# @CxlUncorErrorType:
+#
+# Type of uncorrectable CXL error to inject. These errors are reported via
+# an AER uncorrectable internal error with additional information logged at
+# the CXL device.
+#
+# @cache-data-parity: Data error such as data parity or data ECC error CXL.cache
+# @cache-address-parity: Address parity or other errors associated with the
+# address field on CXL.cache
+# @cache-be-parity: Byte enable parity or other byte enable errors on CXL.cache
+# @cache-data-ecc: ECC error on CXL.cache
+# @mem-data-parity: Data error such as data parity or data ECC error on CXL.mem
+# @mem-address-parity: Address parity or other errors associated with the
+# address field on CXL.mem
+# @mem-be-parity: Byte enable parity or other byte enable errors on CXL.mem.
+# @mem-data-ecc: Data ECC error on CXL.mem.
+# @reinit-threshold: REINIT threshold hit.
+# @rsvd-encoding: Received unrecognized encoding.
+# @poison-received: Received poison from the peer.
+# @receiver-overflow: Buffer overflows (first 3 bits of header log indicate which)
+# @internal: Component specific error
+# @cxl-ide-tx: Integrity and data encryption tx error.
+# @cxl-ide-rx: Integrity and data encryption rx error.
+##
+
+{ 'enum': 'CxlUncorErrorType',
+ 'data': ['cache-data-parity',
+ 'cache-address-parity',
+ 'cache-be-parity',
+ 'cache-data-ecc',
+ 'mem-data-parity',
+ 'mem-address-parity',
+ 'mem-be-parity',
+ 'mem-data-ecc',
+ 'reinit-threshold',
+ 'rsvd-encoding',
+ 'poison-received',
+ 'receiver-overflow',
+ 'internal',
+ 'cxl-ide-tx',
+ 'cxl-ide-rx'
+ ]
+ }
+
+##
+# @CXLUncorErrorRecord:
+#
+# Record of a single error including header log.
+#
+# @type: Type of error
+# @header: 16 DWORD of header.
+##
+{ 'struct': 'CXLUncorErrorRecord',
+ 'data': {
+ 'type': 'CxlUncorErrorType',
+ 'header': [ 'uint32' ]
+ }
+}
+
+##
+# @cxl-inject-uncorrectable-errors:
+#
+# Command to allow injection of multiple errors in one go. This allows testing
+# of multiple header log handling in the OS.
+#
+# @path: CXL Type 3 device canonical QOM path
+# @errors: Errors to inject
+##
+{ 'command': 'cxl-inject-uncorrectable-errors',
+ 'data': { 'path': 'str',
+ 'errors': [ 'CXLUncorErrorRecord' ] }}
+
+##
+# @CxlCorErrorType:
+#
+# Type of CXL correctable error to inject
+#
+# @cache-data-ecc: Data ECC error on CXL.cache
+# @mem-data-ecc: Data ECC error on CXL.mem
+# @crc-threshold: Component specific and applicable to 68 byte Flit mode only.
+# @cache-poison-received: Received poison from a peer on CXL.cache.
+# @mem-poison-received: Received poison from a peer on CXL.mem
+# @physical: Received error indication from the physical layer.
+##
+{ 'enum': 'CxlCorErrorType',
+ 'data': ['cache-data-ecc',
+ 'mem-data-ecc',
+ 'crc-threshold',
+ 'retry-threshold',
+ 'cache-poison-received',
+ 'mem-poison-received',
+ 'physical']
+}
+
+##
+# @cxl-inject-correctable-error:
+#
+# Command to inject a single correctable error. Multiple error injection
+# of this error type is not interesting as there is no associated header log.
+# These errors are reported via AER as a correctable internal error, with
+# additional detail available from the CXL device.
+#
+# @path: CXL Type 3 device canonical QOM path
+# @type: Type of error.
+##
+{ 'command': 'cxl-inject-correctable-error',
+ 'data': { 'path': 'str',
+ 'type': 'CxlCorErrorType'
+ }
+}
diff --git a/qapi/meson.build b/qapi/meson.build
index fbdb442fdf..73c3c8c31a 100644
--- a/qapi/meson.build
+++ b/qapi/meson.build
@@ -31,6 +31,7 @@ qapi_all_modules = [
'compat',
'control',
'crypto',
+ 'cxl',
'dump',
'error',
'introspect',
diff --git a/qapi/qapi-schema.json b/qapi/qapi-schema.json
index f000b90744..079f2a402a 100644
--- a/qapi/qapi-schema.json
+++ b/qapi/qapi-schema.json
@@ -95,3 +95,4 @@
{ 'include': 'pci.json' }
{ 'include': 'stats.json' }
{ 'include': 'virtio.json' }
+{ 'include': 'cxl.json' }
--
2.37.2
^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [PATCH v5 8/8] hw/mem/cxl_type3: Add CXL RAS Error Injection Support.
2023-02-21 15:21 ` [PATCH v5 8/8] hw/mem/cxl_type3: Add CXL RAS Error Injection Support Jonathan Cameron
@ 2023-02-21 15:48 ` Dave Jiang
2023-02-21 22:15 ` Philippe Mathieu-Daudé
2023-10-27 4:54 ` Markus Armbruster
2 siblings, 0 replies; 27+ messages in thread
From: Dave Jiang @ 2023-02-21 15:48 UTC (permalink / raw)
To: Jonathan Cameron, qemu-devel, Michael Tsirkin
Cc: Ben Widawsky, linux-cxl, linuxarm, Ira Weiny, Gregory Price,
Philippe Mathieu-Daudé,
Mike Maslenkin, Markus Armbruster
On 2/21/23 8:21 AM, Jonathan Cameron wrote:
> CXL uses PCI AER Internal errors to signal to the host that an error has
> occurred. The host can then read more detailed status from the CXL RAS
> capability.
>
> For uncorrectable errors: support multiple injection in one operation
> as this is needed to reliably test multiple header logging support in an
> OS. The equivalent feature doesn't exist for correctable errors, so only
> one error need be injected at a time.
>
> Note:
> - Header content needs to be manually specified in a fashion that
> matches the specification for what can be in the header for each
> error type.
>
> Injection via QMP:
> { "execute": "qmp_capabilities" }
> ...
> { "execute": "cxl-inject-uncorrectable-errors",
> "arguments": {
> "path": "/machine/peripheral/cxl-pmem0",
> "errors": [
> {
> "type": "cache-address-parity",
> "header": [ 3, 4]
> },
> {
> "type": "cache-data-parity",
> "header": [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31]
> },
> {
> "type": "internal",
> "header": [ 1, 2, 4]
> }
> ]
> }}
> ...
> { "execute": "cxl-inject-correctable-error",
> "arguments": {
> "path": "/machine/peripheral/cxl-pmem0",
> "type": "physical"
> } }
>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> ---
> v5: (Thanks to Dave Jiang for review)
> - Spell out Implementation Defined (previously typo as Imdef which did
> not help)
> v4:
> - Improved QMP help text wth more detail (following request in review
> of the Poison injection series)
> ---
> hw/cxl/cxl-component-utils.c | 4 +-
> hw/mem/cxl_type3.c | 281 +++++++++++++++++++++++++++++++++
> hw/mem/cxl_type3_stubs.c | 10 ++
> hw/mem/meson.build | 2 +
> include/hw/cxl/cxl_component.h | 26 +++
> include/hw/cxl/cxl_device.h | 11 ++
> qapi/cxl.json | 118 ++++++++++++++
> qapi/meson.build | 1 +
> qapi/qapi-schema.json | 1 +
> 9 files changed, 453 insertions(+), 1 deletion(-)
>
> diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c
> index 737b4764b9..b665d4f565 100644
> --- a/hw/cxl/cxl-component-utils.c
> +++ b/hw/cxl/cxl-component-utils.c
> @@ -142,16 +142,18 @@ static void ras_init_common(uint32_t *reg_state, uint32_t *write_msk)
> * be handled as RO.
> */
> stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_STATUS, 0);
> + stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_STATUS, 0x1cfff);
> /* Bits 12-13 and 17-31 reserved in CXL 2.0 */
> stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_MASK, 0x1cfff);
> stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_MASK, 0x1cfff);
> stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_SEVERITY, 0x1cfff);
> stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_SEVERITY, 0x1cfff);
> stl_le_p(reg_state + R_CXL_RAS_COR_ERR_STATUS, 0);
> + stl_le_p(write_msk + R_CXL_RAS_COR_ERR_STATUS, 0x7f);
> stl_le_p(reg_state + R_CXL_RAS_COR_ERR_MASK, 0x7f);
> stl_le_p(write_msk + R_CXL_RAS_COR_ERR_MASK, 0x7f);
> /* CXL switches and devices must set */
> - stl_le_p(reg_state + R_CXL_RAS_ERR_CAP_CTRL, 0x00);
> + stl_le_p(reg_state + R_CXL_RAS_ERR_CAP_CTRL, 0x200);
> }
>
> static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk,
> diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
> index 6cdd988d1d..abe60b362c 100644
> --- a/hw/mem/cxl_type3.c
> +++ b/hw/mem/cxl_type3.c
> @@ -1,6 +1,7 @@
> #include "qemu/osdep.h"
> #include "qemu/units.h"
> #include "qemu/error-report.h"
> +#include "qapi/qapi-commands-cxl.h"
> #include "hw/mem/memory-device.h"
> #include "hw/mem/pc-dimm.h"
> #include "hw/pci/pci.h"
> @@ -323,6 +324,66 @@ static void hdm_decoder_commit(CXLType3Dev *ct3d, int which)
> ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, COMMITTED, 1);
> }
>
> +static int ct3d_qmp_uncor_err_to_cxl(CxlUncorErrorType qmp_err)
> +{
> + switch (qmp_err) {
> + case CXL_UNCOR_ERROR_TYPE_CACHE_DATA_PARITY:
> + return CXL_RAS_UNC_ERR_CACHE_DATA_PARITY;
> + case CXL_UNCOR_ERROR_TYPE_CACHE_ADDRESS_PARITY:
> + return CXL_RAS_UNC_ERR_CACHE_ADDRESS_PARITY;
> + case CXL_UNCOR_ERROR_TYPE_CACHE_BE_PARITY:
> + return CXL_RAS_UNC_ERR_CACHE_BE_PARITY;
> + case CXL_UNCOR_ERROR_TYPE_CACHE_DATA_ECC:
> + return CXL_RAS_UNC_ERR_CACHE_DATA_ECC;
> + case CXL_UNCOR_ERROR_TYPE_MEM_DATA_PARITY:
> + return CXL_RAS_UNC_ERR_MEM_DATA_PARITY;
> + case CXL_UNCOR_ERROR_TYPE_MEM_ADDRESS_PARITY:
> + return CXL_RAS_UNC_ERR_MEM_ADDRESS_PARITY;
> + case CXL_UNCOR_ERROR_TYPE_MEM_BE_PARITY:
> + return CXL_RAS_UNC_ERR_MEM_BE_PARITY;
> + case CXL_UNCOR_ERROR_TYPE_MEM_DATA_ECC:
> + return CXL_RAS_UNC_ERR_MEM_DATA_ECC;
> + case CXL_UNCOR_ERROR_TYPE_REINIT_THRESHOLD:
> + return CXL_RAS_UNC_ERR_REINIT_THRESHOLD;
> + case CXL_UNCOR_ERROR_TYPE_RSVD_ENCODING:
> + return CXL_RAS_UNC_ERR_RSVD_ENCODING;
> + case CXL_UNCOR_ERROR_TYPE_POISON_RECEIVED:
> + return CXL_RAS_UNC_ERR_POISON_RECEIVED;
> + case CXL_UNCOR_ERROR_TYPE_RECEIVER_OVERFLOW:
> + return CXL_RAS_UNC_ERR_RECEIVER_OVERFLOW;
> + case CXL_UNCOR_ERROR_TYPE_INTERNAL:
> + return CXL_RAS_UNC_ERR_INTERNAL;
> + case CXL_UNCOR_ERROR_TYPE_CXL_IDE_TX:
> + return CXL_RAS_UNC_ERR_CXL_IDE_TX;
> + case CXL_UNCOR_ERROR_TYPE_CXL_IDE_RX:
> + return CXL_RAS_UNC_ERR_CXL_IDE_RX;
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static int ct3d_qmp_cor_err_to_cxl(CxlCorErrorType qmp_err)
> +{
> + switch (qmp_err) {
> + case CXL_COR_ERROR_TYPE_CACHE_DATA_ECC:
> + return CXL_RAS_COR_ERR_CACHE_DATA_ECC;
> + case CXL_COR_ERROR_TYPE_MEM_DATA_ECC:
> + return CXL_RAS_COR_ERR_MEM_DATA_ECC;
> + case CXL_COR_ERROR_TYPE_CRC_THRESHOLD:
> + return CXL_RAS_COR_ERR_CRC_THRESHOLD;
> + case CXL_COR_ERROR_TYPE_RETRY_THRESHOLD:
> + return CXL_RAS_COR_ERR_RETRY_THRESHOLD;
> + case CXL_COR_ERROR_TYPE_CACHE_POISON_RECEIVED:
> + return CXL_RAS_COR_ERR_CACHE_POISON_RECEIVED;
> + case CXL_COR_ERROR_TYPE_MEM_POISON_RECEIVED:
> + return CXL_RAS_COR_ERR_MEM_POISON_RECEIVED;
> + case CXL_COR_ERROR_TYPE_PHYSICAL:
> + return CXL_RAS_COR_ERR_PHYSICAL;
> + default:
> + return -EINVAL;
> + }
> +}
> +
> static void ct3d_reg_write(void *opaque, hwaddr offset, uint64_t value,
> unsigned size)
> {
> @@ -341,6 +402,83 @@ static void ct3d_reg_write(void *opaque, hwaddr offset, uint64_t value,
> should_commit = FIELD_EX32(value, CXL_HDM_DECODER0_CTRL, COMMIT);
> which_hdm = 0;
> break;
> + case A_CXL_RAS_UNC_ERR_STATUS:
> + {
> + uint32_t capctrl = ldl_le_p(cache_mem + R_CXL_RAS_ERR_CAP_CTRL);
> + uint32_t fe = FIELD_EX32(capctrl, CXL_RAS_ERR_CAP_CTRL, FIRST_ERROR_POINTER);
> + CXLError *cxl_err;
> + uint32_t unc_err;
> +
> + /*
> + * If single bit written that corresponds to the first error
> + * pointer being cleared, update the status and header log.
> + */
> + if (!QTAILQ_EMPTY(&ct3d->error_list)) {
> + if ((1 << fe) ^ value) {
> + CXLError *cxl_next;
> + /*
> + * Software is using wrong flow for multiple header recording
> + * Following behavior in PCIe r6.0 and assuming multiple
> + * header support. Implementation defined choice to clear all
> + * matching records if more than one bit set - which corresponds
> + * closest to behavior of hardware not capable of multiple
> + * header recording.
> + */
> + QTAILQ_FOREACH_SAFE(cxl_err, &ct3d->error_list, node, cxl_next) {
> + if ((1 << cxl_err->type) & value) {
> + QTAILQ_REMOVE(&ct3d->error_list, cxl_err, node);
> + g_free(cxl_err);
> + }
> + }
> + } else {
> + /* Done with previous FE, so drop from list */
> + cxl_err = QTAILQ_FIRST(&ct3d->error_list);
> + QTAILQ_REMOVE(&ct3d->error_list, cxl_err, node);
> + g_free(cxl_err);
> + }
> +
> + /*
> + * If there is another FE, then put that in place and update
> + * the header log
> + */
> + if (!QTAILQ_EMPTY(&ct3d->error_list)) {
> + uint32_t *header_log = &cache_mem[R_CXL_RAS_ERR_HEADER0];
> + int i;
> +
> + cxl_err = QTAILQ_FIRST(&ct3d->error_list);
> + for (i = 0; i < CXL_RAS_ERR_HEADER_NUM; i++) {
> + stl_le_p(header_log + i, cxl_err->header[i]);
> + }
> + capctrl = FIELD_DP32(capctrl, CXL_RAS_ERR_CAP_CTRL,
> + FIRST_ERROR_POINTER, cxl_err->type);
> + } else {
> + /*
> + * If no more errors, then follow recomendation of PCI spec
> + * r6.0 6.2.4.2 to set the first error pointer to a status
> + * bit that will never be used.
> + */
> + capctrl = FIELD_DP32(capctrl, CXL_RAS_ERR_CAP_CTRL,
> + FIRST_ERROR_POINTER,
> + CXL_RAS_UNC_ERR_CXL_UNUSED);
> + }
> + stl_le_p((uint8_t *)cache_mem + A_CXL_RAS_ERR_CAP_CTRL, capctrl);
> + }
> + unc_err = 0;
> + QTAILQ_FOREACH(cxl_err, &ct3d->error_list, node) {
> + unc_err |= 1 << cxl_err->type;
> + }
> + stl_le_p((uint8_t *)cache_mem + offset, unc_err);
> +
> + return;
> + }
> + case A_CXL_RAS_COR_ERR_STATUS:
> + {
> + uint32_t rw1c = value;
> + uint32_t temp = ldl_le_p((uint8_t *)cache_mem + offset);
> + temp &= ~rw1c;
> + stl_le_p((uint8_t *)cache_mem + offset, temp);
> + return;
> + }
> default:
> break;
> }
> @@ -404,6 +542,8 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp)
> unsigned short msix_num = 1;
> int i, rc;
>
> + QTAILQ_INIT(&ct3d->error_list);
> +
> if (!cxl_setup_memory(ct3d, errp)) {
> return;
> }
> @@ -631,6 +771,147 @@ static void set_lsa(CXLType3Dev *ct3d, const void *buf, uint64_t size,
> */
> }
>
> +/* For uncorrectable errors include support for multiple header recording */
> +void qmp_cxl_inject_uncorrectable_errors(const char *path,
> + CXLUncorErrorRecordList *errors,
> + Error **errp)
> +{
> + Object *obj = object_resolve_path(path, NULL);
> + static PCIEAERErr err = {};
> + CXLType3Dev *ct3d;
> + CXLError *cxl_err;
> + uint32_t *reg_state;
> + uint32_t unc_err;
> + bool first;
> +
> + if (!obj) {
> + error_setg(errp, "Unable to resolve path");
> + return;
> + }
> +
> + if (!object_dynamic_cast(obj, TYPE_CXL_TYPE3)) {
> + error_setg(errp, "Path does not point to a CXL type 3 device");
> + return;
> + }
> +
> + err.status = PCI_ERR_UNC_INTN;
> + err.source_id = pci_requester_id(PCI_DEVICE(obj));
> + err.flags = 0;
> +
> + ct3d = CXL_TYPE3(obj);
> +
> + first = QTAILQ_EMPTY(&ct3d->error_list);
> + reg_state = ct3d->cxl_cstate.crb.cache_mem_registers;
> + while (errors) {
> + uint32List *header = errors->value->header;
> + uint8_t header_count = 0;
> + int cxl_err_code;
> +
> + cxl_err_code = ct3d_qmp_uncor_err_to_cxl(errors->value->type);
> + if (cxl_err_code < 0) {
> + error_setg(errp, "Unknown error code");
> + return;
> + }
> +
> + /* If the error is masked, nothing to do here */
> + if (!((1 << cxl_err_code) &
> + ~ldl_le_p(reg_state + R_CXL_RAS_UNC_ERR_MASK))) {
> + errors = errors->next;
> + continue;
> + }
> +
> + cxl_err = g_malloc0(sizeof(*cxl_err));
> + if (!cxl_err) {
> + return;
> + }
> +
> + cxl_err->type = cxl_err_code;
> + while (header && header_count < 32) {
> + cxl_err->header[header_count++] = header->value;
> + header = header->next;
> + }
> + if (header_count > 32) {
> + error_setg(errp, "Header must be 32 DWORD or less");
> + return;
> + }
> + QTAILQ_INSERT_TAIL(&ct3d->error_list, cxl_err, node);
> +
> + errors = errors->next;
> + }
> +
> + if (first && !QTAILQ_EMPTY(&ct3d->error_list)) {
> + uint32_t *cache_mem = ct3d->cxl_cstate.crb.cache_mem_registers;
> + uint32_t capctrl = ldl_le_p(cache_mem + R_CXL_RAS_ERR_CAP_CTRL);
> + uint32_t *header_log = &cache_mem[R_CXL_RAS_ERR_HEADER0];
> + int i;
> +
> + cxl_err = QTAILQ_FIRST(&ct3d->error_list);
> + for (i = 0; i < CXL_RAS_ERR_HEADER_NUM; i++) {
> + stl_le_p(header_log + i, cxl_err->header[i]);
> + }
> +
> + capctrl = FIELD_DP32(capctrl, CXL_RAS_ERR_CAP_CTRL,
> + FIRST_ERROR_POINTER, cxl_err->type);
> + stl_le_p(cache_mem + R_CXL_RAS_ERR_CAP_CTRL, capctrl);
> + }
> +
> + unc_err = 0;
> + QTAILQ_FOREACH(cxl_err, &ct3d->error_list, node) {
> + unc_err |= (1 << cxl_err->type);
> + }
> + if (!unc_err) {
> + return;
> + }
> +
> + stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_STATUS, unc_err);
> + pcie_aer_inject_error(PCI_DEVICE(obj), &err);
> +
> + return;
> +}
> +
> +void qmp_cxl_inject_correctable_error(const char *path, CxlCorErrorType type,
> + Error **errp)
> +{
> + static PCIEAERErr err = {};
> + Object *obj = object_resolve_path(path, NULL);
> + CXLType3Dev *ct3d;
> + uint32_t *reg_state;
> + uint32_t cor_err;
> + int cxl_err_type;
> +
> + if (!obj) {
> + error_setg(errp, "Unable to resolve path");
> + return;
> + }
> + if (!object_dynamic_cast(obj, TYPE_CXL_TYPE3)) {
> + error_setg(errp, "Path does not point to a CXL type 3 device");
> + return;
> + }
> +
> + err.status = PCI_ERR_COR_INTERNAL;
> + err.source_id = pci_requester_id(PCI_DEVICE(obj));
> + err.flags = PCIE_AER_ERR_IS_CORRECTABLE;
> +
> + ct3d = CXL_TYPE3(obj);
> + reg_state = ct3d->cxl_cstate.crb.cache_mem_registers;
> + cor_err = ldl_le_p(reg_state + R_CXL_RAS_COR_ERR_STATUS);
> +
> + cxl_err_type = ct3d_qmp_cor_err_to_cxl(type);
> + if (cxl_err_type < 0) {
> + error_setg(errp, "Invalid COR error");
> + return;
> + }
> + /* If the error is masked, nothting to do here */
> + if (!((1 << cxl_err_type) & ~ldl_le_p(reg_state + R_CXL_RAS_COR_ERR_MASK))) {
> + return;
> + }
> +
> + cor_err |= (1 << cxl_err_type);
> + stl_le_p(reg_state + R_CXL_RAS_COR_ERR_STATUS, cor_err);
> +
> + pcie_aer_inject_error(PCI_DEVICE(obj), &err);
> +}
> +
> static void ct3_class_init(ObjectClass *oc, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(oc);
> diff --git a/hw/mem/cxl_type3_stubs.c b/hw/mem/cxl_type3_stubs.c
> new file mode 100644
> index 0000000000..b6b51ced54
> --- /dev/null
> +++ b/hw/mem/cxl_type3_stubs.c
> @@ -0,0 +1,10 @@
> +
> +#include "qemu/osdep.h"
> +#include "qapi/qapi-commands-cxl.h"
> +
> +void qmp_cxl_inject_uncorrectable_errors(const char *path,
> + CXLUncorErrorRecordList *errors,
> + Error **errp) {}
> +
> +void qmp_cxl_inject_correctable_error(const char *path, CxlCorErrorType type,
> + Error **errp) {}
> diff --git a/hw/mem/meson.build b/hw/mem/meson.build
> index 609b2b36fc..56c2618b84 100644
> --- a/hw/mem/meson.build
> +++ b/hw/mem/meson.build
> @@ -4,6 +4,8 @@ mem_ss.add(when: 'CONFIG_DIMM', if_true: files('pc-dimm.c'))
> mem_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_mc.c'))
> mem_ss.add(when: 'CONFIG_NVDIMM', if_true: files('nvdimm.c'))
> mem_ss.add(when: 'CONFIG_CXL_MEM_DEVICE', if_true: files('cxl_type3.c'))
> +softmmu_ss.add(when: 'CONFIG_CXL_MEM_DEVICE', if_false: files('cxl_type3_stubs.c'))
> +softmmu_ss.add(when: 'CONFIG_ALL', if_true: files('cxl_type3_stubs.c'))
>
> softmmu_ss.add_all(when: 'CONFIG_MEM_DEVICE', if_true: mem_ss)
>
> diff --git a/include/hw/cxl/cxl_component.h b/include/hw/cxl/cxl_component.h
> index 692d7a5507..ec4203b83f 100644
> --- a/include/hw/cxl/cxl_component.h
> +++ b/include/hw/cxl/cxl_component.h
> @@ -65,11 +65,37 @@ CXLx_CAPABILITY_HEADER(SNOOP, 0x14)
> #define CXL_RAS_REGISTERS_OFFSET 0x80
> #define CXL_RAS_REGISTERS_SIZE 0x58
> REG32(CXL_RAS_UNC_ERR_STATUS, CXL_RAS_REGISTERS_OFFSET)
> +#define CXL_RAS_UNC_ERR_CACHE_DATA_PARITY 0
> +#define CXL_RAS_UNC_ERR_CACHE_ADDRESS_PARITY 1
> +#define CXL_RAS_UNC_ERR_CACHE_BE_PARITY 2
> +#define CXL_RAS_UNC_ERR_CACHE_DATA_ECC 3
> +#define CXL_RAS_UNC_ERR_MEM_DATA_PARITY 4
> +#define CXL_RAS_UNC_ERR_MEM_ADDRESS_PARITY 5
> +#define CXL_RAS_UNC_ERR_MEM_BE_PARITY 6
> +#define CXL_RAS_UNC_ERR_MEM_DATA_ECC 7
> +#define CXL_RAS_UNC_ERR_REINIT_THRESHOLD 8
> +#define CXL_RAS_UNC_ERR_RSVD_ENCODING 9
> +#define CXL_RAS_UNC_ERR_POISON_RECEIVED 10
> +#define CXL_RAS_UNC_ERR_RECEIVER_OVERFLOW 11
> +#define CXL_RAS_UNC_ERR_INTERNAL 14
> +#define CXL_RAS_UNC_ERR_CXL_IDE_TX 15
> +#define CXL_RAS_UNC_ERR_CXL_IDE_RX 16
> +#define CXL_RAS_UNC_ERR_CXL_UNUSED 63 /* Magic value */
> REG32(CXL_RAS_UNC_ERR_MASK, CXL_RAS_REGISTERS_OFFSET + 0x4)
> REG32(CXL_RAS_UNC_ERR_SEVERITY, CXL_RAS_REGISTERS_OFFSET + 0x8)
> REG32(CXL_RAS_COR_ERR_STATUS, CXL_RAS_REGISTERS_OFFSET + 0xc)
> +#define CXL_RAS_COR_ERR_CACHE_DATA_ECC 0
> +#define CXL_RAS_COR_ERR_MEM_DATA_ECC 1
> +#define CXL_RAS_COR_ERR_CRC_THRESHOLD 2
> +#define CXL_RAS_COR_ERR_RETRY_THRESHOLD 3
> +#define CXL_RAS_COR_ERR_CACHE_POISON_RECEIVED 4
> +#define CXL_RAS_COR_ERR_MEM_POISON_RECEIVED 5
> +#define CXL_RAS_COR_ERR_PHYSICAL 6
> REG32(CXL_RAS_COR_ERR_MASK, CXL_RAS_REGISTERS_OFFSET + 0x10)
> REG32(CXL_RAS_ERR_CAP_CTRL, CXL_RAS_REGISTERS_OFFSET + 0x14)
> + FIELD(CXL_RAS_ERR_CAP_CTRL, FIRST_ERROR_POINTER, 0, 6)
> +REG32(CXL_RAS_ERR_HEADER0, CXL_RAS_REGISTERS_OFFSET + 0x18)
> +#define CXL_RAS_ERR_HEADER_NUM 32
> /* Offset 0x18 - 0x58 reserved for RAS logs */
>
> /* 8.2.5.10 - CXL Security Capability Structure */
> diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
> index 7e5ad65c1d..d589f78202 100644
> --- a/include/hw/cxl/cxl_device.h
> +++ b/include/hw/cxl/cxl_device.h
> @@ -232,6 +232,14 @@ REG64(CXL_MEM_DEV_STS, 0)
> FIELD(CXL_MEM_DEV_STS, MBOX_READY, 4, 1)
> FIELD(CXL_MEM_DEV_STS, RESET_NEEDED, 5, 3)
>
> +typedef struct CXLError {
> + QTAILQ_ENTRY(CXLError) node;
> + int type; /* Error code as per FE definition */
> + uint32_t header[32];
> +} CXLError;
> +
> +typedef QTAILQ_HEAD(, CXLError) CXLErrorList;
> +
> struct CXLType3Dev {
> /* Private */
> PCIDevice parent_obj;
> @@ -248,6 +256,9 @@ struct CXLType3Dev {
>
> /* DOE */
> DOECap doe_cdat;
> +
> + /* Error injection */
> + CXLErrorList error_list;
> };
>
> #define TYPE_CXL_TYPE3 "cxl-type3"
> diff --git a/qapi/cxl.json b/qapi/cxl.json
> new file mode 100644
> index 0000000000..ac7e167fa2
> --- /dev/null
> +++ b/qapi/cxl.json
> @@ -0,0 +1,118 @@
> +# -*- Mode: Python -*-
> +# vim: filetype=python
> +
> +##
> +# = CXL devices
> +##
> +
> +##
> +# @CxlUncorErrorType:
> +#
> +# Type of uncorrectable CXL error to inject. These errors are reported via
> +# an AER uncorrectable internal error with additional information logged at
> +# the CXL device.
> +#
> +# @cache-data-parity: Data error such as data parity or data ECC error CXL.cache
> +# @cache-address-parity: Address parity or other errors associated with the
> +# address field on CXL.cache
> +# @cache-be-parity: Byte enable parity or other byte enable errors on CXL.cache
> +# @cache-data-ecc: ECC error on CXL.cache
> +# @mem-data-parity: Data error such as data parity or data ECC error on CXL.mem
> +# @mem-address-parity: Address parity or other errors associated with the
> +# address field on CXL.mem
> +# @mem-be-parity: Byte enable parity or other byte enable errors on CXL.mem.
> +# @mem-data-ecc: Data ECC error on CXL.mem.
> +# @reinit-threshold: REINIT threshold hit.
> +# @rsvd-encoding: Received unrecognized encoding.
> +# @poison-received: Received poison from the peer.
> +# @receiver-overflow: Buffer overflows (first 3 bits of header log indicate which)
> +# @internal: Component specific error
> +# @cxl-ide-tx: Integrity and data encryption tx error.
> +# @cxl-ide-rx: Integrity and data encryption rx error.
> +##
> +
> +{ 'enum': 'CxlUncorErrorType',
> + 'data': ['cache-data-parity',
> + 'cache-address-parity',
> + 'cache-be-parity',
> + 'cache-data-ecc',
> + 'mem-data-parity',
> + 'mem-address-parity',
> + 'mem-be-parity',
> + 'mem-data-ecc',
> + 'reinit-threshold',
> + 'rsvd-encoding',
> + 'poison-received',
> + 'receiver-overflow',
> + 'internal',
> + 'cxl-ide-tx',
> + 'cxl-ide-rx'
> + ]
> + }
> +
> +##
> +# @CXLUncorErrorRecord:
> +#
> +# Record of a single error including header log.
> +#
> +# @type: Type of error
> +# @header: 16 DWORD of header.
> +##
> +{ 'struct': 'CXLUncorErrorRecord',
> + 'data': {
> + 'type': 'CxlUncorErrorType',
> + 'header': [ 'uint32' ]
> + }
> +}
> +
> +##
> +# @cxl-inject-uncorrectable-errors:
> +#
> +# Command to allow injection of multiple errors in one go. This allows testing
> +# of multiple header log handling in the OS.
> +#
> +# @path: CXL Type 3 device canonical QOM path
> +# @errors: Errors to inject
> +##
> +{ 'command': 'cxl-inject-uncorrectable-errors',
> + 'data': { 'path': 'str',
> + 'errors': [ 'CXLUncorErrorRecord' ] }}
> +
> +##
> +# @CxlCorErrorType:
> +#
> +# Type of CXL correctable error to inject
> +#
> +# @cache-data-ecc: Data ECC error on CXL.cache
> +# @mem-data-ecc: Data ECC error on CXL.mem
> +# @crc-threshold: Component specific and applicable to 68 byte Flit mode only.
> +# @cache-poison-received: Received poison from a peer on CXL.cache.
> +# @mem-poison-received: Received poison from a peer on CXL.mem
> +# @physical: Received error indication from the physical layer.
> +##
> +{ 'enum': 'CxlCorErrorType',
> + 'data': ['cache-data-ecc',
> + 'mem-data-ecc',
> + 'crc-threshold',
> + 'retry-threshold',
> + 'cache-poison-received',
> + 'mem-poison-received',
> + 'physical']
> +}
> +
> +##
> +# @cxl-inject-correctable-error:
> +#
> +# Command to inject a single correctable error. Multiple error injection
> +# of this error type is not interesting as there is no associated header log.
> +# These errors are reported via AER as a correctable internal error, with
> +# additional detail available from the CXL device.
> +#
> +# @path: CXL Type 3 device canonical QOM path
> +# @type: Type of error.
> +##
> +{ 'command': 'cxl-inject-correctable-error',
> + 'data': { 'path': 'str',
> + 'type': 'CxlCorErrorType'
> + }
> +}
> diff --git a/qapi/meson.build b/qapi/meson.build
> index fbdb442fdf..73c3c8c31a 100644
> --- a/qapi/meson.build
> +++ b/qapi/meson.build
> @@ -31,6 +31,7 @@ qapi_all_modules = [
> 'compat',
> 'control',
> 'crypto',
> + 'cxl',
> 'dump',
> 'error',
> 'introspect',
> diff --git a/qapi/qapi-schema.json b/qapi/qapi-schema.json
> index f000b90744..079f2a402a 100644
> --- a/qapi/qapi-schema.json
> +++ b/qapi/qapi-schema.json
> @@ -95,3 +95,4 @@
> { 'include': 'pci.json' }
> { 'include': 'stats.json' }
> { 'include': 'virtio.json' }
> +{ 'include': 'cxl.json' }
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v5 6/8] hw/cxl: Fix endian issues in CXL RAS capability defaults / masks
2023-02-21 15:21 ` [PATCH v5 6/8] hw/cxl: Fix endian issues in CXL RAS capability defaults / masks Jonathan Cameron
@ 2023-02-21 22:06 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-02-21 22:06 UTC (permalink / raw)
To: Jonathan Cameron, qemu-devel, Michael Tsirkin
Cc: Ben Widawsky, linux-cxl, linuxarm, Ira Weiny, Gregory Price,
Mike Maslenkin, Dave Jiang, Markus Armbruster
On 21/2/23 16:21, Jonathan Cameron wrote:
> As these are about to be modified, fix the endian handle for
> this set of registers rather than making it worse.
>
> Note that CXL is currently only supported in QEMU on
> x86 (arm64 patches out of tree) so we aren't going to yet hit
> an problems with big endian. However it is good to avoid making
> things worse for that support in the future.
>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> ---
> hw/cxl/cxl-component-utils.c | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v5 7/8] hw/pci/aer: Make PCIE AER error injection facility available for other emulation to use.
2023-02-21 15:21 ` [PATCH v5 7/8] hw/pci/aer: Make PCIE AER error injection facility available for other emulation to use Jonathan Cameron
@ 2023-02-21 22:08 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-02-21 22:08 UTC (permalink / raw)
To: Jonathan Cameron, qemu-devel, Michael Tsirkin
Cc: Ben Widawsky, linux-cxl, linuxarm, Ira Weiny, Gregory Price,
Mike Maslenkin, Dave Jiang, Markus Armbruster
On 21/2/23 16:21, Jonathan Cameron wrote:
> This infrastructure will be reused for CXL RAS error injection
> in patches that follow.
>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> ---
> hw/pci/pci-internal.h | 1 -
> include/hw/pci/pcie_aer.h | 1 +
> 2 files changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v5 8/8] hw/mem/cxl_type3: Add CXL RAS Error Injection Support.
2023-02-21 15:21 ` [PATCH v5 8/8] hw/mem/cxl_type3: Add CXL RAS Error Injection Support Jonathan Cameron
2023-02-21 15:48 ` Dave Jiang
@ 2023-02-21 22:15 ` Philippe Mathieu-Daudé
2023-02-22 14:53 ` Jonathan Cameron
2023-10-27 4:54 ` Markus Armbruster
2 siblings, 1 reply; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-02-21 22:15 UTC (permalink / raw)
To: Jonathan Cameron, qemu-devel, Michael Tsirkin
Cc: Ben Widawsky, linux-cxl, linuxarm, Ira Weiny, Gregory Price,
Mike Maslenkin, Dave Jiang, Markus Armbruster
Hi Jonathan,
On 21/2/23 16:21, Jonathan Cameron wrote:
> CXL uses PCI AER Internal errors to signal to the host that an error has
> occurred. The host can then read more detailed status from the CXL RAS
> capability.
>
> For uncorrectable errors: support multiple injection in one operation
> as this is needed to reliably test multiple header logging support in an
> OS. The equivalent feature doesn't exist for correctable errors, so only
> one error need be injected at a time.
>
> Note:
> - Header content needs to be manually specified in a fashion that
> matches the specification for what can be in the header for each
> error type.
>
> Injection via QMP:
> { "execute": "qmp_capabilities" }
> ...
> { "execute": "cxl-inject-uncorrectable-errors",
> "arguments": {
> "path": "/machine/peripheral/cxl-pmem0",
> "errors": [
> {
> "type": "cache-address-parity",
> "header": [ 3, 4]
> },
> {
> "type": "cache-data-parity",
> "header": [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31]
> },
> {
> "type": "internal",
> "header": [ 1, 2, 4]
> }
> ]
> }}
> ...
> { "execute": "cxl-inject-correctable-error",
> "arguments": {
> "path": "/machine/peripheral/cxl-pmem0",
> "type": "physical"
> } }
>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
> v5: (Thanks to Dave Jiang for review)
> - Spell out Implementation Defined (previously typo as Imdef which did
> not help)
> v4:
> - Improved QMP help text wth more detail (following request in review
> of the Poison injection series)
> ---
> hw/cxl/cxl-component-utils.c | 4 +-
> hw/mem/cxl_type3.c | 281 +++++++++++++++++++++++++++++++++
> hw/mem/cxl_type3_stubs.c | 10 ++
> hw/mem/meson.build | 2 +
> include/hw/cxl/cxl_component.h | 26 +++
> include/hw/cxl/cxl_device.h | 11 ++
> qapi/cxl.json | 118 ++++++++++++++
> qapi/meson.build | 1 +
> qapi/qapi-schema.json | 1 +
> 9 files changed, 453 insertions(+), 1 deletion(-)
> diff --git a/hw/mem/cxl_type3_stubs.c b/hw/mem/cxl_type3_stubs.c
> new file mode 100644
> index 0000000000..b6b51ced54
> --- /dev/null
> +++ b/hw/mem/cxl_type3_stubs.c
> @@ -0,0 +1,10 @@
> +
> +#include "qemu/osdep.h"
> +#include "qapi/qapi-commands-cxl.h"
> +
> +void qmp_cxl_inject_uncorrectable_errors(const char *path,
> + CXLUncorErrorRecordList *errors,
> + Error **errp) {
What about:
error_setg(errp, "CLX support is not compiled in");
}
> +
> +void qmp_cxl_inject_correctable_error(const char *path, CxlCorErrorType type,
> + Error **errp) {}
Ditto.
> diff --git a/qapi/cxl.json b/qapi/cxl.json
> new file mode 100644
> index 0000000000..ac7e167fa2
> --- /dev/null
> +++ b/qapi/cxl.json
> @@ -0,0 +1,118 @@
> +# -*- Mode: Python -*-
> +# vim: filetype=python
> +
> +##
> +# = CXL devices
> +##
> +
> +##
> +# @CxlUncorErrorType:
Likely missing a "(since 8.0)" mention somewhere.
> +#
> +# Type of uncorrectable CXL error to inject. These errors are reported via
> +# an AER uncorrectable internal error with additional information logged at
> +# the CXL device.
> +#
> +# @cache-data-parity: Data error such as data parity or data ECC error CXL.cache
> +# @cache-address-parity: Address parity or other errors associated with the
> +# address field on CXL.cache
> +# @cache-be-parity: Byte enable parity or other byte enable errors on CXL.cache
> +# @cache-data-ecc: ECC error on CXL.cache
> +# @mem-data-parity: Data error such as data parity or data ECC error on CXL.mem
> +# @mem-address-parity: Address parity or other errors associated with the
> +# address field on CXL.mem
> +# @mem-be-parity: Byte enable parity or other byte enable errors on CXL.mem.
> +# @mem-data-ecc: Data ECC error on CXL.mem.
> +# @reinit-threshold: REINIT threshold hit.
> +# @rsvd-encoding: Received unrecognized encoding.
> +# @poison-received: Received poison from the peer.
> +# @receiver-overflow: Buffer overflows (first 3 bits of header log indicate which)
> +# @internal: Component specific error
> +# @cxl-ide-tx: Integrity and data encryption tx error.
> +# @cxl-ide-rx: Integrity and data encryption rx error.
> +##
> +
> +{ 'enum': 'CxlUncorErrorType',
Doesn't these need
'if': 'CONFIG_CXL_MEM_DEVICE',
?
> + 'data': ['cache-data-parity',
> + 'cache-address-parity',
> + 'cache-be-parity',
> + 'cache-data-ecc',
> + 'mem-data-parity',
> + 'mem-address-parity',
> + 'mem-be-parity',
> + 'mem-data-ecc',
> + 'reinit-threshold',
> + 'rsvd-encoding',
> + 'poison-received',
> + 'receiver-overflow',
> + 'internal',
> + 'cxl-ide-tx',
> + 'cxl-ide-rx'
> + ]
> + }
> +
> +##
> +# @CXLUncorErrorRecord:
> +#
> +# Record of a single error including header log.
> +#
> +# @type: Type of error
> +# @header: 16 DWORD of header.
> +##
> +{ 'struct': 'CXLUncorErrorRecord',
> + 'data': {
> + 'type': 'CxlUncorErrorType',
> + 'header': [ 'uint32' ]
> + }
> +}
> +
> +##
> +# @cxl-inject-uncorrectable-errors:
> +#
> +# Command to allow injection of multiple errors in one go. This allows testing
> +# of multiple header log handling in the OS.
> +#
> +# @path: CXL Type 3 device canonical QOM path
> +# @errors: Errors to inject
> +##
> +{ 'command': 'cxl-inject-uncorrectable-errors',
> + 'data': { 'path': 'str',
> + 'errors': [ 'CXLUncorErrorRecord' ] }}
> +
> +##
> +# @CxlCorErrorType:
> +#
> +# Type of CXL correctable error to inject
> +#
> +# @cache-data-ecc: Data ECC error on CXL.cache
> +# @mem-data-ecc: Data ECC error on CXL.mem
> +# @crc-threshold: Component specific and applicable to 68 byte Flit mode only.
> +# @cache-poison-received: Received poison from a peer on CXL.cache.
> +# @mem-poison-received: Received poison from a peer on CXL.mem
> +# @physical: Received error indication from the physical layer.
> +##
> +{ 'enum': 'CxlCorErrorType',
> + 'data': ['cache-data-ecc',
> + 'mem-data-ecc',
> + 'crc-threshold',
> + 'retry-threshold',
> + 'cache-poison-received',
> + 'mem-poison-received',
> + 'physical']
> +}
> +
> +##
> +# @cxl-inject-correctable-error:
> +#
> +# Command to inject a single correctable error. Multiple error injection
> +# of this error type is not interesting as there is no associated header log.
> +# These errors are reported via AER as a correctable internal error, with
> +# additional detail available from the CXL device.
> +#
> +# @path: CXL Type 3 device canonical QOM path
> +# @type: Type of error.
> +##
> +{ 'command': 'cxl-inject-correctable-error',
> + 'data': { 'path': 'str',
> + 'type': 'CxlCorErrorType'
> + }
> +}
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v5 8/8] hw/mem/cxl_type3: Add CXL RAS Error Injection Support.
2023-02-21 22:15 ` Philippe Mathieu-Daudé
@ 2023-02-22 14:53 ` Jonathan Cameron
2023-02-22 15:32 ` Philippe Mathieu-Daudé
2023-02-22 18:28 ` Markus Armbruster
0 siblings, 2 replies; 27+ messages in thread
From: Jonathan Cameron @ 2023-02-22 14:53 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Michael Tsirkin, Ben Widawsky, linux-cxl, linuxarm,
Ira Weiny, Gregory Price, Mike Maslenkin, Dave Jiang,
Markus Armbruster
On Tue, 21 Feb 2023 23:15:49 +0100
Philippe Mathieu-Daudé <philmd@linaro.org> wrote:
> Hi Jonathan,
>
> On 21/2/23 16:21, Jonathan Cameron wrote:
> > CXL uses PCI AER Internal errors to signal to the host that an error has
> > occurred. The host can then read more detailed status from the CXL RAS
> > capability.
> >
> > For uncorrectable errors: support multiple injection in one operation
> > as this is needed to reliably test multiple header logging support in an
> > OS. The equivalent feature doesn't exist for correctable errors, so only
> > one error need be injected at a time.
> >
> > Note:
> > - Header content needs to be manually specified in a fashion that
> > matches the specification for what can be in the header for each
> > error type.
> >
> > Injection via QMP:
> > { "execute": "qmp_capabilities" }
> > ...
> > { "execute": "cxl-inject-uncorrectable-errors",
> > "arguments": {
> > "path": "/machine/peripheral/cxl-pmem0",
> > "errors": [
> > {
> > "type": "cache-address-parity",
> > "header": [ 3, 4]
> > },
> > {
> > "type": "cache-data-parity",
> > "header": [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31]
> > },
> > {
> > "type": "internal",
> > "header": [ 1, 2, 4]
> > }
> > ]
> > }}
> > ...
> > { "execute": "cxl-inject-correctable-error",
> > "arguments": {
> > "path": "/machine/peripheral/cxl-pmem0",
> > "type": "physical"
> > } }
> >
> > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Hi Philippe,
Thanks for your review. One question inline.
> > +#
> > +# Type of uncorrectable CXL error to inject. These errors are reported via
> > +# an AER uncorrectable internal error with additional information logged at
> > +# the CXL device.
> > +#
> > +# @cache-data-parity: Data error such as data parity or data ECC error CXL.cache
> > +# @cache-address-parity: Address parity or other errors associated with the
> > +# address field on CXL.cache
> > +# @cache-be-parity: Byte enable parity or other byte enable errors on CXL.cache
> > +# @cache-data-ecc: ECC error on CXL.cache
> > +# @mem-data-parity: Data error such as data parity or data ECC error on CXL.mem
> > +# @mem-address-parity: Address parity or other errors associated with the
> > +# address field on CXL.mem
> > +# @mem-be-parity: Byte enable parity or other byte enable errors on CXL.mem.
> > +# @mem-data-ecc: Data ECC error on CXL.mem.
> > +# @reinit-threshold: REINIT threshold hit.
> > +# @rsvd-encoding: Received unrecognized encoding.
> > +# @poison-received: Received poison from the peer.
> > +# @receiver-overflow: Buffer overflows (first 3 bits of header log indicate which)
> > +# @internal: Component specific error
> > +# @cxl-ide-tx: Integrity and data encryption tx error.
> > +# @cxl-ide-rx: Integrity and data encryption rx error.
> > +##
> > +
> > +{ 'enum': 'CxlUncorErrorType',
>
> Doesn't these need
>
> 'if': 'CONFIG_CXL_MEM_DEVICE',
>
> ?
If I make this change I get a bunch of
./qapi/qapi-types-cxl.h:18:13: error: attempt to use poisoned "CONFIG_CXL_MEM_DEVICE"
18 | #if defined(CONFIG_CXL_MEM_DEVICE)
It's a target specific define (I think) as built alongside PCI_EXPRESS
Only CXL_ACPI is specifically included by x86 and arm64 (out of tree)
To be honest though I don't fully understand the QEMU build system so the reason
for the error might be wrong.
>
> > + 'data': ['cache-data-parity',
> > + 'cache-address-parity',
> > + 'cache-be-parity',
> > + 'cache-data-ecc',
> > + 'mem-data-parity',
> > + 'mem-address-parity',
> > + 'mem-be-parity',
> > + 'mem-data-ecc',
> > + 'reinit-threshold',
> > + 'rsvd-encoding',
> > + 'poison-received',
> > + 'receiver-overflow',
> > + 'internal',
> > + 'cxl-ide-tx',
> > + 'cxl-ide-rx'
> > + ]
> > + }
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v5 8/8] hw/mem/cxl_type3: Add CXL RAS Error Injection Support.
2023-02-22 14:53 ` Jonathan Cameron
@ 2023-02-22 15:32 ` Philippe Mathieu-Daudé
2023-02-22 16:49 ` Jonathan Cameron
2023-02-22 18:28 ` Markus Armbruster
1 sibling, 1 reply; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-02-22 15:32 UTC (permalink / raw)
To: Jonathan Cameron
Cc: qemu-devel, Michael Tsirkin, Ben Widawsky, linux-cxl, linuxarm,
Ira Weiny, Gregory Price, Mike Maslenkin, Dave Jiang,
Markus Armbruster
On 22/2/23 15:53, Jonathan Cameron wrote:
> On Tue, 21 Feb 2023 23:15:49 +0100
> Philippe Mathieu-Daudé <philmd@linaro.org> wrote:
>
>> Hi Jonathan,
>>
>> On 21/2/23 16:21, Jonathan Cameron wrote:
>>> CXL uses PCI AER Internal errors to signal to the host that an error has
>>> occurred. The host can then read more detailed status from the CXL RAS
>>> capability.
>>>
>>> For uncorrectable errors: support multiple injection in one operation
>>> as this is needed to reliably test multiple header logging support in an
>>> OS. The equivalent feature doesn't exist for correctable errors, so only
>>> one error need be injected at a time.
>>>
>>> Note:
>>> - Header content needs to be manually specified in a fashion that
>>> matches the specification for what can be in the header for each
>>> error type.
>>>
>>> Injection via QMP:
>>> { "execute": "qmp_capabilities" }
>>> ...
>>> { "execute": "cxl-inject-uncorrectable-errors",
>>> "arguments": {
>>> "path": "/machine/peripheral/cxl-pmem0",
>>> "errors": [
>>> {
>>> "type": "cache-address-parity",
>>> "header": [ 3, 4]
>>> },
>>> {
>>> "type": "cache-data-parity",
>>> "header": [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31]
>>> },
>>> {
>>> "type": "internal",
>>> "header": [ 1, 2, 4]
>>> }
>>> ]
>>> }}
>>> ...
>>> { "execute": "cxl-inject-correctable-error",
>>> "arguments": {
>>> "path": "/machine/peripheral/cxl-pmem0",
>>> "type": "physical"
>>> } }
>>>
>>> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>
> Hi Philippe,
>
> Thanks for your review. One question inline.
>
>>> +#
>>> +# Type of uncorrectable CXL error to inject. These errors are reported via
>>> +# an AER uncorrectable internal error with additional information logged at
>>> +# the CXL device.
>>> +#
>>> +# @cache-data-parity: Data error such as data parity or data ECC error CXL.cache
>>> +# @cache-address-parity: Address parity or other errors associated with the
>>> +# address field on CXL.cache
>>> +# @cache-be-parity: Byte enable parity or other byte enable errors on CXL.cache
>>> +# @cache-data-ecc: ECC error on CXL.cache
>>> +# @mem-data-parity: Data error such as data parity or data ECC error on CXL.mem
>>> +# @mem-address-parity: Address parity or other errors associated with the
>>> +# address field on CXL.mem
>>> +# @mem-be-parity: Byte enable parity or other byte enable errors on CXL.mem.
>>> +# @mem-data-ecc: Data ECC error on CXL.mem.
>>> +# @reinit-threshold: REINIT threshold hit.
>>> +# @rsvd-encoding: Received unrecognized encoding.
>>> +# @poison-received: Received poison from the peer.
>>> +# @receiver-overflow: Buffer overflows (first 3 bits of header log indicate which)
>>> +# @internal: Component specific error
>>> +# @cxl-ide-tx: Integrity and data encryption tx error.
>>> +# @cxl-ide-rx: Integrity and data encryption rx error.
>>> +##
>>> +
>>> +{ 'enum': 'CxlUncorErrorType',
>>
>> Doesn't these need
>>
>> 'if': 'CONFIG_CXL_MEM_DEVICE',
>>
>> ?
>
> If I make this change I get a bunch of
>
> ./qapi/qapi-types-cxl.h:18:13: error: attempt to use poisoned "CONFIG_CXL_MEM_DEVICE"
> 18 | #if defined(CONFIG_CXL_MEM_DEVICE)
Err, I meant the generic CONFIG_CXL, not CONFIG_CXL_MEM_DEVICE.
> It's a target specific define (I think) as built alongside PCI_EXPRESS
> Only CXL_ACPI is specifically included by x86 and arm64 (out of tree)
>
> To be honest though I don't fully understand the QEMU build system so the reason
> for the error might be wrong.
You need to restrict to system emulation (the 'have_system' check):
-- >8 --
diff --git a/qapi/meson.build b/qapi/meson.build
index fbdb442fdf..643c76d61c 100644
--- a/qapi/meson.build
+++ b/qapi/meson.build
@@ -31,6 +31,7 @@ qapi_all_modules = [
'compat',
'control',
'crypto',
- 'cxl',
'dump',
'error',
'introspect',
@@ -58,6 +59,7 @@ if have_system
'audio',
'qdev',
'pci',
+ 'cxl',
'rdma',
'rocker',
'tpm',
---
^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [PATCH v5 8/8] hw/mem/cxl_type3: Add CXL RAS Error Injection Support.
2023-02-22 15:32 ` Philippe Mathieu-Daudé
@ 2023-02-22 16:49 ` Jonathan Cameron
2023-02-22 18:16 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 27+ messages in thread
From: Jonathan Cameron @ 2023-02-22 16:49 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Michael Tsirkin, Ben Widawsky, linux-cxl, linuxarm,
Ira Weiny, Gregory Price, Mike Maslenkin, Dave Jiang,
Markus Armbruster
...
> >>> +# Type of uncorrectable CXL error to inject. These errors are reported via
> >>> +# an AER uncorrectable internal error with additional information logged at
> >>> +# the CXL device.
> >>> +#
> >>> +# @cache-data-parity: Data error such as data parity or data ECC error CXL.cache
> >>> +# @cache-address-parity: Address parity or other errors associated with the
> >>> +# address field on CXL.cache
> >>> +# @cache-be-parity: Byte enable parity or other byte enable errors on CXL.cache
> >>> +# @cache-data-ecc: ECC error on CXL.cache
> >>> +# @mem-data-parity: Data error such as data parity or data ECC error on CXL.mem
> >>> +# @mem-address-parity: Address parity or other errors associated with the
> >>> +# address field on CXL.mem
> >>> +# @mem-be-parity: Byte enable parity or other byte enable errors on CXL.mem.
> >>> +# @mem-data-ecc: Data ECC error on CXL.mem.
> >>> +# @reinit-threshold: REINIT threshold hit.
> >>> +# @rsvd-encoding: Received unrecognized encoding.
> >>> +# @poison-received: Received poison from the peer.
> >>> +# @receiver-overflow: Buffer overflows (first 3 bits of header log indicate which)
> >>> +# @internal: Component specific error
> >>> +# @cxl-ide-tx: Integrity and data encryption tx error.
> >>> +# @cxl-ide-rx: Integrity and data encryption rx error.
> >>> +##
> >>> +
> >>> +{ 'enum': 'CxlUncorErrorType',
> >>
> >> Doesn't these need
> >>
> >> 'if': 'CONFIG_CXL_MEM_DEVICE',
> >>
> >> ?
> >
> > If I make this change I get a bunch of
> >
> > ./qapi/qapi-types-cxl.h:18:13: error: attempt to use poisoned "CONFIG_CXL_MEM_DEVICE"
> > 18 | #if defined(CONFIG_CXL_MEM_DEVICE)
>
> Err, I meant the generic CONFIG_CXL, not CONFIG_CXL_MEM_DEVICE.
>
> > It's a target specific define (I think) as built alongside PCI_EXPRESS
> > Only CXL_ACPI is specifically included by x86 and arm64 (out of tree)
> >
> > To be honest though I don't fully understand the QEMU build system so the reason
> > for the error might be wrong.
>
> You need to restrict to system emulation (the 'have_system' check):
This doesn't help - still have
attempt to used poisoned "CONFIG_CXL"
>
> -- >8 --
> diff --git a/qapi/meson.build b/qapi/meson.build
> index fbdb442fdf..643c76d61c 100644
> --- a/qapi/meson.build
> +++ b/qapi/meson.build
> @@ -31,6 +31,7 @@ qapi_all_modules = [
> 'compat',
> 'control',
> 'crypto',
> - 'cxl',
> 'dump',
> 'error',
> 'introspect',
> @@ -58,6 +59,7 @@ if have_system
> 'audio',
> 'qdev',
> 'pci',
> + 'cxl',
> 'rdma',
> 'rocker',
> 'tpm',
> ---
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v5 8/8] hw/mem/cxl_type3: Add CXL RAS Error Injection Support.
2023-02-22 16:49 ` Jonathan Cameron
@ 2023-02-22 18:16 ` Philippe Mathieu-Daudé
2023-02-23 6:58 ` Thomas Huth
0 siblings, 1 reply; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-02-22 18:16 UTC (permalink / raw)
To: Jonathan Cameron
Cc: qemu-devel, Michael Tsirkin, Ben Widawsky, linux-cxl, linuxarm,
Ira Weiny, Gregory Price, Mike Maslenkin, Dave Jiang,
Markus Armbruster, Thomas Huth, Marc-André Lureau
+Thomas (meson) & Marc-André (conditional QAPI)
On 22/2/23 17:49, Jonathan Cameron wrote:
>>>>> +# Type of uncorrectable CXL error to inject. These errors are reported via
>>>>> +# an AER uncorrectable internal error with additional information logged at
>>>>> +# the CXL device.
>>>>> +#
>>>>> +# @cache-data-parity: Data error such as data parity or data ECC error CXL.cache
>>>>> +# @cache-address-parity: Address parity or other errors associated with the
>>>>> +# address field on CXL.cache
>>>>> +# @cache-be-parity: Byte enable parity or other byte enable errors on CXL.cache
>>>>> +# @cache-data-ecc: ECC error on CXL.cache
>>>>> +# @mem-data-parity: Data error such as data parity or data ECC error on CXL.mem
>>>>> +# @mem-address-parity: Address parity or other errors associated with the
>>>>> +# address field on CXL.mem
>>>>> +# @mem-be-parity: Byte enable parity or other byte enable errors on CXL.mem.
>>>>> +# @mem-data-ecc: Data ECC error on CXL.mem.
>>>>> +# @reinit-threshold: REINIT threshold hit.
>>>>> +# @rsvd-encoding: Received unrecognized encoding.
>>>>> +# @poison-received: Received poison from the peer.
>>>>> +# @receiver-overflow: Buffer overflows (first 3 bits of header log indicate which)
>>>>> +# @internal: Component specific error
>>>>> +# @cxl-ide-tx: Integrity and data encryption tx error.
>>>>> +# @cxl-ide-rx: Integrity and data encryption rx error.
>>>>> +##
>>>>> +
>>>>> +{ 'enum': 'CxlUncorErrorType',
>>>>
>>>> Doesn't these need
>>>>
>>>> 'if': 'CONFIG_CXL_MEM_DEVICE',
>>>>
>>>> ?
>>>
>>> If I make this change I get a bunch of
>>>
>>> ./qapi/qapi-types-cxl.h:18:13: error: attempt to use poisoned "CONFIG_CXL_MEM_DEVICE"
>>> 18 | #if defined(CONFIG_CXL_MEM_DEVICE)
>>
>> Err, I meant the generic CONFIG_CXL, not CONFIG_CXL_MEM_DEVICE.
>>
>>> It's a target specific define (I think) as built alongside PCI_EXPRESS
>>> Only CXL_ACPI is specifically included by x86 and arm64 (out of tree)
>>>
>>> To be honest though I don't fully understand the QEMU build system so the reason
>>> for the error might be wrong.
>>
>> You need to restrict to system emulation (the 'have_system' check):
>
> This doesn't help - still have
> attempt to used poisoned "CONFIG_CXL"
>
>
>>
>> -- >8 --
>> diff --git a/qapi/meson.build b/qapi/meson.build
>> index fbdb442fdf..643c76d61c 100644
>> --- a/qapi/meson.build
>> +++ b/qapi/meson.build
>> @@ -31,6 +31,7 @@ qapi_all_modules = [
>> 'compat',
>> 'control',
>> 'crypto',
>> - 'cxl',
>> 'dump',
>> 'error',
>> 'introspect',
>> @@ -58,6 +59,7 @@ if have_system
>> 'audio',
>> 'qdev',
>> 'pci',
>> + 'cxl',
>> 'rdma',
>> 'rocker',
>> 'tpm',
>> ---
>>
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v5 8/8] hw/mem/cxl_type3: Add CXL RAS Error Injection Support.
2023-02-22 14:53 ` Jonathan Cameron
2023-02-22 15:32 ` Philippe Mathieu-Daudé
@ 2023-02-22 18:28 ` Markus Armbruster
1 sibling, 0 replies; 27+ messages in thread
From: Markus Armbruster @ 2023-02-22 18:28 UTC (permalink / raw)
To: Jonathan Cameron
Cc: Philippe Mathieu-Daudé,
qemu-devel, Michael Tsirkin, Ben Widawsky, linux-cxl, linuxarm,
Ira Weiny, Gregory Price, Mike Maslenkin, Dave Jiang,
Markus Armbruster
Jonathan Cameron <Jonathan.Cameron@huawei.com> writes:
> On Tue, 21 Feb 2023 23:15:49 +0100
> Philippe Mathieu-Daudé <philmd@linaro.org> wrote:
>
>> Hi Jonathan,
>>
>> On 21/2/23 16:21, Jonathan Cameron wrote:
>> > CXL uses PCI AER Internal errors to signal to the host that an error has
>> > occurred. The host can then read more detailed status from the CXL RAS
>> > capability.
>> >
>> > For uncorrectable errors: support multiple injection in one operation
>> > as this is needed to reliably test multiple header logging support in an
>> > OS. The equivalent feature doesn't exist for correctable errors, so only
>> > one error need be injected at a time.
>> >
>> > Note:
>> > - Header content needs to be manually specified in a fashion that
>> > matches the specification for what can be in the header for each
>> > error type.
>> >
>> > Injection via QMP:
>> > { "execute": "qmp_capabilities" }
>> > ...
>> > { "execute": "cxl-inject-uncorrectable-errors",
>> > "arguments": {
>> > "path": "/machine/peripheral/cxl-pmem0",
>> > "errors": [
>> > {
>> > "type": "cache-address-parity",
>> > "header": [ 3, 4]
>> > },
>> > {
>> > "type": "cache-data-parity",
>> > "header": [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31]
>> > },
>> > {
>> > "type": "internal",
>> > "header": [ 1, 2, 4]
>> > }
>> > ]
>> > }}
>> > ...
>> > { "execute": "cxl-inject-correctable-error",
>> > "arguments": {
>> > "path": "/machine/peripheral/cxl-pmem0",
>> > "type": "physical"
>> > } }
>> >
>> > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>
> Hi Philippe,
>
> Thanks for your review. One question inline.
>
>> > +#
>> > +# Type of uncorrectable CXL error to inject. These errors are reported via
>> > +# an AER uncorrectable internal error with additional information logged at
>> > +# the CXL device.
>> > +#
>> > +# @cache-data-parity: Data error such as data parity or data ECC error CXL.cache
>> > +# @cache-address-parity: Address parity or other errors associated with the
>> > +# address field on CXL.cache
>> > +# @cache-be-parity: Byte enable parity or other byte enable errors on CXL.cache
>> > +# @cache-data-ecc: ECC error on CXL.cache
>> > +# @mem-data-parity: Data error such as data parity or data ECC error on CXL.mem
>> > +# @mem-address-parity: Address parity or other errors associated with the
>> > +# address field on CXL.mem
>> > +# @mem-be-parity: Byte enable parity or other byte enable errors on CXL.mem.
>> > +# @mem-data-ecc: Data ECC error on CXL.mem.
>> > +# @reinit-threshold: REINIT threshold hit.
>> > +# @rsvd-encoding: Received unrecognized encoding.
>> > +# @poison-received: Received poison from the peer.
>> > +# @receiver-overflow: Buffer overflows (first 3 bits of header log indicate which)
>> > +# @internal: Component specific error
>> > +# @cxl-ide-tx: Integrity and data encryption tx error.
>> > +# @cxl-ide-rx: Integrity and data encryption rx error.
>> > +##
>> > +
>> > +{ 'enum': 'CxlUncorErrorType',
>>
>> Doesn't these need
>>
>> 'if': 'CONFIG_CXL_MEM_DEVICE',
>>
>> ?
>
> If I make this change I get a bunch of
>
> ./qapi/qapi-types-cxl.h:18:13: error: attempt to use poisoned "CONFIG_CXL_MEM_DEVICE"
> 18 | #if defined(CONFIG_CXL_MEM_DEVICE)
This means you're trying to use target-dependent stuff in
target-independent code.
Have a look at the thread
Subject: Can we unpoison CONFIG_FOO macros?
Message-ID: <87lel9o56z.fsf@pond.sub.org>
https://lists.gnu.org/archive/html/qemu-devel/2023-02/msg01885.html
and if questions remain, ask them right here.
> It's a target specific define (I think) as built alongside PCI_EXPRESS
> Only CXL_ACPI is specifically included by x86 and arm64 (out of tree)
>
> To be honest though I don't fully understand the QEMU build system so the reason
> for the error might be wrong.
[...]
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v5 8/8] hw/mem/cxl_type3: Add CXL RAS Error Injection Support.
2023-02-22 18:16 ` Philippe Mathieu-Daudé
@ 2023-02-23 6:58 ` Thomas Huth
2023-02-23 7:37 ` Markus Armbruster
0 siblings, 1 reply; 27+ messages in thread
From: Thomas Huth @ 2023-02-23 6:58 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Jonathan Cameron, Markus Armbruster
Cc: qemu-devel, Michael Tsirkin, Ben Widawsky, linux-cxl, linuxarm,
Ira Weiny, Gregory Price, Mike Maslenkin, Dave Jiang,
Markus Armbruster, Marc-André Lureau
On 22/02/2023 19.16, Philippe Mathieu-Daudé wrote:
> +Thomas (meson) & Marc-André (conditional QAPI)
+ Markus
> On 22/2/23 17:49, Jonathan Cameron wrote:
>>>>>> +# Type of uncorrectable CXL error to inject. These errors are
>>>>>> reported via
>>>>>> +# an AER uncorrectable internal error with additional information
>>>>>> logged at
>>>>>> +# the CXL device.
>>>>>> +#
>>>>>> +# @cache-data-parity: Data error such as data parity or data ECC
>>>>>> error CXL.cache
>>>>>> +# @cache-address-parity: Address parity or other errors associated
>>>>>> with the
>>>>>> +# address field on CXL.cache
>>>>>> +# @cache-be-parity: Byte enable parity or other byte enable errors on
>>>>>> CXL.cache
>>>>>> +# @cache-data-ecc: ECC error on CXL.cache
>>>>>> +# @mem-data-parity: Data error such as data parity or data ECC error
>>>>>> on CXL.mem
>>>>>> +# @mem-address-parity: Address parity or other errors associated with
>>>>>> the
>>>>>> +# address field on CXL.mem
>>>>>> +# @mem-be-parity: Byte enable parity or other byte enable errors on
>>>>>> CXL.mem.
>>>>>> +# @mem-data-ecc: Data ECC error on CXL.mem.
>>>>>> +# @reinit-threshold: REINIT threshold hit.
>>>>>> +# @rsvd-encoding: Received unrecognized encoding.
>>>>>> +# @poison-received: Received poison from the peer.
>>>>>> +# @receiver-overflow: Buffer overflows (first 3 bits of header log
>>>>>> indicate which)
>>>>>> +# @internal: Component specific error
>>>>>> +# @cxl-ide-tx: Integrity and data encryption tx error.
>>>>>> +# @cxl-ide-rx: Integrity and data encryption rx error.
>>>>>> +##
>>>>>> +
>>>>>> +{ 'enum': 'CxlUncorErrorType',
>>>>>
>>>>> Doesn't these need
>>>>>
>>>>> 'if': 'CONFIG_CXL_MEM_DEVICE',
>>>>>
>>>>> ?
>>>>
>>>> If I make this change I get a bunch of
>>>>
>>>> ./qapi/qapi-types-cxl.h:18:13: error: attempt to use poisoned
>>>> "CONFIG_CXL_MEM_DEVICE"
>>>> 18 | #if defined(CONFIG_CXL_MEM_DEVICE)
>>>
>>> Err, I meant the generic CONFIG_CXL, not CONFIG_CXL_MEM_DEVICE.
>>>
>>>> It's a target specific define (I think) as built alongside PCI_EXPRESS
>>>> Only CXL_ACPI is specifically included by x86 and arm64 (out of tree)
>>>>
>>>> To be honest though I don't fully understand the QEMU build system so
>>>> the reason
>>>> for the error might be wrong.
>>>
>>> You need to restrict to system emulation (the 'have_system' check):
>>
>> This doesn't help - still have
>> attempt to used poisoned "CONFIG_CXL"
Not sure how the QAPI generator works, but target specific config switches
can only be used in target specific json files there, so that's
machine-target.json and misc-target.json currently, as far as I know. Not
sure how the QAPI generator distinguishes between common and target specific
code, though ... just by the "-target" suffix? Maybe Markus or Marc-André
can comment on that.
See also:
https://lists.gnu.org/archive/html/qemu-devel/2023-02/msg01885.html
https://lists.gnu.org/archive/html/qemu-devel/2023-02/msg02001.html
Thomas
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v5 8/8] hw/mem/cxl_type3: Add CXL RAS Error Injection Support.
2023-02-23 6:58 ` Thomas Huth
@ 2023-02-23 7:37 ` Markus Armbruster
2023-02-23 14:27 ` Jonathan Cameron
0 siblings, 1 reply; 27+ messages in thread
From: Markus Armbruster @ 2023-02-23 7:37 UTC (permalink / raw)
To: Thomas Huth
Cc: Philippe Mathieu-Daudé,
Jonathan Cameron, qemu-devel, Michael Tsirkin, Ben Widawsky,
linux-cxl, linuxarm, Ira Weiny, Gregory Price, Mike Maslenkin,
Dave Jiang, Marc-André Lureau
Thomas Huth <thuth@redhat.com> writes:
> On 22/02/2023 19.16, Philippe Mathieu-Daudé wrote:
>> +Thomas (meson) & Marc-André (conditional QAPI)
>
> + Markus
>
>> On 22/2/23 17:49, Jonathan Cameron wrote:
[...]
>>>>>> Doesn't these need
>>>>>>
>>>>>> 'if': 'CONFIG_CXL_MEM_DEVICE',
>>>>>>
>>>>>> ?
>>>>>
>>>>> If I make this change I get a bunch of
>>>>>
>>>>> ./qapi/qapi-types-cxl.h:18:13: error: attempt to use poisoned "CONFIG_CXL_MEM_DEVICE"
>>>>> 18 | #if defined(CONFIG_CXL_MEM_DEVICE)
>>>>
>>>> Err, I meant the generic CONFIG_CXL, not CONFIG_CXL_MEM_DEVICE.
>>>>
>>>>> It's a target specific define (I think) as built alongside PCI_EXPRESS
>>>>> Only CXL_ACPI is specifically included by x86 and arm64 (out of tree)
>>>>>
>>>>> To be honest though I don't fully understand the QEMU build system so the reason
>>>>> for the error might be wrong.
>>>>
>>>> You need to restrict to system emulation (the 'have_system' check):
>>>
>>> This doesn't help - still have
>>> attempt to used poisoned "CONFIG_CXL"
>
> Not sure how the QAPI generator works, but target specific config switches can only be used in target specific json files there, so that's machine-target.json and misc-target.json currently, as far as I know. Not sure how the QAPI generator distinguishes between common and target specific code, though ... just by the "-target" suffix? Maybe Markus or Marc-André can comment on that.
Whenever you use a poisoned macro in a conditional, all the code
generated for this .json file (we call it a "QAPI schema module")
becomes target-dependent. The QAPI code generator itself is blissfully
unaware of this.
Since target-dependent code needs to be compiled differently, the build
process needs to be know which modules are target-dependent. We do this
in one of the stupidest ways that could possibly work: a module is
target-dependent if its name ends with "-target". There are just two
right now: qapi/machine-target.json and qapi/misc-target.json.
The logic resides in qapi/meson.build. Look for
if module.endswith('-target')
Questions?
[...]
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v5 8/8] hw/mem/cxl_type3: Add CXL RAS Error Injection Support.
2023-02-23 7:37 ` Markus Armbruster
@ 2023-02-23 14:27 ` Jonathan Cameron
2023-02-24 17:37 ` Jonathan Cameron
2023-02-24 19:02 ` Philippe Mathieu-Daudé
0 siblings, 2 replies; 27+ messages in thread
From: Jonathan Cameron @ 2023-02-23 14:27 UTC (permalink / raw)
To: Markus Armbruster
Cc: Thomas Huth, Philippe Mathieu-Daudé,
qemu-devel, Michael Tsirkin, Ben Widawsky, linux-cxl, linuxarm,
Ira Weiny, Gregory Price, Mike Maslenkin, Dave Jiang,
Marc-André Lureau
On Thu, 23 Feb 2023 08:37:46 +0100
Markus Armbruster <armbru@redhat.com> wrote:
> Thomas Huth <thuth@redhat.com> writes:
>
> > On 22/02/2023 19.16, Philippe Mathieu-Daudé wrote:
> >> +Thomas (meson) & Marc-André (conditional QAPI)
> >
> > + Markus
> >
> >> On 22/2/23 17:49, Jonathan Cameron wrote:
>
> [...]
>
> >>>>>> Doesn't these need
> >>>>>>
> >>>>>> 'if': 'CONFIG_CXL_MEM_DEVICE',
> >>>>>>
> >>>>>> ?
> >>>>>
> >>>>> If I make this change I get a bunch of
> >>>>>
> >>>>> ./qapi/qapi-types-cxl.h:18:13: error: attempt to use poisoned "CONFIG_CXL_MEM_DEVICE"
> >>>>> 18 | #if defined(CONFIG_CXL_MEM_DEVICE)
> >>>>
> >>>> Err, I meant the generic CONFIG_CXL, not CONFIG_CXL_MEM_DEVICE.
> >>>>
> >>>>> It's a target specific define (I think) as built alongside PCI_EXPRESS
> >>>>> Only CXL_ACPI is specifically included by x86 and arm64 (out of tree)
> >>>>>
> >>>>> To be honest though I don't fully understand the QEMU build system so the reason
> >>>>> for the error might be wrong.
> >>>>
> >>>> You need to restrict to system emulation (the 'have_system' check):
> >>>
> >>> This doesn't help - still have
> >>> attempt to used poisoned "CONFIG_CXL"
> >
> > Not sure how the QAPI generator works, but target specific config switches can only be used in target specific json files there, so that's machine-target.json and misc-target.json currently, as far as I know. Not sure how the QAPI generator distinguishes between common and target specific code, though ... just by the "-target" suffix? Maybe Markus or Marc-André can comment on that.
>
> Whenever you use a poisoned macro in a conditional, all the code
> generated for this .json file (we call it a "QAPI schema module")
> becomes target-dependent. The QAPI code generator itself is blissfully
> unaware of this.
>
> Since target-dependent code needs to be compiled differently, the build
> process needs to be know which modules are target-dependent. We do this
> in one of the stupidest ways that could possibly work: a module is
> target-dependent if its name ends with "-target". There are just two
> right now: qapi/machine-target.json and qapi/misc-target.json.
>
> The logic resides in qapi/meson.build. Look for
>
> if module.endswith('-target')
Thanks for all the pointers.
>
> Questions?
Is it sensible to make the cxl stuff all target dependent and do the following?
I like that we can get rid of the stubs if we do this but I'm sure there are
disadvantages. Only alternative I can currently see is continue to have
stubs and not make the qmp commands conditional on them doing anything useful.
Note this is on top of my tree so involves more changes - I'll push it down
into the relevant series.
From 551122103cf1f5bb4de8ee005482c72532181439 Mon Sep 17 00:00:00 2001
From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: Thu, 23 Feb 2023 14:22:53 +0000
Subject: [PATCH] hw/cxl: Make CXL compilation target specific
---
hw/cxl/cxl-host-stubs.c | 15 --------
hw/cxl/meson.build | 6 +---
hw/mem/cxl_type3.c | 3 +-
hw/mem/cxl_type3_stubs.c | 58 ------------------------------
hw/mem/meson.build | 8 ++---
qapi/{cxl.json => cxl-target.json} | 37 +++++++++++++------
qapi/meson.build | 2 +-
qapi/qapi-schema.json | 2 +-
8 files changed, 35 insertions(+), 96 deletions(-)
diff --git a/hw/cxl/cxl-host-stubs.c b/hw/cxl/cxl-host-stubs.c
deleted file mode 100644
index cae4afcdde..0000000000
--- a/hw/cxl/cxl-host-stubs.c
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * CXL host parameter parsing routine stubs
- *
- * Copyright (c) 2022 Huawei
- */
-#include "qemu/osdep.h"
-#include "qapi/error.h"
-#include "hw/cxl/cxl.h"
-#include "hw/cxl/cxl_host.h"
-
-void cxl_fmws_link_targets(CXLState *stat, Error **errp) {};
-void cxl_machine_init(Object *obj, CXLState *state) {};
-void cxl_hook_up_pxb_registers(PCIBus *bus, CXLState *state, Error **errp) {};
-
-const MemoryRegionOps cfmws_ops;
diff --git a/hw/cxl/meson.build b/hw/cxl/meson.build
index 99ee564ce8..99eeb84268 100644
--- a/hw/cxl/meson.build
+++ b/hw/cxl/meson.build
@@ -1,4 +1,4 @@
-softmmu_ss.add(when: 'CONFIG_CXL',
+specific_ss.add(when: 'CONFIG_CXL',
if_true: files(
'cxl-component-utils.c',
'cxl-device-utils.c',
@@ -8,9 +8,5 @@ softmmu_ss.add(when: 'CONFIG_CXL',
'cxl-events.c',
'cxl-cpmu.c',
'switch-mailbox-cci.c',
- ),
- if_false: files(
- 'cxl-host-stubs.c',
))
-softmmu_ss.add(when: 'CONFIG_ALL', if_true: files('cxl-host-stubs.c'))
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index 334ce92f5e..cf20fb81ff 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -1,7 +1,8 @@
#include "qemu/osdep.h"
+#include CONFIG_DEVICES
#include "qemu/units.h"
#include "qemu/error-report.h"
-#include "qapi/qapi-commands-cxl.h"
+#include "qapi/qapi-commands-cxl-target.h"
#include "hw/mem/memory-device.h"
#include "hw/mem/pc-dimm.h"
#include "hw/pci/pci.h"
diff --git a/hw/mem/cxl_type3_stubs.c b/hw/mem/cxl_type3_stubs.c
deleted file mode 100644
index 2196bd841c..0000000000
--- a/hw/mem/cxl_type3_stubs.c
+++ /dev/null
@@ -1,58 +0,0 @@
-
-#include "qemu/osdep.h"
-#include "qapi/error.h"
-#include "qapi/qapi-commands-cxl.h"
-
-void qmp_cxl_inject_gen_media_event(const char *path, CxlEventLog log,
- uint8_t flags, uint64_t physaddr,
- uint8_t descriptor, uint8_t type,
- uint8_t transaction_type,
- bool has_channel, uint8_t channel,
- bool has_rank, uint8_t rank,
- bool has_device, uint32_t device,
- const char *component_id,
- Error **errp) {}
-
-void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log, uint8_t flags,
- uint64_t physaddr, uint8_t descriptor,
- uint8_t type, uint8_t transaction_type,
- bool has_channel, uint8_t channel,
- bool has_rank, uint8_t rank,
- bool has_nibble_mask, uint32_t nibble_mask,
- bool has_bank_group, uint8_t bank_group,
- bool has_bank, uint8_t bank,
- bool has_row, uint32_t row,
- bool has_column, uint16_t column,
- bool has_correction_mask, uint64List *correction_mask,
- Error **errp) {}
-
-void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log,
- uint8_t flags, uint8_t type,
- uint8_t health_status,
- uint8_t media_status,
- uint8_t additional_status,
- uint8_t life_used,
- int16_t temperature,
- uint32_t dirty_shutdown_count,
- uint32_t corrected_volatile_error_count,
- uint32_t corrected_persistent_error_count,
- Error **errp) {}
-
-void qmp_cxl_inject_poison(const char *path, uint64_t start, uint64_t length,
- Error **errp)
-{
- error_setg(errp, "CXL Type 3 support is not compiled in");
-}
-
-void qmp_cxl_inject_uncorrectable_errors(const char *path,
- CXLUncorErrorRecordList *errors,
- Error **errp)
-{
- error_setg(errp, "CXL Type 3 support is not compiled in");
-}
-
-void qmp_cxl_inject_correctable_error(const char *path, CxlCorErrorType type,
- Error **errp)
-{
- error_setg(errp, "CXL Type 3 support is not compiled in");
-}
diff --git a/hw/mem/meson.build b/hw/mem/meson.build
index 56c2618b84..2bdd24512e 100644
--- a/hw/mem/meson.build
+++ b/hw/mem/meson.build
@@ -3,10 +3,10 @@ mem_ss.add(files('memory-device.c'))
mem_ss.add(when: 'CONFIG_DIMM', if_true: files('pc-dimm.c'))
mem_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_mc.c'))
mem_ss.add(when: 'CONFIG_NVDIMM', if_true: files('nvdimm.c'))
-mem_ss.add(when: 'CONFIG_CXL_MEM_DEVICE', if_true: files('cxl_type3.c'))
-softmmu_ss.add(when: 'CONFIG_CXL_MEM_DEVICE', if_false: files('cxl_type3_stubs.c'))
-softmmu_ss.add(when: 'CONFIG_ALL', if_true: files('cxl_type3_stubs.c'))
+specific_ss.add(when: 'CONFIG_CXL_MEM_DEVICE', if_true: files('cxl_type3.c'))
+#specific_ss.add(when: 'CONFIG_CXL_MEM_DEVICE', if_false: files('cxl_type3_stubs.c'))
+#specific_ss.add(when: 'CONFIG_ALL', if_true: files('cxl_type3_stubs.c'))
-softmmu_ss.add_all(when: 'CONFIG_MEM_DEVICE', if_true: mem_ss)
+specific_ss.add_all(when: 'CONFIG_MEM_DEVICE', if_true: mem_ss)
softmmu_ss.add(when: 'CONFIG_SPARSE_MEM', if_true: files('sparse-mem.c'))
diff --git a/qapi/cxl.json b/qapi/cxl-target.json
similarity index 94%
rename from qapi/cxl.json
rename to qapi/cxl-target.json
index 4c029f2807..b3aecea4f0 100644
--- a/qapi/cxl.json
+++ b/qapi/cxl-target.json
@@ -21,7 +21,8 @@
'warning',
'failure',
'fatal'
- ]
+ ],
+ 'if': 'CONFIG_CXL_MEM_DEVICE'
}
##
@@ -49,7 +50,9 @@
'type': 'uint8', 'transaction-type': 'uint8',
'*channel': 'uint8', '*rank': 'uint8',
'*device': 'uint32', '*component-id': 'str'
- }}
+ },
+ 'if': 'CONFIG_CXL_MEM_DEVICE'
+ }
##
# @cxl-inject-dram-event:
@@ -82,7 +85,9 @@
'*channel': 'uint8', '*rank': 'uint8', '*nibble-mask': 'uint32',
'*bank-group': 'uint8', '*bank': 'uint8', '*row': 'uint32',
'*column': 'uint16', '*correction-mask': [ 'uint64' ]
- }}
+ },
+ 'if': 'CONFIG_CXL_MEM_DEVICE'
+}
##
# @cxl-inject-memory-module-event:
@@ -115,7 +120,9 @@
'dirty-shutdown-count': 'uint32',
'corrected-volatile-error-count': 'uint32',
'corrected-persistent-error-count': 'uint32'
- }}
+ },
+ 'if': 'CONFIG_CXL_MEM_DEVICE'
+}
##
# @cxl-inject-poison:
@@ -133,7 +140,9 @@
# Since: 8.0
##
{ 'command': 'cxl-inject-poison',
- 'data': { 'path': 'str', 'start': 'uint64', 'length': 'uint64' }}
+ 'data': { 'path': 'str', 'start': 'uint64', 'length': 'uint64' },
+ 'if': 'CONFIG_CXL_MEM_DEVICE'
+}
##
# @CxlUncorErrorType:
@@ -179,8 +188,9 @@
'internal',
'cxl-ide-tx',
'cxl-ide-rx'
- ]
- }
+ ],
+ 'if': 'CONFIG_CXL_MEM_DEVICE'
+}
##
# @CXLUncorErrorRecord:
@@ -196,7 +206,8 @@
'data': {
'type': 'CxlUncorErrorType',
'header': [ 'uint32' ]
- }
+ },
+ 'if': 'CONFIG_CXL_MEM_DEVICE'
}
##
@@ -212,7 +223,9 @@
##
{ 'command': 'cxl-inject-uncorrectable-errors',
'data': { 'path': 'str',
- 'errors': [ 'CXLUncorErrorRecord' ] }}
+ 'errors': [ 'CXLUncorErrorRecord' ] },
+ 'if': 'CONFIG_CXL_MEM_DEVICE'
+}
##
# @CxlCorErrorType:
@@ -235,7 +248,8 @@
'retry-threshold',
'cache-poison-received',
'mem-poison-received',
- 'physical']
+ 'physical'],
+ 'if': 'CONFIG_CXL_MEM_DEVICE'
}
##
@@ -254,5 +268,6 @@
{ 'command': 'cxl-inject-correctable-error',
'data': { 'path': 'str',
'type': 'CxlCorErrorType'
- }
+ },
+ 'if': 'CONFIG_CXL_MEM_DEVICE'
}
diff --git a/qapi/meson.build b/qapi/meson.build
index 73c3c8c31a..f5b3f36979 100644
--- a/qapi/meson.build
+++ b/qapi/meson.build
@@ -31,7 +31,7 @@ qapi_all_modules = [
'compat',
'control',
'crypto',
- 'cxl',
+ 'cxl-target',
'dump',
'error',
'introspect',
diff --git a/qapi/qapi-schema.json b/qapi/qapi-schema.json
index 079f2a402a..a79d84577f 100644
--- a/qapi/qapi-schema.json
+++ b/qapi/qapi-schema.json
@@ -95,4 +95,4 @@
{ 'include': 'pci.json' }
{ 'include': 'stats.json' }
{ 'include': 'virtio.json' }
-{ 'include': 'cxl.json' }
+{ 'include': 'cxl-target.json' }
--
2.37.2
>
> [...]
>
^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [PATCH v5 8/8] hw/mem/cxl_type3: Add CXL RAS Error Injection Support.
2023-02-23 14:27 ` Jonathan Cameron
@ 2023-02-24 17:37 ` Jonathan Cameron
2023-02-24 19:02 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 27+ messages in thread
From: Jonathan Cameron @ 2023-02-24 17:37 UTC (permalink / raw)
To: Markus Armbruster
Cc: Thomas Huth, Philippe Mathieu-Daudé,
qemu-devel, Michael Tsirkin, Ben Widawsky, linux-cxl, linuxarm,
Ira Weiny, Gregory Price, Mike Maslenkin, Dave Jiang,
Marc-André Lureau
On Thu, 23 Feb 2023 14:27:48 +0000
Jonathan Cameron <Jonathan.Cameron@huawei.com> wrote:
> On Thu, 23 Feb 2023 08:37:46 +0100
> Markus Armbruster <armbru@redhat.com> wrote:
>
> > Thomas Huth <thuth@redhat.com> writes:
> >
> > > On 22/02/2023 19.16, Philippe Mathieu-Daudé wrote:
> > >> +Thomas (meson) & Marc-André (conditional QAPI)
> > >
> > > + Markus
> > >
> > >> On 22/2/23 17:49, Jonathan Cameron wrote:
> >
> > [...]
> >
> > >>>>>> Doesn't these need
> > >>>>>>
> > >>>>>> 'if': 'CONFIG_CXL_MEM_DEVICE',
> > >>>>>>
> > >>>>>> ?
> > >>>>>
> > >>>>> If I make this change I get a bunch of
> > >>>>>
> > >>>>> ./qapi/qapi-types-cxl.h:18:13: error: attempt to use poisoned "CONFIG_CXL_MEM_DEVICE"
> > >>>>> 18 | #if defined(CONFIG_CXL_MEM_DEVICE)
> > >>>>
> > >>>> Err, I meant the generic CONFIG_CXL, not CONFIG_CXL_MEM_DEVICE.
> > >>>>
> > >>>>> It's a target specific define (I think) as built alongside PCI_EXPRESS
> > >>>>> Only CXL_ACPI is specifically included by x86 and arm64 (out of tree)
> > >>>>>
> > >>>>> To be honest though I don't fully understand the QEMU build system so the reason
> > >>>>> for the error might be wrong.
> > >>>>
> > >>>> You need to restrict to system emulation (the 'have_system' check):
> > >>>
> > >>> This doesn't help - still have
> > >>> attempt to used poisoned "CONFIG_CXL"
> > >
> > > Not sure how the QAPI generator works, but target specific config switches can only be used in target specific json files there, so that's machine-target.json and misc-target.json currently, as far as I know. Not sure how the QAPI generator distinguishes between common and target specific code, though ... just by the "-target" suffix? Maybe Markus or Marc-André can comment on that.
> >
> > Whenever you use a poisoned macro in a conditional, all the code
> > generated for this .json file (we call it a "QAPI schema module")
> > becomes target-dependent. The QAPI code generator itself is blissfully
> > unaware of this.
> >
> > Since target-dependent code needs to be compiled differently, the build
> > process needs to be know which modules are target-dependent. We do this
> > in one of the stupidest ways that could possibly work: a module is
> > target-dependent if its name ends with "-target". There are just two
> > right now: qapi/machine-target.json and qapi/misc-target.json.
> >
> > The logic resides in qapi/meson.build. Look for
> >
> > if module.endswith('-target')
>
> Thanks for all the pointers.
> >
> > Questions?
>
> Is it sensible to make the cxl stuff all target dependent and do the following?
> I like that we can get rid of the stubs if we do this but I'm sure there are
> disadvantages. Only alternative I can currently see is continue to have
> stubs and not make the qmp commands conditional on them doing anything useful.
>
> Note this is on top of my tree so involves more changes - I'll push it down
> into the relevant series.
I got too focused on getting it to build, and failed to realize that the below
change results in the new commands not being available anywhere. Oops.
Anyhow, my current conclusion is there isn't an easy way to make these conditional
so we should just keep the stubs for non CXL supporting builds.
If I'm wrong on that, let me know.
Thanks,
Jonathan
>
> From 551122103cf1f5bb4de8ee005482c72532181439 Mon Sep 17 00:00:00 2001
> From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Date: Thu, 23 Feb 2023 14:22:53 +0000
> Subject: [PATCH] hw/cxl: Make CXL compilation target specific
>
> ---
> hw/cxl/cxl-host-stubs.c | 15 --------
> hw/cxl/meson.build | 6 +---
> hw/mem/cxl_type3.c | 3 +-
> hw/mem/cxl_type3_stubs.c | 58 ------------------------------
> hw/mem/meson.build | 8 ++---
> qapi/{cxl.json => cxl-target.json} | 37 +++++++++++++------
> qapi/meson.build | 2 +-
> qapi/qapi-schema.json | 2 +-
> 8 files changed, 35 insertions(+), 96 deletions(-)
>
> diff --git a/hw/cxl/cxl-host-stubs.c b/hw/cxl/cxl-host-stubs.c
> deleted file mode 100644
> index cae4afcdde..0000000000
> --- a/hw/cxl/cxl-host-stubs.c
> +++ /dev/null
> @@ -1,15 +0,0 @@
> -/*
> - * CXL host parameter parsing routine stubs
> - *
> - * Copyright (c) 2022 Huawei
> - */
> -#include "qemu/osdep.h"
> -#include "qapi/error.h"
> -#include "hw/cxl/cxl.h"
> -#include "hw/cxl/cxl_host.h"
> -
> -void cxl_fmws_link_targets(CXLState *stat, Error **errp) {};
> -void cxl_machine_init(Object *obj, CXLState *state) {};
> -void cxl_hook_up_pxb_registers(PCIBus *bus, CXLState *state, Error **errp) {};
> -
> -const MemoryRegionOps cfmws_ops;
> diff --git a/hw/cxl/meson.build b/hw/cxl/meson.build
> index 99ee564ce8..99eeb84268 100644
> --- a/hw/cxl/meson.build
> +++ b/hw/cxl/meson.build
> @@ -1,4 +1,4 @@
> -softmmu_ss.add(when: 'CONFIG_CXL',
> +specific_ss.add(when: 'CONFIG_CXL',
> if_true: files(
> 'cxl-component-utils.c',
> 'cxl-device-utils.c',
> @@ -8,9 +8,5 @@ softmmu_ss.add(when: 'CONFIG_CXL',
> 'cxl-events.c',
> 'cxl-cpmu.c',
> 'switch-mailbox-cci.c',
> - ),
> - if_false: files(
> - 'cxl-host-stubs.c',
> ))
>
> -softmmu_ss.add(when: 'CONFIG_ALL', if_true: files('cxl-host-stubs.c'))
> diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
> index 334ce92f5e..cf20fb81ff 100644
> --- a/hw/mem/cxl_type3.c
> +++ b/hw/mem/cxl_type3.c
> @@ -1,7 +1,8 @@
> #include "qemu/osdep.h"
> +#include CONFIG_DEVICES
> #include "qemu/units.h"
> #include "qemu/error-report.h"
> -#include "qapi/qapi-commands-cxl.h"
> +#include "qapi/qapi-commands-cxl-target.h"
> #include "hw/mem/memory-device.h"
> #include "hw/mem/pc-dimm.h"
> #include "hw/pci/pci.h"
> diff --git a/hw/mem/cxl_type3_stubs.c b/hw/mem/cxl_type3_stubs.c
> deleted file mode 100644
> index 2196bd841c..0000000000
> --- a/hw/mem/cxl_type3_stubs.c
> +++ /dev/null
> @@ -1,58 +0,0 @@
> -
> -#include "qemu/osdep.h"
> -#include "qapi/error.h"
> -#include "qapi/qapi-commands-cxl.h"
> -
> -void qmp_cxl_inject_gen_media_event(const char *path, CxlEventLog log,
> - uint8_t flags, uint64_t physaddr,
> - uint8_t descriptor, uint8_t type,
> - uint8_t transaction_type,
> - bool has_channel, uint8_t channel,
> - bool has_rank, uint8_t rank,
> - bool has_device, uint32_t device,
> - const char *component_id,
> - Error **errp) {}
> -
> -void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log, uint8_t flags,
> - uint64_t physaddr, uint8_t descriptor,
> - uint8_t type, uint8_t transaction_type,
> - bool has_channel, uint8_t channel,
> - bool has_rank, uint8_t rank,
> - bool has_nibble_mask, uint32_t nibble_mask,
> - bool has_bank_group, uint8_t bank_group,
> - bool has_bank, uint8_t bank,
> - bool has_row, uint32_t row,
> - bool has_column, uint16_t column,
> - bool has_correction_mask, uint64List *correction_mask,
> - Error **errp) {}
> -
> -void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log,
> - uint8_t flags, uint8_t type,
> - uint8_t health_status,
> - uint8_t media_status,
> - uint8_t additional_status,
> - uint8_t life_used,
> - int16_t temperature,
> - uint32_t dirty_shutdown_count,
> - uint32_t corrected_volatile_error_count,
> - uint32_t corrected_persistent_error_count,
> - Error **errp) {}
> -
> -void qmp_cxl_inject_poison(const char *path, uint64_t start, uint64_t length,
> - Error **errp)
> -{
> - error_setg(errp, "CXL Type 3 support is not compiled in");
> -}
> -
> -void qmp_cxl_inject_uncorrectable_errors(const char *path,
> - CXLUncorErrorRecordList *errors,
> - Error **errp)
> -{
> - error_setg(errp, "CXL Type 3 support is not compiled in");
> -}
> -
> -void qmp_cxl_inject_correctable_error(const char *path, CxlCorErrorType type,
> - Error **errp)
> -{
> - error_setg(errp, "CXL Type 3 support is not compiled in");
> -}
> diff --git a/hw/mem/meson.build b/hw/mem/meson.build
> index 56c2618b84..2bdd24512e 100644
> --- a/hw/mem/meson.build
> +++ b/hw/mem/meson.build
> @@ -3,10 +3,10 @@ mem_ss.add(files('memory-device.c'))
> mem_ss.add(when: 'CONFIG_DIMM', if_true: files('pc-dimm.c'))
> mem_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_mc.c'))
> mem_ss.add(when: 'CONFIG_NVDIMM', if_true: files('nvdimm.c'))
> -mem_ss.add(when: 'CONFIG_CXL_MEM_DEVICE', if_true: files('cxl_type3.c'))
> -softmmu_ss.add(when: 'CONFIG_CXL_MEM_DEVICE', if_false: files('cxl_type3_stubs.c'))
> -softmmu_ss.add(when: 'CONFIG_ALL', if_true: files('cxl_type3_stubs.c'))
> +specific_ss.add(when: 'CONFIG_CXL_MEM_DEVICE', if_true: files('cxl_type3.c'))
> +#specific_ss.add(when: 'CONFIG_CXL_MEM_DEVICE', if_false: files('cxl_type3_stubs.c'))
> +#specific_ss.add(when: 'CONFIG_ALL', if_true: files('cxl_type3_stubs.c'))
>
> -softmmu_ss.add_all(when: 'CONFIG_MEM_DEVICE', if_true: mem_ss)
> +specific_ss.add_all(when: 'CONFIG_MEM_DEVICE', if_true: mem_ss)
>
> softmmu_ss.add(when: 'CONFIG_SPARSE_MEM', if_true: files('sparse-mem.c'))
> diff --git a/qapi/cxl.json b/qapi/cxl-target.json
> similarity index 94%
> rename from qapi/cxl.json
> rename to qapi/cxl-target.json
> index 4c029f2807..b3aecea4f0 100644
> --- a/qapi/cxl.json
> +++ b/qapi/cxl-target.json
> @@ -21,7 +21,8 @@
> 'warning',
> 'failure',
> 'fatal'
> - ]
> + ],
> + 'if': 'CONFIG_CXL_MEM_DEVICE'
> }
>
> ##
> @@ -49,7 +50,9 @@
> 'type': 'uint8', 'transaction-type': 'uint8',
> '*channel': 'uint8', '*rank': 'uint8',
> '*device': 'uint32', '*component-id': 'str'
> - }}
> + },
> + 'if': 'CONFIG_CXL_MEM_DEVICE'
> + }
>
> ##
> # @cxl-inject-dram-event:
> @@ -82,7 +85,9 @@
> '*channel': 'uint8', '*rank': 'uint8', '*nibble-mask': 'uint32',
> '*bank-group': 'uint8', '*bank': 'uint8', '*row': 'uint32',
> '*column': 'uint16', '*correction-mask': [ 'uint64' ]
> - }}
> + },
> + 'if': 'CONFIG_CXL_MEM_DEVICE'
> +}
>
> ##
> # @cxl-inject-memory-module-event:
> @@ -115,7 +120,9 @@
> 'dirty-shutdown-count': 'uint32',
> 'corrected-volatile-error-count': 'uint32',
> 'corrected-persistent-error-count': 'uint32'
> - }}
> + },
> + 'if': 'CONFIG_CXL_MEM_DEVICE'
> +}
>
> ##
> # @cxl-inject-poison:
> @@ -133,7 +140,9 @@
> # Since: 8.0
> ##
> { 'command': 'cxl-inject-poison',
> - 'data': { 'path': 'str', 'start': 'uint64', 'length': 'uint64' }}
> + 'data': { 'path': 'str', 'start': 'uint64', 'length': 'uint64' },
> + 'if': 'CONFIG_CXL_MEM_DEVICE'
> +}
>
> ##
> # @CxlUncorErrorType:
> @@ -179,8 +188,9 @@
> 'internal',
> 'cxl-ide-tx',
> 'cxl-ide-rx'
> - ]
> - }
> + ],
> + 'if': 'CONFIG_CXL_MEM_DEVICE'
> +}
>
> ##
> # @CXLUncorErrorRecord:
> @@ -196,7 +206,8 @@
> 'data': {
> 'type': 'CxlUncorErrorType',
> 'header': [ 'uint32' ]
> - }
> + },
> + 'if': 'CONFIG_CXL_MEM_DEVICE'
> }
>
> ##
> @@ -212,7 +223,9 @@
> ##
> { 'command': 'cxl-inject-uncorrectable-errors',
> 'data': { 'path': 'str',
> - 'errors': [ 'CXLUncorErrorRecord' ] }}
> + 'errors': [ 'CXLUncorErrorRecord' ] },
> + 'if': 'CONFIG_CXL_MEM_DEVICE'
> +}
>
> ##
> # @CxlCorErrorType:
> @@ -235,7 +248,8 @@
> 'retry-threshold',
> 'cache-poison-received',
> 'mem-poison-received',
> - 'physical']
> + 'physical'],
> + 'if': 'CONFIG_CXL_MEM_DEVICE'
> }
>
> ##
> @@ -254,5 +268,6 @@
> { 'command': 'cxl-inject-correctable-error',
> 'data': { 'path': 'str',
> 'type': 'CxlCorErrorType'
> - }
> + },
> + 'if': 'CONFIG_CXL_MEM_DEVICE'
> }
> diff --git a/qapi/meson.build b/qapi/meson.build
> index 73c3c8c31a..f5b3f36979 100644
> --- a/qapi/meson.build
> +++ b/qapi/meson.build
> @@ -31,7 +31,7 @@ qapi_all_modules = [
> 'compat',
> 'control',
> 'crypto',
> - 'cxl',
> + 'cxl-target',
> 'dump',
> 'error',
> 'introspect',
> diff --git a/qapi/qapi-schema.json b/qapi/qapi-schema.json
> index 079f2a402a..a79d84577f 100644
> --- a/qapi/qapi-schema.json
> +++ b/qapi/qapi-schema.json
> @@ -95,4 +95,4 @@
> { 'include': 'pci.json' }
> { 'include': 'stats.json' }
> { 'include': 'virtio.json' }
> -{ 'include': 'cxl.json' }
> +{ 'include': 'cxl-target.json' }
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v5 8/8] hw/mem/cxl_type3: Add CXL RAS Error Injection Support.
2023-02-23 14:27 ` Jonathan Cameron
2023-02-24 17:37 ` Jonathan Cameron
@ 2023-02-24 19:02 ` Philippe Mathieu-Daudé
2023-02-27 9:40 ` Markus Armbruster
1 sibling, 1 reply; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-02-24 19:02 UTC (permalink / raw)
To: Jonathan Cameron, Thomas Huth
Cc: qemu-devel, Michael Tsirkin, Ben Widawsky, linux-cxl, linuxarm,
Ira Weiny, Markus Armbruster, Gregory Price, Mike Maslenkin,
Dave Jiang, Marc-André Lureau
On 23/2/23 15:27, Jonathan Cameron wrote:
> On Thu, 23 Feb 2023 08:37:46 +0100
> Markus Armbruster <armbru@redhat.com> wrote:
>
>> Thomas Huth <thuth@redhat.com> writes:
>>
>>> On 22/02/2023 19.16, Philippe Mathieu-Daudé wrote:
>>>> +Thomas (meson) & Marc-André (conditional QAPI)
>>>
>>> + Markus
>>>
>>>> On 22/2/23 17:49, Jonathan Cameron wrote:
>>
>> [...]
>>
>>>>>>>> Doesn't these need
>>>>>>>>
>>>>>>>> 'if': 'CONFIG_CXL_MEM_DEVICE',
>>>>>>>>
>>>>>>>> ?
>>>>>>>
>>>>>>> If I make this change I get a bunch of
>>>>>>>
>>>>>>> ./qapi/qapi-types-cxl.h:18:13: error: attempt to use poisoned "CONFIG_CXL_MEM_DEVICE"
>>>>>>> 18 | #if defined(CONFIG_CXL_MEM_DEVICE)
>>>>>>
>>>>>> Err, I meant the generic CONFIG_CXL, not CONFIG_CXL_MEM_DEVICE.
>>>>>>
>>>>>>> It's a target specific define (I think) as built alongside PCI_EXPRESS
>>>>>>> Only CXL_ACPI is specifically included by x86 and arm64 (out of tree)
>>>>>>>
>>>>>>> To be honest though I don't fully understand the QEMU build system so the reason
>>>>>>> for the error might be wrong.
>>>>>>
>>>>>> You need to restrict to system emulation (the 'have_system' check):
>>>>>
>>>>> This doesn't help - still have
>>>>> attempt to used poisoned "CONFIG_CXL"
>>>
>>> Not sure how the QAPI generator works, but target specific config switches can only be used in target specific json files there, so that's machine-target.json and misc-target.json currently, as far as I know. Not sure how the QAPI generator distinguishes between common and target specific code, though ... just by the "-target" suffix? Maybe Markus or Marc-André can comment on that.
>>
>> Whenever you use a poisoned macro in a conditional, all the code
>> generated for this .json file (we call it a "QAPI schema module")
>> becomes target-dependent. The QAPI code generator itself is blissfully
>> unaware of this.
>>
>> Since target-dependent code needs to be compiled differently, the build
>> process needs to be know which modules are target-dependent. We do this
>> in one of the stupidest ways that could possibly work: a module is
>> target-dependent if its name ends with "-target". There are just two
>> right now: qapi/machine-target.json and qapi/misc-target.json.
>>
>> The logic resides in qapi/meson.build. Look for
>>
>> if module.endswith('-target')
>
> Thanks for all the pointers.
>>
>> Questions?
>
> Is it sensible to make the cxl stuff all target dependent and do the following?
> I like that we can get rid of the stubs if we do this but I'm sure there are
> disadvantages. Only alternative I can currently see is continue to have
> stubs and not make the qmp commands conditional on them doing anything useful.
I still don't understand what is the target-dependent part of CXL.
IIUC CXL depends on PCIe which isn't target dependent.
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v5 8/8] hw/mem/cxl_type3: Add CXL RAS Error Injection Support.
2023-02-24 19:02 ` Philippe Mathieu-Daudé
@ 2023-02-27 9:40 ` Markus Armbruster
0 siblings, 0 replies; 27+ messages in thread
From: Markus Armbruster @ 2023-02-27 9:40 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Jonathan Cameron, Thomas Huth, qemu-devel, Michael Tsirkin,
Ben Widawsky, linux-cxl, linuxarm, Ira Weiny, Gregory Price,
Mike Maslenkin, Dave Jiang, Marc-André Lureau
Philippe Mathieu-Daudé <philmd@linaro.org> writes:
> On 23/2/23 15:27, Jonathan Cameron wrote:
>> On Thu, 23 Feb 2023 08:37:46 +0100
>> Markus Armbruster <armbru@redhat.com> wrote:
>>> Whenever you use a poisoned macro in a conditional, all the code
>>> generated for this .json file (we call it a "QAPI schema module")
>>> becomes target-dependent. The QAPI code generator itself is blissfully
>>> unaware of this.
>>>
>>> Since target-dependent code needs to be compiled differently, the build
>>> process needs to be know which modules are target-dependent. We do this
>>> in one of the stupidest ways that could possibly work: a module is
>>> target-dependent if its name ends with "-target". There are just two
>>> right now: qapi/machine-target.json and qapi/misc-target.json.
>>>
>>> The logic resides in qapi/meson.build. Look for
>>>
>>> if module.endswith('-target')
>>
>> Thanks for all the pointers.
>>
>>> Questions?
>>>
>> Is it sensible to make the cxl stuff all target dependent and do the following?
>> I like that we can get rid of the stubs if we do this but I'm sure there are
>> disadvantages. Only alternative I can currently see is continue to have
>> stubs and not make the qmp commands conditional on them doing anything useful.
>
> I still don't understand what is the target-dependent part of CXL.
>
> IIUC CXL depends on PCIe which isn't target dependent.
As far as I can tell, the target-dependent part of CXL is the macro
CONFIG_CXL :)
Consider a device model implemented in perfectly target-independent
code, to be linked only into some qemu-system-TARGET. How do we do
that?
We put a 'config FOO' section in the appropriate Kconfig, and select it
from the target's Kconfig for the targets that want it. We add device
model sources to Meson source set softmmu_ss when CONFIG_FOO.
This puts CONFIG_FOO=y into the TARGET-softmmu-config-devices.mak, and
#define CONFIG_FOO 1 into TARGET-softmmu-config-devices.h. It also puts
#pragma GCC poison CONFIG_FOO into config-poison.h.
Note the two CONFIG_FOO have subtly different meaning:
* The make variable means "there is an enabled target that has FOO
enabled". It gets propagated to Meson.
* The C macro means "the current target has FOO enabled". It therefore
must not be used in target-independent code. That's why we poison it
in config-poison.h.
Note that the device model code has no use for C macro CONFIG_FOO. It
remains target-independent as it should.
Now consider how to have the QAPI schema provide something for FOO.
If we make it a QAPI schema module of its own, we can arrange for it to
be linked only into the qemu-system-TARGET that have the device model,
just like the device model code. We haven't tried this for individual
devices, only for whole subsystems like PCI.
If we don't make it a module of its own, we have two choices:
* We use 'if': 'CONFIG_FOO'. This is actually the C macro. The module
becomes target-dependent. We compile the code generated for the
module separately for each target.
* We make it unconditional. The module can remain target-independent.
The code generated for FOO's QAPI schema is linked unconditionally,
even when the target doesn't need it. Any references to handwritten
FOO code need to be satisfied with stubs.
I dislike both. Existing usage seems to prefer "unconditional schema".
Sticking to that is okay.
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v5 8/8] hw/mem/cxl_type3: Add CXL RAS Error Injection Support.
2023-02-21 15:21 ` [PATCH v5 8/8] hw/mem/cxl_type3: Add CXL RAS Error Injection Support Jonathan Cameron
2023-02-21 15:48 ` Dave Jiang
2023-02-21 22:15 ` Philippe Mathieu-Daudé
@ 2023-10-27 4:54 ` Markus Armbruster
2023-10-31 17:55 ` Jonathan Cameron
2 siblings, 1 reply; 27+ messages in thread
From: Markus Armbruster @ 2023-10-27 4:54 UTC (permalink / raw)
To: Jonathan Cameron
Cc: qemu-devel, Michael Tsirkin, Ben Widawsky, linux-cxl, linuxarm,
Ira Weiny, Gregory Price, Philippe Mathieu-Daudé,
Mike Maslenkin, Dave Jiang
I'm trying to fill in QMP documentation holes, and found one in commit
415442a1b4a (this patch). Details inline.
Jonathan Cameron <Jonathan.Cameron@huawei.com> writes:
> CXL uses PCI AER Internal errors to signal to the host that an error has
> occurred. The host can then read more detailed status from the CXL RAS
> capability.
>
> For uncorrectable errors: support multiple injection in one operation
> as this is needed to reliably test multiple header logging support in an
> OS. The equivalent feature doesn't exist for correctable errors, so only
> one error need be injected at a time.
>
> Note:
> - Header content needs to be manually specified in a fashion that
> matches the specification for what can be in the header for each
> error type.
>
> Injection via QMP:
> { "execute": "qmp_capabilities" }
> ...
> { "execute": "cxl-inject-uncorrectable-errors",
> "arguments": {
> "path": "/machine/peripheral/cxl-pmem0",
> "errors": [
> {
> "type": "cache-address-parity",
> "header": [ 3, 4]
> },
> {
> "type": "cache-data-parity",
> "header": [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31]
> },
> {
> "type": "internal",
> "header": [ 1, 2, 4]
> }
> ]
> }}
> ...
> { "execute": "cxl-inject-correctable-error",
> "arguments": {
> "path": "/machine/peripheral/cxl-pmem0",
> "type": "physical"
> } }
>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
[...]
> diff --git a/qapi/cxl.json b/qapi/cxl.json
> new file mode 100644
> index 0000000000..ac7e167fa2
> --- /dev/null
> +++ b/qapi/cxl.json
> @@ -0,0 +1,118 @@
> +# -*- Mode: Python -*-
> +# vim: filetype=python
> +
> +##
> +# = CXL devices
> +##
> +
> +##
> +# @CxlUncorErrorType:
> +#
> +# Type of uncorrectable CXL error to inject. These errors are reported via
> +# an AER uncorrectable internal error with additional information logged at
> +# the CXL device.
> +#
> +# @cache-data-parity: Data error such as data parity or data ECC error CXL.cache
> +# @cache-address-parity: Address parity or other errors associated with the
> +# address field on CXL.cache
> +# @cache-be-parity: Byte enable parity or other byte enable errors on CXL.cache
> +# @cache-data-ecc: ECC error on CXL.cache
> +# @mem-data-parity: Data error such as data parity or data ECC error on CXL.mem
> +# @mem-address-parity: Address parity or other errors associated with the
> +# address field on CXL.mem
> +# @mem-be-parity: Byte enable parity or other byte enable errors on CXL.mem.
> +# @mem-data-ecc: Data ECC error on CXL.mem.
> +# @reinit-threshold: REINIT threshold hit.
> +# @rsvd-encoding: Received unrecognized encoding.
> +# @poison-received: Received poison from the peer.
> +# @receiver-overflow: Buffer overflows (first 3 bits of header log indicate which)
> +# @internal: Component specific error
> +# @cxl-ide-tx: Integrity and data encryption tx error.
> +# @cxl-ide-rx: Integrity and data encryption rx error.
> +##
> +
> +{ 'enum': 'CxlUncorErrorType',
> + 'data': ['cache-data-parity',
> + 'cache-address-parity',
> + 'cache-be-parity',
> + 'cache-data-ecc',
> + 'mem-data-parity',
> + 'mem-address-parity',
> + 'mem-be-parity',
> + 'mem-data-ecc',
> + 'reinit-threshold',
> + 'rsvd-encoding',
> + 'poison-received',
> + 'receiver-overflow',
> + 'internal',
> + 'cxl-ide-tx',
> + 'cxl-ide-rx'
> + ]
> + }
> +
> +##
> +# @CXLUncorErrorRecord:
> +#
> +# Record of a single error including header log.
> +#
> +# @type: Type of error
> +# @header: 16 DWORD of header.
> +##
> +{ 'struct': 'CXLUncorErrorRecord',
> + 'data': {
> + 'type': 'CxlUncorErrorType',
> + 'header': [ 'uint32' ]
> + }
> +}
> +
> +##
> +# @cxl-inject-uncorrectable-errors:
> +#
> +# Command to allow injection of multiple errors in one go. This allows testing
> +# of multiple header log handling in the OS.
> +#
> +# @path: CXL Type 3 device canonical QOM path
> +# @errors: Errors to inject
> +##
> +{ 'command': 'cxl-inject-uncorrectable-errors',
> + 'data': { 'path': 'str',
> + 'errors': [ 'CXLUncorErrorRecord' ] }}
> +
> +##
> +# @CxlCorErrorType:
> +#
> +# Type of CXL correctable error to inject
> +#
> +# @cache-data-ecc: Data ECC error on CXL.cache
> +# @mem-data-ecc: Data ECC error on CXL.mem
Missing:
# @retry-threshold: ...
I need suitable description text. Can you help me?
> +# @crc-threshold: Component specific and applicable to 68 byte Flit mode only.
> +# @cache-poison-received: Received poison from a peer on CXL.cache.
> +# @mem-poison-received: Received poison from a peer on CXL.mem
> +# @physical: Received error indication from the physical layer.
> +##
> +{ 'enum': 'CxlCorErrorType',
> + 'data': ['cache-data-ecc',
> + 'mem-data-ecc',
> + 'crc-threshold',
> + 'retry-threshold',
> + 'cache-poison-received',
> + 'mem-poison-received',
> + 'physical']
> +}
> +
> +##
> +# @cxl-inject-correctable-error:
> +#
> +# Command to inject a single correctable error. Multiple error injection
> +# of this error type is not interesting as there is no associated header log.
> +# These errors are reported via AER as a correctable internal error, with
> +# additional detail available from the CXL device.
> +#
> +# @path: CXL Type 3 device canonical QOM path
> +# @type: Type of error.
> +##
> +{ 'command': 'cxl-inject-correctable-error',
> + 'data': { 'path': 'str',
> + 'type': 'CxlCorErrorType'
> + }
> +}
[...]
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v5 8/8] hw/mem/cxl_type3: Add CXL RAS Error Injection Support.
2023-10-27 4:54 ` Markus Armbruster
@ 2023-10-31 17:55 ` Jonathan Cameron
2023-11-02 6:47 ` Markus Armbruster
0 siblings, 1 reply; 27+ messages in thread
From: Jonathan Cameron @ 2023-10-31 17:55 UTC (permalink / raw)
To: Markus Armbruster
Cc: qemu-devel, Michael Tsirkin, Ben Widawsky, linux-cxl, linuxarm,
Ira Weiny, Gregory Price, Philippe Mathieu-Daudé,
Mike Maslenkin, Dave Jiang
On Fri, 27 Oct 2023 06:54:39 +0200
Markus Armbruster <armbru@redhat.com> wrote:
> I'm trying to fill in QMP documentation holes, and found one in commit
> 415442a1b4a (this patch). Details inline.
>
> Jonathan Cameron <Jonathan.Cameron@huawei.com> writes:
>
> > CXL uses PCI AER Internal errors to signal to the host that an error has
> > occurred. The host can then read more detailed status from the CXL RAS
> > capability.
> >
> > For uncorrectable errors: support multiple injection in one operation
> > as this is needed to reliably test multiple header logging support in an
> > OS. The equivalent feature doesn't exist for correctable errors, so only
> > one error need be injected at a time.
> >
> > Note:
> > - Header content needs to be manually specified in a fashion that
> > matches the specification for what can be in the header for each
> > error type.
> >
> > Injection via QMP:
> > { "execute": "qmp_capabilities" }
> > ...
> > { "execute": "cxl-inject-uncorrectable-errors",
> > "arguments": {
> > "path": "/machine/peripheral/cxl-pmem0",
> > "errors": [
> > {
> > "type": "cache-address-parity",
> > "header": [ 3, 4]
> > },
> > {
> > "type": "cache-data-parity",
> > "header": [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31]
> > },
> > {
> > "type": "internal",
> > "header": [ 1, 2, 4]
> > }
> > ]
> > }}
> > ...
> > { "execute": "cxl-inject-correctable-error",
> > "arguments": {
> > "path": "/machine/peripheral/cxl-pmem0",
> > "type": "physical"
> > } }
> >
> > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>
> [...]
>
> > diff --git a/qapi/cxl.json b/qapi/cxl.json
> > new file mode 100644
> > index 0000000000..ac7e167fa2
> > --- /dev/null
> > +++ b/qapi/cxl.json
> > @@ -0,0 +1,118 @@
> > +# -*- Mode: Python -*-
> > +# vim: filetype=python
> > +
> > +##
> > +# = CXL devices
> > +##
> > +
> > +##
> > +# @CxlUncorErrorType:
> > +#
> > +# Type of uncorrectable CXL error to inject. These errors are reported via
> > +# an AER uncorrectable internal error with additional information logged at
> > +# the CXL device.
> > +#
> > +# @cache-data-parity: Data error such as data parity or data ECC error CXL.cache
> > +# @cache-address-parity: Address parity or other errors associated with the
> > +# address field on CXL.cache
> > +# @cache-be-parity: Byte enable parity or other byte enable errors on CXL.cache
> > +# @cache-data-ecc: ECC error on CXL.cache
> > +# @mem-data-parity: Data error such as data parity or data ECC error on CXL.mem
> > +# @mem-address-parity: Address parity or other errors associated with the
> > +# address field on CXL.mem
> > +# @mem-be-parity: Byte enable parity or other byte enable errors on CXL.mem.
> > +# @mem-data-ecc: Data ECC error on CXL.mem.
> > +# @reinit-threshold: REINIT threshold hit.
> > +# @rsvd-encoding: Received unrecognized encoding.
> > +# @poison-received: Received poison from the peer.
> > +# @receiver-overflow: Buffer overflows (first 3 bits of header log indicate which)
> > +# @internal: Component specific error
> > +# @cxl-ide-tx: Integrity and data encryption tx error.
> > +# @cxl-ide-rx: Integrity and data encryption rx error.
> > +##
> > +
> > +{ 'enum': 'CxlUncorErrorType',
> > + 'data': ['cache-data-parity',
> > + 'cache-address-parity',
> > + 'cache-be-parity',
> > + 'cache-data-ecc',
> > + 'mem-data-parity',
> > + 'mem-address-parity',
> > + 'mem-be-parity',
> > + 'mem-data-ecc',
> > + 'reinit-threshold',
> > + 'rsvd-encoding',
> > + 'poison-received',
> > + 'receiver-overflow',
> > + 'internal',
> > + 'cxl-ide-tx',
> > + 'cxl-ide-rx'
> > + ]
> > + }
> > +
> > +##
> > +# @CXLUncorErrorRecord:
> > +#
> > +# Record of a single error including header log.
> > +#
> > +# @type: Type of error
> > +# @header: 16 DWORD of header.
> > +##
> > +{ 'struct': 'CXLUncorErrorRecord',
> > + 'data': {
> > + 'type': 'CxlUncorErrorType',
> > + 'header': [ 'uint32' ]
> > + }
> > +}
> > +
> > +##
> > +# @cxl-inject-uncorrectable-errors:
> > +#
> > +# Command to allow injection of multiple errors in one go. This allows testing
> > +# of multiple header log handling in the OS.
> > +#
> > +# @path: CXL Type 3 device canonical QOM path
> > +# @errors: Errors to inject
> > +##
> > +{ 'command': 'cxl-inject-uncorrectable-errors',
> > + 'data': { 'path': 'str',
> > + 'errors': [ 'CXLUncorErrorRecord' ] }}
> > +
> > +##
> > +# @CxlCorErrorType:
> > +#
> > +# Type of CXL correctable error to inject
> > +#
> > +# @cache-data-ecc: Data ECC error on CXL.cache
> > +# @mem-data-ecc: Data ECC error on CXL.mem
>
> Missing:
>
> # @retry-threshold: ...
>
> I need suitable description text. Can you help me?
Spec says:
"Retry Threshold Hit. (NUM_RETRY>=MAX_NUM_RETRY).
See Section 4.2.8.5.1 for the definitions of NUM_RETRY and MAX_NUM_RETRY."
Following the reference:
"NUM_RETRY: This counter is used to count the number of RETRY.Req requests
sent to retry the same flit. The counter remains enabled during the whole retry
sequence (state is not RETRY_LOCAL_NORMAL). It is reset to 0 at initialization. It is
also reset to 0 when a RETRY.Ack sequence is received with the Empty bit set or
whenever the LRSM state is RETRY_LOCAL_NORMAL and an error-free retryable flit
is received. The counter is incremented whenever the LRSM state changes from
RETRY_LLRREQ to RETRY_LOCAL_IDLE. If the counter reaches a threshold (called
MAX_NUM_RETRY), then the local retry state machine transitions to the
RETRY_PHY_REINIT. The NUM_RETRY counter is also reset when the Physical layer
exits from LTSSM recovery state (the LRSM transition through RETRY_PHY_REINIT
to RETRY_LLRREQ)."
So based on my failure to understand much of that beyond it has something
to do with low level retries, maybe just
"Number of times the retry threshold was hit."
Thanks for tidying this up!
?
>
> > +# @crc-threshold: Component specific and applicable to 68 byte Flit mode only.
> > +# @cache-poison-received: Received poison from a peer on CXL.cache.
> > +# @mem-poison-received: Received poison from a peer on CXL.mem
> > +# @physical: Received error indication from the physical layer.
> > +##
> > +{ 'enum': 'CxlCorErrorType',
> > + 'data': ['cache-data-ecc',
> > + 'mem-data-ecc',
> > + 'crc-threshold',
> > + 'retry-threshold',
> > + 'cache-poison-received',
> > + 'mem-poison-received',
> > + 'physical']
> > +}
> > +
> > +##
> > +# @cxl-inject-correctable-error:
> > +#
> > +# Command to inject a single correctable error. Multiple error injection
> > +# of this error type is not interesting as there is no associated header log.
> > +# These errors are reported via AER as a correctable internal error, with
> > +# additional detail available from the CXL device.
> > +#
> > +# @path: CXL Type 3 device canonical QOM path
> > +# @type: Type of error.
> > +##
> > +{ 'command': 'cxl-inject-correctable-error',
> > + 'data': { 'path': 'str',
> > + 'type': 'CxlCorErrorType'
> > + }
> > +}
>
> [...]
>
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v5 8/8] hw/mem/cxl_type3: Add CXL RAS Error Injection Support.
2023-10-31 17:55 ` Jonathan Cameron
@ 2023-11-02 6:47 ` Markus Armbruster
0 siblings, 0 replies; 27+ messages in thread
From: Markus Armbruster @ 2023-11-02 6:47 UTC (permalink / raw)
To: Jonathan Cameron
Cc: qemu-devel, Michael Tsirkin, Ben Widawsky, linux-cxl, linuxarm,
Ira Weiny, Gregory Price, Philippe Mathieu-Daudé,
Mike Maslenkin, Dave Jiang
Jonathan Cameron <Jonathan.Cameron@Huawei.com> writes:
> On Fri, 27 Oct 2023 06:54:39 +0200
> Markus Armbruster <armbru@redhat.com> wrote:
>
>> I'm trying to fill in QMP documentation holes, and found one in commit
>> 415442a1b4a (this patch). Details inline.
>>
>> Jonathan Cameron <Jonathan.Cameron@huawei.com> writes:
>>
>> > CXL uses PCI AER Internal errors to signal to the host that an error has
>> > occurred. The host can then read more detailed status from the CXL RAS
>> > capability.
>> >
>> > For uncorrectable errors: support multiple injection in one operation
>> > as this is needed to reliably test multiple header logging support in an
>> > OS. The equivalent feature doesn't exist for correctable errors, so only
>> > one error need be injected at a time.
>> >
>> > Note:
>> > - Header content needs to be manually specified in a fashion that
>> > matches the specification for what can be in the header for each
>> > error type.
>> >
>> > Injection via QMP:
>> > { "execute": "qmp_capabilities" }
>> > ...
>> > { "execute": "cxl-inject-uncorrectable-errors",
>> > "arguments": {
>> > "path": "/machine/peripheral/cxl-pmem0",
>> > "errors": [
>> > {
>> > "type": "cache-address-parity",
>> > "header": [ 3, 4]
>> > },
>> > {
>> > "type": "cache-data-parity",
>> > "header": [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31]
>> > },
>> > {
>> > "type": "internal",
>> > "header": [ 1, 2, 4]
>> > }
>> > ]
>> > }}
>> > ...
>> > { "execute": "cxl-inject-correctable-error",
>> > "arguments": {
>> > "path": "/machine/peripheral/cxl-pmem0",
>> > "type": "physical"
>> > } }
>> >
>> > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>>
>> [...]
>>
>> > diff --git a/qapi/cxl.json b/qapi/cxl.json
>> > new file mode 100644
>> > index 0000000000..ac7e167fa2
>> > --- /dev/null
>> > +++ b/qapi/cxl.json
>> > @@ -0,0 +1,118 @@
>> > +# -*- Mode: Python -*-
>> > +# vim: filetype=python
>> > +
>> > +##
>> > +# = CXL devices
>> > +##
>> > +
>> > +##
>> > +# @CxlUncorErrorType:
>> > +#
>> > +# Type of uncorrectable CXL error to inject. These errors are reported via
>> > +# an AER uncorrectable internal error with additional information logged at
>> > +# the CXL device.
>> > +#
>> > +# @cache-data-parity: Data error such as data parity or data ECC error CXL.cache
>> > +# @cache-address-parity: Address parity or other errors associated with the
>> > +# address field on CXL.cache
>> > +# @cache-be-parity: Byte enable parity or other byte enable errors on CXL.cache
>> > +# @cache-data-ecc: ECC error on CXL.cache
>> > +# @mem-data-parity: Data error such as data parity or data ECC error on CXL.mem
>> > +# @mem-address-parity: Address parity or other errors associated with the
>> > +# address field on CXL.mem
>> > +# @mem-be-parity: Byte enable parity or other byte enable errors on CXL.mem.
>> > +# @mem-data-ecc: Data ECC error on CXL.mem.
>> > +# @reinit-threshold: REINIT threshold hit.
>> > +# @rsvd-encoding: Received unrecognized encoding.
>> > +# @poison-received: Received poison from the peer.
>> > +# @receiver-overflow: Buffer overflows (first 3 bits of header log indicate which)
>> > +# @internal: Component specific error
>> > +# @cxl-ide-tx: Integrity and data encryption tx error.
>> > +# @cxl-ide-rx: Integrity and data encryption rx error.
>> > +##
>> > +
>> > +{ 'enum': 'CxlUncorErrorType',
>> > + 'data': ['cache-data-parity',
>> > + 'cache-address-parity',
>> > + 'cache-be-parity',
>> > + 'cache-data-ecc',
>> > + 'mem-data-parity',
>> > + 'mem-address-parity',
>> > + 'mem-be-parity',
>> > + 'mem-data-ecc',
>> > + 'reinit-threshold',
>> > + 'rsvd-encoding',
>> > + 'poison-received',
>> > + 'receiver-overflow',
>> > + 'internal',
>> > + 'cxl-ide-tx',
>> > + 'cxl-ide-rx'
>> > + ]
>> > + }
>> > +
>> > +##
>> > +# @CXLUncorErrorRecord:
>> > +#
>> > +# Record of a single error including header log.
>> > +#
>> > +# @type: Type of error
>> > +# @header: 16 DWORD of header.
>> > +##
>> > +{ 'struct': 'CXLUncorErrorRecord',
>> > + 'data': {
>> > + 'type': 'CxlUncorErrorType',
>> > + 'header': [ 'uint32' ]
>> > + }
>> > +}
>> > +
>> > +##
>> > +# @cxl-inject-uncorrectable-errors:
>> > +#
>> > +# Command to allow injection of multiple errors in one go. This allows testing
>> > +# of multiple header log handling in the OS.
>> > +#
>> > +# @path: CXL Type 3 device canonical QOM path
>> > +# @errors: Errors to inject
>> > +##
>> > +{ 'command': 'cxl-inject-uncorrectable-errors',
>> > + 'data': { 'path': 'str',
>> > + 'errors': [ 'CXLUncorErrorRecord' ] }}
>> > +
>> > +##
>> > +# @CxlCorErrorType:
>> > +#
>> > +# Type of CXL correctable error to inject
>> > +#
>> > +# @cache-data-ecc: Data ECC error on CXL.cache
>> > +# @mem-data-ecc: Data ECC error on CXL.mem
>>
>> Missing:
>>
>> # @retry-threshold: ...
>>
>> I need suitable description text. Can you help me?
>
> Spec says:
> "Retry Threshold Hit. (NUM_RETRY>=MAX_NUM_RETRY).
> See Section 4.2.8.5.1 for the definitions of NUM_RETRY and MAX_NUM_RETRY."
>
> Following the reference:
> "NUM_RETRY: This counter is used to count the number of RETRY.Req requests
> sent to retry the same flit. The counter remains enabled during the whole retry
> sequence (state is not RETRY_LOCAL_NORMAL). It is reset to 0 at initialization. It is
> also reset to 0 when a RETRY.Ack sequence is received with the Empty bit set or
> whenever the LRSM state is RETRY_LOCAL_NORMAL and an error-free retryable flit
> is received. The counter is incremented whenever the LRSM state changes from
> RETRY_LLRREQ to RETRY_LOCAL_IDLE. If the counter reaches a threshold (called
> MAX_NUM_RETRY), then the local retry state machine transitions to the
> RETRY_PHY_REINIT. The NUM_RETRY counter is also reset when the Physical layer
> exits from LTSSM recovery state (the LRSM transition through RETRY_PHY_REINIT
> to RETRY_LLRREQ)."
>
> So based on my failure to understand much of that beyond it has something
> to do with low level retries, maybe just
>
> "Number of times the retry threshold was hit."
Sold! Thanks for your help.
> Thanks for tidying this up!
You're welcome!
I intend post the patch as part of a series filling in documentation
holes all over the place. Will take some time, I'm afraid.
[...]
^ permalink raw reply [flat|nested] 27+ messages in thread
end of thread, other threads:[~2023-11-02 6:47 UTC | newest]
Thread overview: 27+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-02-21 15:21 [PATCH v5 0/8] hw/cxl: RAS error emulation and injection Jonathan Cameron
2023-02-21 15:21 ` [PATCH v5 1/8] hw/pci/aer: Implement PCI_ERR_UNCOR_MASK register Jonathan Cameron
2023-02-21 15:21 ` [PATCH v5 2/8] hw/pci/aer: Add missing routing for AER errors Jonathan Cameron
2023-02-21 15:21 ` [PATCH v5 3/8] hw/pci-bridge/cxl_root_port: Wire up AER Jonathan Cameron
2023-02-21 15:21 ` [PATCH v5 4/8] hw/pci-bridge/cxl_root_port: Wire up MSI Jonathan Cameron
2023-02-21 15:21 ` [PATCH v5 5/8] hw/mem/cxl-type3: Add AER extended capability Jonathan Cameron
2023-02-21 15:21 ` [PATCH v5 6/8] hw/cxl: Fix endian issues in CXL RAS capability defaults / masks Jonathan Cameron
2023-02-21 22:06 ` Philippe Mathieu-Daudé
2023-02-21 15:21 ` [PATCH v5 7/8] hw/pci/aer: Make PCIE AER error injection facility available for other emulation to use Jonathan Cameron
2023-02-21 22:08 ` Philippe Mathieu-Daudé
2023-02-21 15:21 ` [PATCH v5 8/8] hw/mem/cxl_type3: Add CXL RAS Error Injection Support Jonathan Cameron
2023-02-21 15:48 ` Dave Jiang
2023-02-21 22:15 ` Philippe Mathieu-Daudé
2023-02-22 14:53 ` Jonathan Cameron
2023-02-22 15:32 ` Philippe Mathieu-Daudé
2023-02-22 16:49 ` Jonathan Cameron
2023-02-22 18:16 ` Philippe Mathieu-Daudé
2023-02-23 6:58 ` Thomas Huth
2023-02-23 7:37 ` Markus Armbruster
2023-02-23 14:27 ` Jonathan Cameron
2023-02-24 17:37 ` Jonathan Cameron
2023-02-24 19:02 ` Philippe Mathieu-Daudé
2023-02-27 9:40 ` Markus Armbruster
2023-02-22 18:28 ` Markus Armbruster
2023-10-27 4:54 ` Markus Armbruster
2023-10-31 17:55 ` Jonathan Cameron
2023-11-02 6:47 ` Markus Armbruster
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