Re: [PATCH v2] cxl: Rename mem to pci

From: Dan Williams <dan.j.williams@intel.com>
To: Ben Widawsky <ben.widawsky@intel.com>
Cc: linux-cxl@vger.kernel.org,
	Jonathan Cameron <Jonathan.Cameron@huawei.com>,
	Alison Schofield <alison.schofield@intel.com>,
	Ira Weiny <ira.weiny@intel.com>,
	Vishal Verma <vishal.l.verma@intel.com>
Subject: Re: [PATCH v2] cxl: Rename mem to pci
Date: Thu, 20 May 2021 12:39:21 -0700	[thread overview]
Message-ID: <CAPcyv4iUE7OyGmWJUnO-ONdNHB+i36m4OnkL0KQCO_Q2Ssz29g@mail.gmail.com> (raw)
In-Reply-To: <20210520184138.996337-1-ben.widawsky@intel.com>

On Thu, May 20, 2021 at 11:41 AM Ben Widawsky <ben.widawsky@intel.com> wrote:
>
> As the driver has undergone development, it's become clear that the
> majority [entirety?] of the current functionality in mem.c is actually a
> layer encapsulating functionality exposed through PCI based
> interactions. This layer can be used either in isolation or to provide
> functionality for higher level functionality.
>
> CXL capabilities exist in a parallel domain to PCIe. CXL devices are
> enumerable and controllable via "legacy" PCIe mechanisms; however, their
> CXL capabilities are a superset of PCIe. For example, a CXL device may
> be connected to a non-CXL capable PCIe root port, and therefore will not
> be able to participate in CXL.mem or CXL.cache operations, but can still
> be accessed through PCIe mechanisms for CXL.io operations.
>
> To properly represent the PCI nature of this driver, and in preparation for
> introducing a new driver for the CXL.mem / HDM decoder (Host-managed Device
> Memory) capabilities of a CXL memory expander, rename mem.c to pci.c so that
> mem.c is available for this new driver.
>
> The result of the change is that there is a clear layering distinction
> in the driver, and a systems administrator may load only the cxl_pci
> module and gain access to such operations as, firmware update, offline
> provisioning of devices, and error collection. In addition to freeing up
> the file name for another purpose, there are two primary reasons this is
> useful,
>     1. Acting upon devices which don't have full CXL capabilities. This
>        may happen for instance if the CXL device is connected in a CXL
>        unaware part of the platform topology.
>     2. Userspace-first provisioning for devices without kernel driver
>        interference. This may be useful when provisioning a new device
>        in a specific manner that might otherwise be blocked or prevented
>        by the real CXL mem driver.
>
> Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
> ---
> v2: Makes it clear that the main motivation for this patch is for proper
> layering and that administrative PCI-only activities is a secondary benefit.
>
> I'm proposing we take the hit now and merge this as our next patch for cxl/next.

Looks good to me, and I think low risk to expedite into cxl/next to
remove the burden on git to cope with other development touching these
files.

Reviewed-by: Dan Williams <dan.j.williams@intel.com>