[RFC PATCH 0/9] soc: samsung: Add support of suspend-to-RAM on Exynos5433

[RFC PATCH 0/9] soc: samsung: Add support of suspend-to-RAM on Exynos5433

[Chanwoo Choi]

In the mainline, there is no case to support the suspend-to-RAM for Samsung
Exynos SoC. This patchset support the suspend-to-RAM for 64bit Exynos SoC.

For 32bit, arch/arm/mach-exynos/* directoy contains the suspend-related
codes such as suspend.c/exynos.c. But, 64bit Exynos should contain
the suspend-related codes in the drivers/soc/samsung/*. So, this patchset
develop the patch4/5 for drivers/soc/samsung/exynos-pm.c. to support suspend
64bit Exynos SoC.

But, I'm not sure what is proper approach for both 32/64bit Exynos.
- Approach1 : Split out the supend-related codes between 32/64bit.
  : arch/arm/mach-exynos/* contains the suspend-related codes for 32bit.
  : drivers/soc/samsung/* contains the suspend-related codes for 64bit.
- Approach2 : Consolidate the all suspend-related codes to drivers/soc/samsung/.

Please let us know your opinion.

The patch1/2/3 and 6/7/8/9 is just general patch. So, I add 'RFC' prefix to
only cover-letter, patch4/5. If you want to add the 'RFC' prefix to all
patches, I'll add 'RFC' prefix on v2.

Based on:
- git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git (branch: for-next)

Need to discuss patch4/5:
- patch4: soc: samsung: Add generic power-management driver for Exynos
- patch5: soc: samsung: pm: Add support for suspend-to-ram of Exynos5433

[Remaining Issues]
- The hang-out happen when disabling the MMC clocks on dw_mmc.c.
  I reported to Jaehoon Chung. He is checking this issue. To test the
  suspend-to-ram temporarily, you need to add CLK_IS_CRITICAL flag to
  'aclk_mmc2/aclk_mmc0/sclk_mmc2/sclk_mmc0'.
- I enabled the at least kernel configuration in order to test
  the suspend-to-RAM. So, I need to test it more time with DRM/Multimedia
  and other. But, the suspend-to-RAM of cpu is successful.
- Exynos5433 SoC has two EXYNOS5433_EINT_WAKEUP_MASKx registers. The
  pinctr-exynos.c need to handle the extra EINT_WAKEUP_MASKx for Exynos5433.
  The suspend-to-ram test is failed on first time and then next tryout is ok.
  I'm developing it.

Chanwoo Choi (9):
  clk: samsung: exynos5433: Add clock flag to support suspend-to-ram
  soc: samsung: pmu: Add powerup_conf callback
  soc: samsung: pmu: Add the PMU data of exynos5433 to support low-power state
  soc: samsung: Add generic power-management driver for Exynos
  soc: samsung: pm: Add support for suspend-to-ram of Exynos5433
  arm64: dts: exynos: Add iRAM device-tree node for Exynos5433
  arm64: dts: exynos: Use power key as a wakeup source on TM2/TM2E board
  arm64: dts: exynos: Add cpu_suspend property of PSCI for exynos5433
  arm64: dts: exynos: Add cpu topology information for Exynos5433 SoC

 arch/arm/mach-exynos/common.h                      |   3 -
 arch/arm/mach-exynos/exynos.c                      |  23 +-
 .../boot/dts/exynos/exynos5433-tm2-common.dtsi     |   1 +
 arch/arm64/boot/dts/exynos/exynos5433.dtsi         |  47 ++++
 drivers/clk/samsung/clk-exynos5433.c               |  22 +-
 drivers/soc/samsung/Makefile                       |   5 +-
 drivers/soc/samsung/exynos-pm.c                    | 214 +++++++++++++++
 drivers/soc/samsung/exynos-pmu.c                   |   9 +
 drivers/soc/samsung/exynos-pmu.h                   |   3 +
 drivers/soc/samsung/exynos5433-pmu.c               | 286 +++++++++++++++++++++
 include/linux/soc/samsung/exynos-pm.h              |  21 ++
 include/linux/soc/samsung/exynos-pmu.h             |   1 +
 include/linux/soc/samsung/exynos-regs-pmu.h        | 148 +++++++++++
 13 files changed, 745 insertions(+), 38 deletions(-)
 create mode 100644 drivers/soc/samsung/exynos-pm.c
 create mode 100644 drivers/soc/samsung/exynos5433-pmu.c
 create mode 100644 include/linux/soc/samsung/exynos-pm.h

--
1.9.1

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[PATCH 1/9] clk: samsung: exynos5433: Add clock flag to support suspend-to-ram

[Chanwoo Choi]

This patch adds the CLK_IS_CRITICAL and CLK_IGNORE_UNUSED flag
to some clocks in order to avoid the hang-out in the suspend mode.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-clk@vger.kernel.org
---
 drivers/clk/samsung/clk-exynos5433.c | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index db270908037a..3dc53cd0c730 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -583,25 +583,25 @@
 			CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 	GATE(CLK_ACLK_CAM1_333, "aclk_cam1_333", "div_aclk_cam1_333",
 			ENABLE_ACLK_TOP, 13,
-			CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+			CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
 	GATE(CLK_ACLK_CAM1_400, "aclk_cam1_400", "div_aclk_cam1_400",
 			ENABLE_ACLK_TOP, 12,
 			CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
 	GATE(CLK_ACLK_CAM1_552, "aclk_cam1_552", "div_aclk_cam1_552",
 			ENABLE_ACLK_TOP, 11,
-			CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+			CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
 	GATE(CLK_ACLK_CAM0_333, "aclk_cam0_333", "div_aclk_cam0_333",
 			ENABLE_ACLK_TOP, 10,
-			CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+			CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
 	GATE(CLK_ACLK_CAM0_400, "aclk_cam0_400", "div_aclk_cam0_400",
 			ENABLE_ACLK_TOP, 9,
 			CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
 	GATE(CLK_ACLK_CAM0_552, "aclk_cam0_552", "div_aclk_cam0_552",
 			ENABLE_ACLK_TOP, 8,
-			CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+			CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
 	GATE(CLK_ACLK_ISP_DIS_400, "aclk_isp_dis_400", "div_aclk_isp_dis_400",
 			ENABLE_ACLK_TOP, 7,
-			CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+			CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
 	GATE(CLK_ACLK_ISP_400, "aclk_isp_400", "div_aclk_isp_400",
 			ENABLE_ACLK_TOP, 6,
 			CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
@@ -624,11 +624,11 @@

 	/* ENABLE_SCLK_TOP_CAM1 */
 	GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "div_sclk_isp_sensor2_b",
-			ENABLE_SCLK_TOP_CAM1, 7, 0, 0),
+			ENABLE_SCLK_TOP_CAM1, 7, CLK_IGNORE_UNUSED, 0),
 	GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "div_sclk_isp_sensor1_b",
 			ENABLE_SCLK_TOP_CAM1, 6, 0, 0),
 	GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "div_sclk_isp_sensor0_b",
-			ENABLE_SCLK_TOP_CAM1, 5, 0, 0),
+			ENABLE_SCLK_TOP_CAM1, 5, CLK_IGNORE_UNUSED, 0),
 	GATE(CLK_SCLK_ISP_MCTADC_CAM1, "sclk_isp_mctadc_cam1", "oscclk",
 			ENABLE_SCLK_TOP_CAM1, 4, 0, 0),
 	GATE(CLK_SCLK_ISP_UART_CAM1, "sclk_isp_uart_cam1", "div_sclk_isp_uart",
@@ -636,7 +636,7 @@
 	GATE(CLK_SCLK_ISP_SPI1_CAM1, "sclk_isp_spi1_cam1", "div_sclk_isp_spi1_b",
 			ENABLE_SCLK_TOP_CAM1, 1, 0, 0),
 	GATE(CLK_SCLK_ISP_SPI0_CAM1, "sclk_isp_spi0_cam1", "div_sclk_isp_spi0_b",
-			ENABLE_SCLK_TOP_CAM1, 0, 0, 0),
+			ENABLE_SCLK_TOP_CAM1, 0, CLK_IGNORE_UNUSED, 0),

 	/* ENABLE_SCLK_TOP_DISP */
 	GATE(CLK_SCLK_HDMI_SPDIF_DISP, "sclk_hdmi_spdif_disp",
@@ -654,7 +654,7 @@
 			ENABLE_SCLK_TOP_FSYS, 4, CLK_SET_RATE_PARENT, 0),
 	GATE(CLK_SCLK_UFSUNIPRO_FSYS, "sclk_ufsunipro_fsys",
 			"div_sclk_ufsunipro", ENABLE_SCLK_TOP_FSYS,
-			3, CLK_SET_RATE_PARENT, 0),
+			3, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
 	GATE(CLK_SCLK_USBHOST30_FSYS, "sclk_usbhost30_fsys",
 			"div_sclk_usbhost30", ENABLE_SCLK_TOP_FSYS,
 			1, CLK_SET_RATE_PARENT, 0),
@@ -2982,7 +2982,7 @@ static void __init exynos5433_cmu_peris_init(struct device_node *np)
 	GATE(CLK_PCLK_AUD_SLIMBUS, "pclk_aud_slimbus", "div_aclk_aud",
 			ENABLE_PCLK_AUD, 6, 0, 0),
 	GATE(CLK_PCLK_AUD_UART, "pclk_aud_uart", "div_aclk_aud",
-			ENABLE_PCLK_AUD, 5, 0, 0),
+			ENABLE_PCLK_AUD, 5, CLK_IS_CRITICAL, 0),
 	GATE(CLK_PCLK_AUD_PCM, "pclk_aud_pcm", "div_aclk_aud",
 			ENABLE_PCLK_AUD, 4, 0, 0),
 	GATE(CLK_PCLK_AUD_I2S, "pclk_aud_i2s", "div_aclk_aud",
@@ -3008,7 +3008,7 @@ static void __init exynos5433_cmu_peris_init(struct device_node *np)
 	GATE(CLK_SCLK_AUD_SLIMBUS, "sclk_aud_slimbus", "div_sclk_aud_slimbus",
 			ENABLE_SCLK_AUD1, 4, 0, 0),
 	GATE(CLK_SCLK_AUD_UART, "sclk_aud_uart", "div_sclk_aud_uart",
-			ENABLE_SCLK_AUD1, 3, CLK_IGNORE_UNUSED, 0),
+			ENABLE_SCLK_AUD1, 3, CLK_IS_CRITICAL, 0),
 	GATE(CLK_SCLK_AUD_PCM, "sclk_aud_pcm", "div_sclk_aud_pcm",
 			ENABLE_SCLK_AUD1, 2, 0, 0),
 	GATE(CLK_SCLK_I2S_BCLK, "sclk_i2s_bclk", "ioclk_i2s_bclk",
--
1.9.1

Re: [PATCH 1/9] clk: samsung: exynos5433: Add clock flag to support suspend-to-ram

[Krzysztof Kozlowski]

On Tue, Jan 9, 2018 at 8:58 AM, Chanwoo Choi <cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> wrote:
> This patch adds the CLK_IS_CRITICAL and CLK_IGNORE_UNUSED flag
> to some clocks in order to avoid the hang-out in the suspend mode.
>
> Signed-off-by: Chanwoo Choi <cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> Cc: Tomasz Figa <tomasz.figa-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Cc: Michael Turquette <mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
> Cc: Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> Cc: linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> ---
>  drivers/clk/samsung/clk-exynos5433.c | 22 +++++++++++-----------
>  1 file changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
> index db270908037a..3dc53cd0c730 100644
> --- a/drivers/clk/samsung/clk-exynos5433.c
> +++ b/drivers/clk/samsung/clk-exynos5433.c
> @@ -583,25 +583,25 @@
>                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
>         GATE(CLK_ACLK_CAM1_333, "aclk_cam1_333", "div_aclk_cam1_333",
>                         ENABLE_ACLK_TOP, 13,
> -                       CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
> +                       CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
>         GATE(CLK_ACLK_CAM1_400, "aclk_cam1_400", "div_aclk_cam1_400",
>                         ENABLE_ACLK_TOP, 12,
>                         CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
>         GATE(CLK_ACLK_CAM1_552, "aclk_cam1_552", "div_aclk_cam1_552",
>                         ENABLE_ACLK_TOP, 11,
> -                       CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
> +                       CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
>         GATE(CLK_ACLK_CAM0_333, "aclk_cam0_333", "div_aclk_cam0_333",
>                         ENABLE_ACLK_TOP, 10,
> -                       CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
> +                       CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
>         GATE(CLK_ACLK_CAM0_400, "aclk_cam0_400", "div_aclk_cam0_400",
>                         ENABLE_ACLK_TOP, 9,
>                         CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
>         GATE(CLK_ACLK_CAM0_552, "aclk_cam0_552", "div_aclk_cam0_552",
>                         ENABLE_ACLK_TOP, 8,
> -                       CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
> +                       CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
>         GATE(CLK_ACLK_ISP_DIS_400, "aclk_isp_dis_400", "div_aclk_isp_dis_400",
>                         ENABLE_ACLK_TOP, 7,
> -                       CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
> +                       CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
>         GATE(CLK_ACLK_ISP_400, "aclk_isp_400", "div_aclk_isp_400",
>                         ENABLE_ACLK_TOP, 6,
>                         CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
> @@ -624,11 +624,11 @@
>
>         /* ENABLE_SCLK_TOP_CAM1 */
>         GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "div_sclk_isp_sensor2_b",
> -                       ENABLE_SCLK_TOP_CAM1, 7, 0, 0),
> +                       ENABLE_SCLK_TOP_CAM1, 7, CLK_IGNORE_UNUSED, 0),
>         GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "div_sclk_isp_sensor1_b",
>                         ENABLE_SCLK_TOP_CAM1, 6, 0, 0),
>         GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "div_sclk_isp_sensor0_b",
> -                       ENABLE_SCLK_TOP_CAM1, 5, 0, 0),
> +                       ENABLE_SCLK_TOP_CAM1, 5, CLK_IGNORE_UNUSED, 0),

Marking this and few others related to ISP as ignore_unused or
is_critical looks like a hacky workaround for wrong topology or
missing clock users. The real cause should be fixed instead marking
all the clocks as critical or ignore_unused.

Best regards,
Krzysztof

>         GATE(CLK_SCLK_ISP_MCTADC_CAM1, "sclk_isp_mctadc_cam1", "oscclk",
>                         ENABLE_SCLK_TOP_CAM1, 4, 0, 0),
>         GATE(CLK_SCLK_ISP_UART_CAM1, "sclk_isp_uart_cam1", "div_sclk_isp_uart",
> @@ -636,7 +636,7 @@
>         GATE(CLK_SCLK_ISP_SPI1_CAM1, "sclk_isp_spi1_cam1", "div_sclk_isp_spi1_b",
>                         ENABLE_SCLK_TOP_CAM1, 1, 0, 0),
>         GATE(CLK_SCLK_ISP_SPI0_CAM1, "sclk_isp_spi0_cam1", "div_sclk_isp_spi0_b",
> -                       ENABLE_SCLK_TOP_CAM1, 0, 0, 0),
> +                       ENABLE_SCLK_TOP_CAM1, 0, CLK_IGNORE_UNUSED, 0),
>
>         /* ENABLE_SCLK_TOP_DISP */
>         GATE(CLK_SCLK_HDMI_SPDIF_DISP, "sclk_hdmi_spdif_disp",
> @@ -654,7 +654,7 @@
>                         ENABLE_SCLK_TOP_FSYS, 4, CLK_SET_RATE_PARENT, 0),
>         GATE(CLK_SCLK_UFSUNIPRO_FSYS, "sclk_ufsunipro_fsys",
>                         "div_sclk_ufsunipro", ENABLE_SCLK_TOP_FSYS,
> -                       3, CLK_SET_RATE_PARENT, 0),
> +                       3, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
>         GATE(CLK_SCLK_USBHOST30_FSYS, "sclk_usbhost30_fsys",
>                         "div_sclk_usbhost30", ENABLE_SCLK_TOP_FSYS,
>                         1, CLK_SET_RATE_PARENT, 0),
> @@ -2982,7 +2982,7 @@ static void __init exynos5433_cmu_peris_init(struct device_node *np)
>         GATE(CLK_PCLK_AUD_SLIMBUS, "pclk_aud_slimbus", "div_aclk_aud",
>                         ENABLE_PCLK_AUD, 6, 0, 0),
>         GATE(CLK_PCLK_AUD_UART, "pclk_aud_uart", "div_aclk_aud",
> -                       ENABLE_PCLK_AUD, 5, 0, 0),
> +                       ENABLE_PCLK_AUD, 5, CLK_IS_CRITICAL, 0),
>         GATE(CLK_PCLK_AUD_PCM, "pclk_aud_pcm", "div_aclk_aud",
>                         ENABLE_PCLK_AUD, 4, 0, 0),
>         GATE(CLK_PCLK_AUD_I2S, "pclk_aud_i2s", "div_aclk_aud",
> @@ -3008,7 +3008,7 @@ static void __init exynos5433_cmu_peris_init(struct device_node *np)
>         GATE(CLK_SCLK_AUD_SLIMBUS, "sclk_aud_slimbus", "div_sclk_aud_slimbus",
>                         ENABLE_SCLK_AUD1, 4, 0, 0),
>         GATE(CLK_SCLK_AUD_UART, "sclk_aud_uart", "div_sclk_aud_uart",
> -                       ENABLE_SCLK_AUD1, 3, CLK_IGNORE_UNUSED, 0),
> +                       ENABLE_SCLK_AUD1, 3, CLK_IS_CRITICAL, 0),
>         GATE(CLK_SCLK_AUD_PCM, "sclk_aud_pcm", "div_sclk_aud_pcm",
>                         ENABLE_SCLK_AUD1, 2, 0, 0),
>         GATE(CLK_SCLK_I2S_BCLK, "sclk_i2s_bclk", "ioclk_i2s_bclk",
> --
> 1.9.1
>
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Re: [PATCH 1/9] clk: samsung: exynos5433: Add clock flag to support suspend-to-ram

[Chanwoo Choi]

On 2018년 01월 09일 20:44, Krzysztof Kozlowski wrote:
> On Tue, Jan 9, 2018 at 8:58 AM, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>> This patch adds the CLK_IS_CRITICAL and CLK_IGNORE_UNUSED flag
>> to some clocks in order to avoid the hang-out in the suspend mode.
>>
>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>> Cc: Tomasz Figa <tomasz.figa@gmail.com>
>> Cc: Michael Turquette <mturquette@baylibre.com>
>> Cc: Stephen Boyd <sboyd@codeaurora.org>
>> Cc: linux-clk@vger.kernel.org
>> ---
>>  drivers/clk/samsung/clk-exynos5433.c | 22 +++++++++++-----------
>>  1 file changed, 11 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
>> index db270908037a..3dc53cd0c730 100644
>> --- a/drivers/clk/samsung/clk-exynos5433.c
>> +++ b/drivers/clk/samsung/clk-exynos5433.c
>> @@ -583,25 +583,25 @@
>>                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
>>         GATE(CLK_ACLK_CAM1_333, "aclk_cam1_333", "div_aclk_cam1_333",
>>                         ENABLE_ACLK_TOP, 13,
>> -                       CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
>> +                       CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
>>         GATE(CLK_ACLK_CAM1_400, "aclk_cam1_400", "div_aclk_cam1_400",
>>                         ENABLE_ACLK_TOP, 12,
>>                         CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
>>         GATE(CLK_ACLK_CAM1_552, "aclk_cam1_552", "div_aclk_cam1_552",
>>                         ENABLE_ACLK_TOP, 11,
>> -                       CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
>> +                       CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
>>         GATE(CLK_ACLK_CAM0_333, "aclk_cam0_333", "div_aclk_cam0_333",
>>                         ENABLE_ACLK_TOP, 10,
>> -                       CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
>> +                       CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
>>         GATE(CLK_ACLK_CAM0_400, "aclk_cam0_400", "div_aclk_cam0_400",
>>                         ENABLE_ACLK_TOP, 9,
>>                         CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
>>         GATE(CLK_ACLK_CAM0_552, "aclk_cam0_552", "div_aclk_cam0_552",
>>                         ENABLE_ACLK_TOP, 8,
>> -                       CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
>> +                       CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
>>         GATE(CLK_ACLK_ISP_DIS_400, "aclk_isp_dis_400", "div_aclk_isp_dis_400",
>>                         ENABLE_ACLK_TOP, 7,
>> -                       CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
>> +                       CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
>>         GATE(CLK_ACLK_ISP_400, "aclk_isp_400", "div_aclk_isp_400",
>>                         ENABLE_ACLK_TOP, 6,
>>                         CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
>> @@ -624,11 +624,11 @@
>>
>>         /* ENABLE_SCLK_TOP_CAM1 */
>>         GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "div_sclk_isp_sensor2_b",
>> -                       ENABLE_SCLK_TOP_CAM1, 7, 0, 0),
>> +                       ENABLE_SCLK_TOP_CAM1, 7, CLK_IGNORE_UNUSED, 0),
>>         GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "div_sclk_isp_sensor1_b",
>>                         ENABLE_SCLK_TOP_CAM1, 6, 0, 0),
>>         GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "div_sclk_isp_sensor0_b",
>> -                       ENABLE_SCLK_TOP_CAM1, 5, 0, 0),
>> +                       ENABLE_SCLK_TOP_CAM1, 5, CLK_IGNORE_UNUSED, 0),
> 
> Marking this and few others related to ISP as ignore_unused or
> is_critical looks like a hacky workaround for wrong topology or
> missing clock users. The real cause should be fixed instead marking
> all the clocks as critical or ignore_unused.

I'm sorry. It is my mistake. When I tested the suspend again,
following three clocks need CLK_IS_CRITICAL flag.

- CLK_ACLK_CAM0_552 / CLK_SCLK_UFSUNIPRO_FSYS
  : there are not clk consumer until now.

- CLK_SCLK_AUD_UART is for serial_3.
  : There are no problem for the clocks of other serial port.
  Only this clock must need to enable it always on. If we have to
  handle CLK_SCLK_AUD_UART on drivers/tty/serial/samsung.c,
  we need to pass the 'serial port information and Exynos info'.
  So, If possible, adding the CLK_IS_CRITICAL flag to CLK_SCLK_AUD_UART
  is simple.

> 
> Best regards,
> Krzysztof
> 
>>         GATE(CLK_SCLK_ISP_MCTADC_CAM1, "sclk_isp_mctadc_cam1", "oscclk",
>>                         ENABLE_SCLK_TOP_CAM1, 4, 0, 0),
>>         GATE(CLK_SCLK_ISP_UART_CAM1, "sclk_isp_uart_cam1", "div_sclk_isp_uart",
>> @@ -636,7 +636,7 @@
>>         GATE(CLK_SCLK_ISP_SPI1_CAM1, "sclk_isp_spi1_cam1", "div_sclk_isp_spi1_b",
>>                         ENABLE_SCLK_TOP_CAM1, 1, 0, 0),
>>         GATE(CLK_SCLK_ISP_SPI0_CAM1, "sclk_isp_spi0_cam1", "div_sclk_isp_spi0_b",
>> -                       ENABLE_SCLK_TOP_CAM1, 0, 0, 0),
>> +                       ENABLE_SCLK_TOP_CAM1, 0, CLK_IGNORE_UNUSED, 0),
>>
>>         /* ENABLE_SCLK_TOP_DISP */
>>         GATE(CLK_SCLK_HDMI_SPDIF_DISP, "sclk_hdmi_spdif_disp",
>> @@ -654,7 +654,7 @@
>>                         ENABLE_SCLK_TOP_FSYS, 4, CLK_SET_RATE_PARENT, 0),
>>         GATE(CLK_SCLK_UFSUNIPRO_FSYS, "sclk_ufsunipro_fsys",
>>                         "div_sclk_ufsunipro", ENABLE_SCLK_TOP_FSYS,
>> -                       3, CLK_SET_RATE_PARENT, 0),
>> +                       3, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
>>         GATE(CLK_SCLK_USBHOST30_FSYS, "sclk_usbhost30_fsys",
>>                         "div_sclk_usbhost30", ENABLE_SCLK_TOP_FSYS,
>>                         1, CLK_SET_RATE_PARENT, 0),
>> @@ -2982,7 +2982,7 @@ static void __init exynos5433_cmu_peris_init(struct device_node *np)
>>         GATE(CLK_PCLK_AUD_SLIMBUS, "pclk_aud_slimbus", "div_aclk_aud",
>>                         ENABLE_PCLK_AUD, 6, 0, 0),
>>         GATE(CLK_PCLK_AUD_UART, "pclk_aud_uart", "div_aclk_aud",
>> -                       ENABLE_PCLK_AUD, 5, 0, 0),
>> +                       ENABLE_PCLK_AUD, 5, CLK_IS_CRITICAL, 0),
>>         GATE(CLK_PCLK_AUD_PCM, "pclk_aud_pcm", "div_aclk_aud",
>>                         ENABLE_PCLK_AUD, 4, 0, 0),
>>         GATE(CLK_PCLK_AUD_I2S, "pclk_aud_i2s", "div_aclk_aud",
>> @@ -3008,7 +3008,7 @@ static void __init exynos5433_cmu_peris_init(struct device_node *np)
>>         GATE(CLK_SCLK_AUD_SLIMBUS, "sclk_aud_slimbus", "div_sclk_aud_slimbus",
>>                         ENABLE_SCLK_AUD1, 4, 0, 0),
>>         GATE(CLK_SCLK_AUD_UART, "sclk_aud_uart", "div_sclk_aud_uart",
>> -                       ENABLE_SCLK_AUD1, 3, CLK_IGNORE_UNUSED, 0),
>> +                       ENABLE_SCLK_AUD1, 3, CLK_IS_CRITICAL, 0),
>>         GATE(CLK_SCLK_AUD_PCM, "sclk_aud_pcm", "div_sclk_aud_pcm",
>>                         ENABLE_SCLK_AUD1, 2, 0, 0),
>>         GATE(CLK_SCLK_I2S_BCLK, "sclk_i2s_bclk", "ioclk_i2s_bclk",
>> --
>> 1.9.1
>>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 
> 
> 


-- 
Best Regards,
Chanwoo Choi
Samsung Electronics

Re: [PATCH 1/9] clk: samsung: exynos5433: Add clock flag to support suspend-to-ram

[Marek Szyprowski]

Hi Krzysztof and Chanwoo,

On 2018-01-09 12:44, Krzysztof Kozlowski wrote:
> On Tue, Jan 9, 2018 at 8:58 AM, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>> This patch adds the CLK_IS_CRITICAL and CLK_IGNORE_UNUSED flag
>> to some clocks in order to avoid the hang-out in the suspend mode.
>>
>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>> Cc: Tomasz Figa <tomasz.figa@gmail.com>
>> Cc: Michael Turquette <mturquette@baylibre.com>
>> Cc: Stephen Boyd <sboyd@codeaurora.org>
>> Cc: linux-clk@vger.kernel.org
>> ---
>>   drivers/clk/samsung/clk-exynos5433.c | 22 +++++++++++-----------
>>   1 file changed, 11 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
>> index db270908037a..3dc53cd0c730 100644
>> --- a/drivers/clk/samsung/clk-exynos5433.c
>> +++ b/drivers/clk/samsung/clk-exynos5433.c
>> @@ -583,25 +583,25 @@
>>                          CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
>>          GATE(CLK_ACLK_CAM1_333, "aclk_cam1_333", "div_aclk_cam1_333",
>>                          ENABLE_ACLK_TOP, 13,
>> -                       CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
>> +                       CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
>>          GATE(CLK_ACLK_CAM1_400, "aclk_cam1_400", "div_aclk_cam1_400",
>>                          ENABLE_ACLK_TOP, 12,
>>                          CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
>>          GATE(CLK_ACLK_CAM1_552, "aclk_cam1_552", "div_aclk_cam1_552",
>>                          ENABLE_ACLK_TOP, 11,
>> -                       CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
>> +                       CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
>>          GATE(CLK_ACLK_CAM0_333, "aclk_cam0_333", "div_aclk_cam0_333",
>>                          ENABLE_ACLK_TOP, 10,
>> -                       CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
>> +                       CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
>>          GATE(CLK_ACLK_CAM0_400, "aclk_cam0_400", "div_aclk_cam0_400",
>>                          ENABLE_ACLK_TOP, 9,
>>                          CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
>>          GATE(CLK_ACLK_CAM0_552, "aclk_cam0_552", "div_aclk_cam0_552",
>>                          ENABLE_ACLK_TOP, 8,
>> -                       CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
>> +                       CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
>>          GATE(CLK_ACLK_ISP_DIS_400, "aclk_isp_dis_400", "div_aclk_isp_dis_400",
>>                          ENABLE_ACLK_TOP, 7,
>> -                       CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
>> +                       CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
>>          GATE(CLK_ACLK_ISP_400, "aclk_isp_400", "div_aclk_isp_400",
>>                          ENABLE_ACLK_TOP, 6,
>>                          CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
>> @@ -624,11 +624,11 @@
>>
>>          /* ENABLE_SCLK_TOP_CAM1 */
>>          GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "div_sclk_isp_sensor2_b",
>> -                       ENABLE_SCLK_TOP_CAM1, 7, 0, 0),
>> +                       ENABLE_SCLK_TOP_CAM1, 7, CLK_IGNORE_UNUSED, 0),
>>          GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "div_sclk_isp_sensor1_b",
>>                          ENABLE_SCLK_TOP_CAM1, 6, 0, 0),
>>          GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "div_sclk_isp_sensor0_b",
>> -                       ENABLE_SCLK_TOP_CAM1, 5, 0, 0),
>> +                       ENABLE_SCLK_TOP_CAM1, 5, CLK_IGNORE_UNUSED, 0),
> Marking this and few others related to ISP as ignore_unused or
> is_critical looks like a hacky workaround for wrong topology or
> missing clock users. The real cause should be fixed instead marking
> all the clocks as critical or ignore_unused.

I think that instead of using CLK_IGNORE_UNUSED / CLK_IS_CRITICAL 
workaround,
exynos5433 clk driver should simply use *_suspend_regs infrastructure.
See suspend_regs entry in samsung_cmu_info and similar solution in
exynos5420.c clk driver (see exynos5420_clk_suspend function).

There is no point guessing why those clocks have to be enabled for proper
suspend cycle and which client driver should handle it. The documentation
misses such information at all. Just handle it in clk driver internally
without exposing it to clock clients. We already do this in case of other
Exynos SoCs.

>
> Best regards,
> Krzysztof
>
>>          GATE(CLK_SCLK_ISP_MCTADC_CAM1, "sclk_isp_mctadc_cam1", "oscclk",
>>                          ENABLE_SCLK_TOP_CAM1, 4, 0, 0),
>>          GATE(CLK_SCLK_ISP_UART_CAM1, "sclk_isp_uart_cam1", "div_sclk_isp_uart",
>> @@ -636,7 +636,7 @@
>>          GATE(CLK_SCLK_ISP_SPI1_CAM1, "sclk_isp_spi1_cam1", "div_sclk_isp_spi1_b",
>>                          ENABLE_SCLK_TOP_CAM1, 1, 0, 0),
>>          GATE(CLK_SCLK_ISP_SPI0_CAM1, "sclk_isp_spi0_cam1", "div_sclk_isp_spi0_b",
>> -                       ENABLE_SCLK_TOP_CAM1, 0, 0, 0),
>> +                       ENABLE_SCLK_TOP_CAM1, 0, CLK_IGNORE_UNUSED, 0),
>>
>>          /* ENABLE_SCLK_TOP_DISP */
>>          GATE(CLK_SCLK_HDMI_SPDIF_DISP, "sclk_hdmi_spdif_disp",
>> @@ -654,7 +654,7 @@
>>                          ENABLE_SCLK_TOP_FSYS, 4, CLK_SET_RATE_PARENT, 0),
>>          GATE(CLK_SCLK_UFSUNIPRO_FSYS, "sclk_ufsunipro_fsys",
>>                          "div_sclk_ufsunipro", ENABLE_SCLK_TOP_FSYS,
>> -                       3, CLK_SET_RATE_PARENT, 0),
>> +                       3, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
>>          GATE(CLK_SCLK_USBHOST30_FSYS, "sclk_usbhost30_fsys",
>>                          "div_sclk_usbhost30", ENABLE_SCLK_TOP_FSYS,
>>                          1, CLK_SET_RATE_PARENT, 0),
>> @@ -2982,7 +2982,7 @@ static void __init exynos5433_cmu_peris_init(struct device_node *np)
>>          GATE(CLK_PCLK_AUD_SLIMBUS, "pclk_aud_slimbus", "div_aclk_aud",
>>                          ENABLE_PCLK_AUD, 6, 0, 0),
>>          GATE(CLK_PCLK_AUD_UART, "pclk_aud_uart", "div_aclk_aud",
>> -                       ENABLE_PCLK_AUD, 5, 0, 0),
>> +                       ENABLE_PCLK_AUD, 5, CLK_IS_CRITICAL, 0),
>>          GATE(CLK_PCLK_AUD_PCM, "pclk_aud_pcm", "div_aclk_aud",
>>                          ENABLE_PCLK_AUD, 4, 0, 0),
>>          GATE(CLK_PCLK_AUD_I2S, "pclk_aud_i2s", "div_aclk_aud",
>> @@ -3008,7 +3008,7 @@ static void __init exynos5433_cmu_peris_init(struct device_node *np)
>>          GATE(CLK_SCLK_AUD_SLIMBUS, "sclk_aud_slimbus", "div_sclk_aud_slimbus",
>>                          ENABLE_SCLK_AUD1, 4, 0, 0),
>>          GATE(CLK_SCLK_AUD_UART, "sclk_aud_uart", "div_sclk_aud_uart",
>> -                       ENABLE_SCLK_AUD1, 3, CLK_IGNORE_UNUSED, 0),
>> +                       ENABLE_SCLK_AUD1, 3, CLK_IS_CRITICAL, 0),
>>          GATE(CLK_SCLK_AUD_PCM, "sclk_aud_pcm", "div_sclk_aud_pcm",
>>                          ENABLE_SCLK_AUD1, 2, 0, 0),
>>          GATE(CLK_SCLK_I2S_BCLK, "sclk_i2s_bclk", "ioclk_i2s_bclk",
>> --
>> 1.9.1
>>
>
>

Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland

[PATCH 2/9] soc: samsung: pmu: Add powerup_conf callback

[Chanwoo Choi]

This patch adds the powerup_conf callback which is used to re-initialize
the PMU registers during the resume state.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
 drivers/soc/samsung/exynos-pmu.c       | 8 ++++++++
 drivers/soc/samsung/exynos-pmu.h       | 1 +
 include/linux/soc/samsung/exynos-pmu.h | 1 +
 3 files changed, 10 insertions(+)

diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsung/exynos-pmu.c
index f56adbd9fb8b..cfc9de518344 100644
--- a/drivers/soc/samsung/exynos-pmu.c
+++ b/drivers/soc/samsung/exynos-pmu.c
@@ -58,6 +58,14 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode)
 		pmu_data->powerdown_conf_extra(mode);
 }
 
+void exynos_sys_powerup_conf(enum sys_powerdown mode)
+{
+	const struct exynos_pmu_data *pmu_data = pmu_context->pmu_data;
+
+	if (pmu_data->powerup_conf)
+		pmu_data->powerup_conf(mode);
+}
+
 /*
  * Split the data between ARM architectures because it is relatively big
  * and useless on other arch.
diff --git a/drivers/soc/samsung/exynos-pmu.h b/drivers/soc/samsung/exynos-pmu.h
index 977e4daf5a0f..efbaf8929252 100644
--- a/drivers/soc/samsung/exynos-pmu.h
+++ b/drivers/soc/samsung/exynos-pmu.h
@@ -24,6 +24,7 @@ struct exynos_pmu_data {
 	void (*pmu_init)(void);
 	void (*powerdown_conf)(enum sys_powerdown);
 	void (*powerdown_conf_extra)(enum sys_powerdown);
+	void (*powerup_conf)(enum sys_powerdown);
 };
 
 extern void __iomem *pmu_base_addr;
diff --git a/include/linux/soc/samsung/exynos-pmu.h b/include/linux/soc/samsung/exynos-pmu.h
index e57eb4b6cc5a..3aacf7b18401 100644
--- a/include/linux/soc/samsung/exynos-pmu.h
+++ b/include/linux/soc/samsung/exynos-pmu.h
@@ -22,6 +22,7 @@ enum sys_powerdown {
 };
 
 extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);
+extern void exynos_sys_powerup_conf(enum sys_powerdown mode);
 #ifdef CONFIG_EXYNOS_PMU
 extern struct regmap *exynos_get_pmu_regmap(void);
 #else
-- 
1.9.1

Re: [PATCH 2/9] soc: samsung: pmu: Add powerup_conf callback

[Krzysztof Kozlowski]

On Tue, Jan 9, 2018 at 8:58 AM, Chanwoo Choi <cw00.choi@samsung.com> wrote:
> This patch adds the powerup_conf callback which is used to re-initialize

Do not describe every patch as this patch. It does not bring any
information because I am already looking at this patch.
http://elixir.free-electrons.com/linux/latest/source/Documentation/process/submitting-patches.rst#L151

> the PMU registers during the resume state.
>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> ---
>  drivers/soc/samsung/exynos-pmu.c       | 8 ++++++++
>  drivers/soc/samsung/exynos-pmu.h       | 1 +
>  include/linux/soc/samsung/exynos-pmu.h | 1 +
>  3 files changed, 10 insertions(+)
>
> diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsung/exynos-pmu.c
> index f56adbd9fb8b..cfc9de518344 100644
> --- a/drivers/soc/samsung/exynos-pmu.c
> +++ b/drivers/soc/samsung/exynos-pmu.c
> @@ -58,6 +58,14 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode)
>                 pmu_data->powerdown_conf_extra(mode);
>  }
>
> +void exynos_sys_powerup_conf(enum sys_powerdown mode)
> +{
> +       const struct exynos_pmu_data *pmu_data = pmu_context->pmu_data;
> +

Follow the existing pattern of exynos_sys_powerdown_conf() to check if
pmu_context was initialized. At this commit, for Exynos5433 it is not
being set.

Best regards,
Krzysztof

> +       if (pmu_data->powerup_conf)
> +               pmu_data->powerup_conf(mode);
> +}
> +
>  /*
>   * Split the data between ARM architectures because it is relatively big
>   * and useless on other arch.
> diff --git a/drivers/soc/samsung/exynos-pmu.h b/drivers/soc/samsung/exynos-pmu.h
> index 977e4daf5a0f..efbaf8929252 100644
> --- a/drivers/soc/samsung/exynos-pmu.h
> +++ b/drivers/soc/samsung/exynos-pmu.h
> @@ -24,6 +24,7 @@ struct exynos_pmu_data {
>         void (*pmu_init)(void);
>         void (*powerdown_conf)(enum sys_powerdown);
>         void (*powerdown_conf_extra)(enum sys_powerdown);
> +       void (*powerup_conf)(enum sys_powerdown);
>  };
>
>  extern void __iomem *pmu_base_addr;
> diff --git a/include/linux/soc/samsung/exynos-pmu.h b/include/linux/soc/samsung/exynos-pmu.h
> index e57eb4b6cc5a..3aacf7b18401 100644
> --- a/include/linux/soc/samsung/exynos-pmu.h
> +++ b/include/linux/soc/samsung/exynos-pmu.h
> @@ -22,6 +22,7 @@ enum sys_powerdown {
>  };
>
>  extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);
> +extern void exynos_sys_powerup_conf(enum sys_powerdown mode);
>  #ifdef CONFIG_EXYNOS_PMU
>  extern struct regmap *exynos_get_pmu_regmap(void);
>  #else
> --
> 1.9.1
>

[PATCH 3/9] soc: samsung: pmu: Add the PMU data of exynos5433 to support low-power state

[Chanwoo Choi]

This patch adds the PMU (Power Management Unit) data of exynos5433 SoC
in order to support the various power modes. Each power mode has
the different value for reducing the power-consumption.

Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
 arch/arm/mach-exynos/common.h               |   2 -
 drivers/soc/samsung/Makefile                |   3 +-
 drivers/soc/samsung/exynos-pmu.c            |   1 +
 drivers/soc/samsung/exynos-pmu.h            |   2 +
 drivers/soc/samsung/exynos5433-pmu.c        | 286 ++++++++++++++++++++++++++++
 include/linux/soc/samsung/exynos-regs-pmu.h | 148 ++++++++++++++
 6 files changed, 439 insertions(+), 3 deletions(-)
 create mode 100644 drivers/soc/samsung/exynos5433-pmu.c

diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 098f84a149a3..afbc143a3d5d 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -125,8 +125,6 @@ enum {
 void exynos_set_boot_flag(unsigned int cpu, unsigned int mode);
 void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode);
 
-extern u32 exynos_get_eint_wake_mask(void);
-
 #ifdef CONFIG_PM_SLEEP
 extern void __init exynos_pm_init(void);
 #else
diff --git a/drivers/soc/samsung/Makefile b/drivers/soc/samsung/Makefile
index 29f294baac6e..d2e637339a45 100644
--- a/drivers/soc/samsung/Makefile
+++ b/drivers/soc/samsung/Makefile
@@ -2,5 +2,6 @@
 obj-$(CONFIG_EXYNOS_PMU)	+= exynos-pmu.o
 
 obj-$(CONFIG_EXYNOS_PMU_ARM_DRIVERS)	+= exynos3250-pmu.o exynos4-pmu.o \
-					exynos5250-pmu.o exynos5420-pmu.o
+					exynos5250-pmu.o exynos5420-pmu.o \
+					exynos5433-pmu.o
 obj-$(CONFIG_EXYNOS_PM_DOMAINS) += pm_domains.o
diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsung/exynos-pmu.c
index cfc9de518344..7112d7b2749b 100644
--- a/drivers/soc/samsung/exynos-pmu.c
+++ b/drivers/soc/samsung/exynos-pmu.c
@@ -97,6 +97,7 @@ void exynos_sys_powerup_conf(enum sys_powerdown mode)
 		.data = exynos_pmu_data_arm_ptr(exynos5420_pmu_data),
 	}, {
 		.compatible = "samsung,exynos5433-pmu",
+		.data = exynos_pmu_data_arm_ptr(exynos5433_pmu_data),
 	},
 	{ /*sentinel*/ },
 };
diff --git a/drivers/soc/samsung/exynos-pmu.h b/drivers/soc/samsung/exynos-pmu.h
index efbaf8929252..895c786a2f4c 100644
--- a/drivers/soc/samsung/exynos-pmu.h
+++ b/drivers/soc/samsung/exynos-pmu.h
@@ -28,6 +28,7 @@ struct exynos_pmu_data {
 };
 
 extern void __iomem *pmu_base_addr;
+extern u32 exynos_get_eint_wake_mask(void);
 
 #ifdef CONFIG_EXYNOS_PMU_ARM_DRIVERS
 /* list of all exported SoC specific data */
@@ -36,6 +37,7 @@ struct exynos_pmu_data {
 extern const struct exynos_pmu_data exynos4412_pmu_data;
 extern const struct exynos_pmu_data exynos5250_pmu_data;
 extern const struct exynos_pmu_data exynos5420_pmu_data;
+extern const struct exynos_pmu_data exynos5433_pmu_data;
 #endif
 
 extern void pmu_raw_writel(u32 val, u32 offset);
diff --git a/drivers/soc/samsung/exynos5433-pmu.c b/drivers/soc/samsung/exynos5433-pmu.c
new file mode 100644
index 000000000000..2571e61522f0
--- /dev/null
+++ b/drivers/soc/samsung/exynos5433-pmu.c
@@ -0,0 +1,286 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2018 Samsung Electronics Co., Ltd.
+// Copyright (c) Jonghwa Lee <jonghwa3.lee@samsung.com>
+// Copyright (c) Chanwoo Choi <cw00.choi@samsung.com>
+//
+// EXYNOS5433 - CPU PMU (Power Management Unit) support
+
+#include <linux/soc/samsung/exynos-regs-pmu.h>
+#include <linux/soc/samsung/exynos-pmu.h>
+
+#include "exynos-pmu.h"
+
+static struct exynos_pmu_conf exynos5433_pmu_config[] = {
+	/* { .offset = address,	.val = { AFTR, LPA, SLEEP } } */
+	{ EXYNOS5433_ATLAS_CPU0_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
+	{ EXYNOS5433_DIS_IRQ_ATLAS_CPU0_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0 } },
+	{ EXYNOS5433_ATLAS_CPU1_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
+	{ EXYNOS5433_DIS_IRQ_ATLAS_CPU1_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0 } },
+	{ EXYNOS5433_ATLAS_CPU2_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
+	{ EXYNOS5433_DIS_IRQ_ATLAS_CPU2_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0 } },
+	{ EXYNOS5433_ATLAS_CPU3_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
+	{ EXYNOS5433_DIS_IRQ_ATLAS_CPU3_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0 } },
+	{ EXYNOS5433_APOLLO_CPU0_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
+	{ EXYNOS5433_DIS_IRQ_APOLLO_CPU0_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0 } },
+	{ EXYNOS5433_APOLLO_CPU1_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
+	{ EXYNOS5433_DIS_IRQ_APOLLO_CPU1_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0 } },
+	{ EXYNOS5433_APOLLO_CPU2_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
+	{ EXYNOS5433_DIS_IRQ_APOLLO_CPU2_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0 } },
+	{ EXYNOS5433_APOLLO_CPU3_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
+	{ EXYNOS5433_DIS_IRQ_APOLLO_CPU3_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0 } },
+	{ EXYNOS5433_ATLAS_NONCPU_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
+	{ EXYNOS5433_APOLLO_NONCPU_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
+	{ EXYNOS5433_A5IS_SYS_PWR_REG,				{ 0x0, 0x0, 0x0 } },
+	{ EXYNOS5433_DIS_IRQ_A5IS_LOCAL_SYS_PWR_REG,		{ 0x0, 0x0, 0x0 } },
+	{ EXYNOS5433_DIS_IRQ_A5IS_CENTRAL_SYS_PWR_REG,		{ 0x0, 0x0, 0x0 } },
+	{ EXYNOS5433_ATLAS_L2_SYS_PWR_REG,			{ 0x0, 0x0, 0x7 } },
+	{ EXYNOS5433_APOLLO_L2_SYS_PWR_REG,			{ 0x0, 0x0, 0x7 } },
+	{ EXYNOS5433_CLKSTOP_CMU_TOP_SYS_PWR_REG,		{ 0x1, 0x0, 0x0 } },
+	{ EXYNOS5433_CLKRUN_CMU_TOP_SYS_PWR_REG,		{ 0x1, 0x0, 0x0 } },
+	{ EXYNOS5433_RESET_CMU_TOP_SYS_PWR_REG,			{ 0x1, 0x0, 0x0 } },
+	{ EXYNOS5433_RESET_CPUCLKSTOP_SYS_PWR_REG,		{ 0x1, 0x1, 0x0 } },
+	{ EXYNOS5433_CLKSTOP_CMU_MIF_SYS_PWR_REG,		{ 0x1, 0x0, 0x0 } },
+	{ EXYNOS5433_CLKRUN_CMU_MIF_SYS_PWR_REG,		{ 0x1, 0x1, 0x0 } },
+	{ EXYNOS5433_RESET_CMU_MIF_SYS_PWR_REG,			{ 0x1, 0x0, 0x0 } },
+	{ EXYNOS5433_DDRPHY_DLLLOCK_SYS_PWR_REG,		{ 0x1, 0x1, 0x1 } },
+	{ EXYNOS5433_DISABLE_PLL_CMU_TOP_SYS_PWR_REG,		{ 0x1, 0x0, 0x0 } },
+	{ EXYNOS5433_DISABLE_PLL_AUD_PLL_SYS_PWR_REG,		{ 0x1, 0x1, 0x0 } },
+	{ EXYNOS5433_DISABLE_PLL_CMU_MIF_SYS_PWR_REG,		{ 0x1, 0x0, 0x0 } },
+	{ EXYNOS5433_TOP_BUS_SYS_PWR_REG,			{ 0x7, 0x0, 0x0 } },
+	{ EXYNOS5433_TOP_RETENTION_SYS_PWR_REG,			{ 0x1, 0x0, 0x1 } },
+	{ EXYNOS5433_TOP_PWR_SYS_PWR_REG,			{ 0x3, 0x0, 0x3 } },
+	{ EXYNOS5433_TOP_BUS_MIF_SYS_PWR_REG,			{ 0x7, 0x0, 0x0 } },
+	{ EXYNOS5433_TOP_RETENTION_MIF_SYS_PWR_REG,		{ 0x1, 0x0, 0x1 } },
+	{ EXYNOS5433_TOP_PWR_MIF_SYS_PWR_REG,			{ 0x3, 0x0, 0x3 } },
+	{ EXYNOS5433_LOGIC_RESET_SYS_PWR_REG,			{ 0x1, 0x0, 0x0 } },
+	{ EXYNOS5433_OSCCLK_GATE_SYS_PWR_REG,			{ 0x1, 0x0, 0x1 } },
+	{ EXYNOS5433_SLEEP_RESET_SYS_PWR_REG,			{ 0x1, 0x1, 0x0 } },
+	{ EXYNOS5433_LOGIC_RESET_MIF_SYS_PWR_REG,		{ 0x1, 0x0, 0x0 } },
+	{ EXYNOS5433_OSCCLK_GATE_MIF_SYS_PWR_REG,		{ 0x1, 0x0, 0x1 } },
+	{ EXYNOS5433_SLEEP_RESET_MIF_SYS_PWR_REG,		{ 0x1, 0x1, 0x0 } },
+	{ EXYNOS5433_MEMORY_TOP_SYS_PWR_REG,			{ 0x3, 0x0, 0x0 } },
+	{ EXYNOS5433_PAD_RETENTION_LPDDR3_SYS_PWR_REG,		{ 0x1, 0x0, 0x0 } },
+	{ EXYNOS5433_PAD_RETENTION_JTAG_SYS_PWR_REG,		{ 0x1, 0x0, 0x0 } },
+	{ EXYNOS5433_PAD_RETENTION_TOP_SYS_PWR_REG,		{ 0x1, 0x0, 0x0 } },
+	{ EXYNOS5433_PAD_RETENTION_UART_SYS_PWR_REG,		{ 0x1, 0x0, 0x0 } },
+	{ EXYNOS5433_PAD_RETENTION_EBIA_SYS_PWR_REG,		{ 0x1, 0x0, 0x0 } },
+	{ EXYNOS5433_PAD_RETENTION_EBIB_SYS_PWR_REG,		{ 0x1, 0x0, 0x0 } },
+	{ EXYNOS5433_PAD_RETENTION_SPI_SYS_PWR_REG,		{ 0x1, 0x0, 0x0 } },
+	{ EXYNOS5433_PAD_RETENTION_MIF_SYS_PWR_REG,		{ 0x1, 0x0, 0x0 } },
+	{ EXYNOS5433_PAD_ISOLATION_SYS_PWR_REG,			{ 0x1, 0x0, 0x1 } },
+	{ EXYNOS5433_PAD_RETENTION_USBXTI_SYS_PWR_REG,		{ 0x1, 0x0, 0x0 } },
+	{ EXYNOS5433_PAD_RETENTION_BOOTLDO_SYS_PWR_REG,		{ 0x1, 0x0, 0x0 } },
+	{ EXYNOS5433_PAD_ISOLATION_MIF_SYS_PWR_REG,		{ 0x1, 0x0, 0x1 } },
+	{ EXYNOS5433_PAD_RETENTION_FSYSGENIO_SYS_PWR_REG,	{ 0x1, 0x0, 0x0 } },
+	{ EXYNOS5433_PAD_ALV_SEL_SYS_PWR_REG,			{ 0x1, 0x0, 0x0 } },
+	{ EXYNOS5433_XXTI_SYS_PWR_REG,				{ 0x1, 0x1, 0x0 } },
+	{ EXYNOS5433_XXTI26_SYS_PWR_REG,			{ 0x1, 0x0, 0x0 } },
+	{ EXYNOS5433_EXT_REGULATOR_SYS_PWR_REG,			{ 0x1, 0x1, 0x0 } },
+	{ EXYNOS5433_GPIO_MODE_SYS_PWR_REG,			{ 0x1, 0x0, 0x0 } },
+	{ EXYNOS5433_GPIO_MODE_FSYS0_SYS_PWR_REG,		{ 0x1, 0x0, 0x0 } },
+	{ EXYNOS5433_GPIO_MODE_MIF_SYS_PWR_REG,			{ 0x1, 0x0, 0x0 } },
+	{ EXYNOS5433_GPIO_MODE_AUD_SYS_PWR_REG,			{ 0x1, 0x1, 0x0 } },
+	{ EXYNOS5433_GSCL_SYS_PWR_REG,				{ 0xF, 0x0, 0x0 } },
+	{ EXYNOS5433_CAM0_SYS_PWR_REG,				{ 0xF, 0x0, 0x0 } },
+	{ EXYNOS5433_MSCL_SYS_PWR_REG,				{ 0xF, 0x0, 0x0 } },
+	{ EXYNOS5433_G3D_SYS_PWR_REG,				{ 0xF, 0x0, 0x0 } },
+	{ EXYNOS5433_DISP_SYS_PWR_REG,				{ 0xF, 0x0, 0x0 } },
+	{ EXYNOS5433_CAM1_SYS_PWR_REG,				{ 0xF, 0x0, 0x0 } },
+	{ EXYNOS5433_AUD_SYS_PWR_REG,				{ 0xF, 0xF, 0x0 } },
+	{ EXYNOS5433_FSYS_SYS_PWR_REG,				{ 0xF, 0x0, 0x0 } },
+	{ EXYNOS5433_BUS2_SYS_PWR_REG,				{ 0xF, 0x0, 0x0 } },
+	{ EXYNOS5433_G2D_SYS_PWR_REG,				{ 0xF, 0x0, 0x0 } },
+	{ EXYNOS5433_ISP0_SYS_PWR_REG,				{ 0xF, 0x0, 0x0 } },
+	{ EXYNOS5433_MFC_SYS_PWR_REG,				{ 0xF, 0x0, 0x0 } },
+	{ EXYNOS5433_HEVC_SYS_PWR_REG,				{ 0xF, 0x0, 0x0 } },
+	{ EXYNOS5433_RESET_SLEEP_FSYS_SYS_PWR_REG,		{ 0x1, 0x1, 0x0 } },
+	{ EXYNOS5433_RESET_SLEEP_BUS2_SYS_PWR_REG,		{ 0x1, 0x1, 0x0 } },
+	{ PMU_TABLE_END, },
+};
+
+static unsigned int const exynos5433_list_feed[] = {
+	EXYNOS5433_ATLAS_NONCPU_OPTION,
+	EXYNOS5433_APOLLO_NONCPU_OPTION,
+	EXYNOS5433_TOP_PWR_OPTION,
+	EXYNOS5433_TOP_PWR_MIF_OPTION,
+	EXYNOS5433_AUD_OPTION,
+	EXYNOS5433_CAM0_OPTION,
+	EXYNOS5433_DISP_OPTION,
+	EXYNOS5433_G2D_OPTION,
+	EXYNOS5433_G3D_OPTION,
+	EXYNOS5433_HEVC_OPTION,
+	EXYNOS5433_MSCL_OPTION,
+	EXYNOS5433_MFC_OPTION,
+	EXYNOS5433_GSCL_OPTION,
+	EXYNOS5433_FSYS_OPTION,
+	EXYNOS5433_ISP_OPTION,
+	EXYNOS5433_BUS2_OPTION,
+};
+
+static unsigned int const exynos5433_list_pad_retention[] = {
+	EXYNOS5433_PAD_RETENTION_LPDDR3_OPTION,
+	EXYNOS5433_PAD_RETENTION_AUD_OPTION,
+	EXYNOS5433_PAD_RETENTION_MMC2_OPTION,
+	EXYNOS5433_PAD_RETENTION_TOP_OPTION,
+	EXYNOS5433_PAD_RETENTION_UART_OPTION,
+	EXYNOS5433_PAD_RETENTION_MMC0_OPTION,
+	EXYNOS5433_PAD_RETENTION_MMC1_OPTION,
+	EXYNOS5433_PAD_RETENTION_EBIA_OPTION,
+	EXYNOS5433_PAD_RETENTION_EBIB_OPTION,
+	EXYNOS5433_PAD_RETENTION_SPI_OPTION,
+	EXYNOS5433_PAD_RETENTION_MIF_OPTION,
+	EXYNOS5433_PAD_RETENTION_USBXTI_OPTION,
+	EXYNOS5433_PAD_RETENTION_BOOTLDO_OPTION,
+	EXYNOS5433_PAD_RETENTION_UFS_OPTION,
+	EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION,
+};
+
+static void exynos5433_set_wakeupmask(enum sys_powerdown mode)
+{
+	u32 intmask = 0;
+
+	pmu_raw_writel(exynos_get_eint_wake_mask(),
+					EXYNOS5433_EINT_WAKEUP_MASK);
+
+	/* Disable WAKEUP event monitor */
+	intmask = pmu_raw_readl(EXYNOS5433_WAKEUP_MASK);
+	intmask &= ~(1 << 31);
+	pmu_raw_writel(intmask, EXYNOS5433_WAKEUP_MASK);
+
+	pmu_raw_writel(0xFFFF0000, EXYNOS5433_WAKEUP_MASK2);
+	pmu_raw_writel(0xFFFF0000, EXYNOS5433_WAKEUP_MASK3);
+}
+
+static void exynos5433_pmu_central_seq(bool enable)
+{
+	unsigned int tmp;
+
+	tmp = pmu_raw_readl(EXYNOS5433_CENTRAL_SEQ_CONFIGURATION);
+	if (enable)
+		tmp &= ~EXYNOS5433_CENTRALSEQ_PWR_CFG;
+	else
+		tmp |= EXYNOS5433_CENTRALSEQ_PWR_CFG;
+	pmu_raw_writel(tmp, EXYNOS5433_CENTRAL_SEQ_CONFIGURATION);
+
+	tmp = pmu_raw_readl(EXYNOS5433_CENTRAL_SEQ_MIF_CONFIGURATION);
+	if (enable)
+		tmp &= ~EXYNOS5433_CENTRALSEQ_PWR_CFG;
+	else
+		tmp |= EXYNOS5433_CENTRALSEQ_PWR_CFG;
+	pmu_raw_writel(tmp, EXYNOS5433_CENTRAL_SEQ_MIF_CONFIGURATION);
+}
+
+static void exynos5433_pmu_pad_retention_release(void)
+{
+	unsigned int tmp;
+	int i;
+
+	for (i = 0 ; i < ARRAY_SIZE(exynos5433_list_pad_retention) ; i++) {
+		tmp = pmu_raw_readl(exynos5433_list_pad_retention[i]);
+		tmp |= EXYNOS5433_INITIATE_WAKEUP_FROM_LOWPOWER;
+		pmu_raw_writel(tmp, exynos5433_list_pad_retention[i]);
+	}
+}
+
+static void exynos5433_pmu_init(void)
+{
+	unsigned int tmp;
+	int i, cluster, cpu;
+
+	/* Enable non retention flip-flop reset for wakeup */
+	tmp = pmu_raw_readl(EXYNOS5433_PMU_SPARE0);
+	tmp |= EXYNOS5433_EN_NONRET_RESET;
+	pmu_raw_writel(tmp, EXYNOS5433_PMU_SPARE0);
+
+	 /* Enable only SC_FEEDBACK for the register list */
+	for (i = 0 ; i < ARRAY_SIZE(exynos5433_list_feed) ; i++) {
+		tmp = pmu_raw_readl(exynos5433_list_feed[i]);
+		tmp &= ~EXYNOS5_USE_SC_COUNTER;
+		tmp |= EXYNOS5_USE_SC_FEEDBACK;
+		pmu_raw_writel(tmp, exynos5433_list_feed[i]);
+	}
+
+	/*
+	 * Disable automatic L2 flush, Disable L2 retention and
+	 * Enable STANDBYWFIL2, ACE/ACP
+	 */
+	for (cluster = 0; cluster < 2; cluster++) {
+		tmp = pmu_raw_readl(EXYNOS5433_ATLAS_L2_OPTION + (cluster * 0x20));
+		tmp &= ~(EXYNOS5433_USE_AUTO_L2FLUSHREQ | EXYNOS5433_USE_RETENTION);
+
+		if (cluster == 0) {
+			tmp |= (EXYNOS5433_USE_STANDBYWFIL2 |
+				EXYNOS5433_USE_DEACTIVATE_ACE |
+				EXYNOS5433_USE_DEACTIVATE_ACP);
+		}
+		pmu_raw_writel(tmp, EXYNOS5433_ATLAS_L2_OPTION + (cluster * 0x20));
+	}
+
+	/*
+	 * Enable both SC_COUNTER and SC_FEEDBACK for the CPUs
+	 * Use STANDBYWFI and SMPEN to indicate that core is ready to enter
+	 * low power mode
+	 */
+	for (cpu = 0; cpu < 8; cpu++) {
+		tmp = pmu_raw_readl(EXYNOS5433_CPU_OPTION(cpu));
+		tmp |= (EXYNOS5_USE_SC_FEEDBACK | EXYNOS5_USE_SC_COUNTER);
+		tmp |= EXYNOS5433_USE_SMPEN;
+		tmp |= EXYNOS5433_USE_STANDBYWFI;
+		tmp &= ~EXYNOS5433_USE_STANDBYWFE;
+		pmu_raw_writel(tmp, EXYNOS5433_CPU_OPTION(cpu));
+
+		tmp = pmu_raw_readl(EXYNOS5433_CPU_DURATION(cpu));
+		tmp |= EXYNOS5433_DUR_WAIT_RESET;
+		tmp &= ~EXYNOS5433_DUR_SCALL;
+		tmp |= EXYNOS5433_DUR_SCALL_VALUE;
+		pmu_raw_writel(tmp, EXYNOS5433_CPU_DURATION(cpu));
+	}
+
+	/* Skip atlas block power-off during automatic power down sequence */
+	tmp = pmu_raw_readl(EXYNOS5433_ATLAS_CPUSEQUENCER_OPTION);
+	tmp |= EXYNOS5433_SKIP_BLK_PWR_DOWN;
+	pmu_raw_writel(tmp, EXYNOS5433_ATLAS_CPUSEQUENCER_OPTION);
+
+	/* Limit in-rush current during local power up of cores */
+	tmp = pmu_raw_readl(EXYNOS5433_UP_SCHEDULER);
+	tmp |= EXYNOS5433_ENABLE_ATLAS_CPU;
+	pmu_raw_writel(tmp, EXYNOS5433_UP_SCHEDULER);
+}
+
+static void exynos5433_powerdown_conf(enum sys_powerdown mode)
+{
+	switch (mode) {
+	case SYS_SLEEP:
+		exynos5433_set_wakeupmask(mode);
+		exynos5433_pmu_central_seq(true);
+		break;
+	default:
+		break;
+	};
+}
+
+static void exynos5433_powerup_conf(enum sys_powerdown mode)
+{
+	unsigned int wakeup;
+
+	switch (mode) {
+	case SYS_SLEEP:
+		wakeup = pmu_raw_readl(EXYNOS5433_CENTRAL_SEQ_CONFIGURATION);
+		wakeup &= EXYNOS5433_CENTRALSEQ_PWR_CFG;
+		if (wakeup)
+			exynos5433_pmu_pad_retention_release();
+		else
+			exynos5433_pmu_central_seq(false);
+		break;
+	default:
+		break;
+	};
+}
+
+const struct exynos_pmu_data exynos5433_pmu_data = {
+	.pmu_config		= exynos5433_pmu_config,
+	.pmu_init		= exynos5433_pmu_init,
+	.powerdown_conf		= exynos5433_powerdown_conf,
+	.powerup_conf		= exynos5433_powerup_conf,
+};
diff --git a/include/linux/soc/samsung/exynos-regs-pmu.h b/include/linux/soc/samsung/exynos-regs-pmu.h
index bebdde5dccd6..93a52d133ba1 100644
--- a/include/linux/soc/samsung/exynos-regs-pmu.h
+++ b/include/linux/soc/samsung/exynos-regs-pmu.h
@@ -645,7 +645,110 @@
 					 | EXYNOS5420_KFC_USE_STANDBY_WFI3)
 
 /* For EXYNOS5433 */
+#define EXYNOS5433_UP_SCHEDULER					(0x0120)
+#define EXYNOS5433_CENTRAL_SEQ_CONFIGURATION			(0x0200)
+#define EXYNOS5433_CENTRAL_SEQ_MIF_CONFIGURATION		(0x0240)
+#define EXYNOS5433_EINT_WAKEUP_MASK				(0x060C)
+#define EXYNOS5433_WAKEUP_MASK					(0x0610)
+#define EXYNOS5433_WAKEUP_MASK2					(0x0614)
+#define EXYNOS5433_WAKEUP_MASK3					(0x0618)
+#define EXYNOS5433_EINT_WAKEUP_MASK1				(0x062C)
 #define EXYNOS5433_USBHOST30_PHY_CONTROL			(0x0728)
+#define EXYNOS5433_PMU_SPARE0					(0x0900)
+#define EXYNOS5433_ATLAS_CPU0_SYS_PWR_REG			(0x1000)
+#define EXYNOS5433_DIS_IRQ_ATLAS_CPU0_CENTRAL_SYS_PWR_REG	(0x1008)
+#define EXYNOS5433_ATLAS_CPU1_SYS_PWR_REG			(0x1010)
+#define EXYNOS5433_DIS_IRQ_ATLAS_CPU1_CENTRAL_SYS_PWR_REG	(0x1018)
+#define EXYNOS5433_ATLAS_CPU2_SYS_PWR_REG			(0x1020)
+#define EXYNOS5433_DIS_IRQ_ATLAS_CPU2_CENTRAL_SYS_PWR_REG	(0x1028)
+#define EXYNOS5433_ATLAS_CPU3_SYS_PWR_REG			(0x1030)
+#define EXYNOS5433_DIS_IRQ_ATLAS_CPU3_CENTRAL_SYS_PWR_REG	(0x1038)
+#define EXYNOS5433_APOLLO_CPU0_SYS_PWR_REG			(0x1040)
+#define EXYNOS5433_DIS_IRQ_APOLLO_CPU0_CENTRAL_SYS_PWR_REG	(0x1048)
+#define EXYNOS5433_APOLLO_CPU1_SYS_PWR_REG			(0x1050)
+#define EXYNOS5433_DIS_IRQ_APOLLO_CPU1_CENTRAL_SYS_PWR_REG	(0x1058)
+#define EXYNOS5433_APOLLO_CPU2_SYS_PWR_REG			(0x1060)
+#define EXYNOS5433_DIS_IRQ_APOLLO_CPU2_CENTRAL_SYS_PWR_REG	(0x1068)
+#define EXYNOS5433_APOLLO_CPU3_SYS_PWR_REG			(0x1070)
+#define EXYNOS5433_DIS_IRQ_APOLLO_CPU3_CENTRAL_SYS_PWR_REG	(0x1078)
+#define EXYNOS5433_ATLAS_NONCPU_SYS_PWR_REG			(0x1080)
+#define EXYNOS5433_ATLAS_L2_SYS_PWR_REG				(0x10C0)
+#define EXYNOS5433_APOLLO_L2_SYS_PWR_REG			(0x10C4)
+#define EXYNOS5433_APOLLO_NONCPU_SYS_PWR_REG			(0x1084)
+#define EXYNOS5433_A5IS_SYS_PWR_REG				(0x10B0)
+#define EXYNOS5433_DIS_IRQ_A5IS_LOCAL_SYS_PWR_REG		(0x10B4)
+#define EXYNOS5433_DIS_IRQ_A5IS_CENTRAL_SYS_PWR_REG		(0x10B8)
+#define EXYNOS5433_CLKSTOP_CMU_TOP_SYS_PWR_REG			(0x1100)
+#define EXYNOS5433_CLKRUN_CMU_TOP_SYS_PWR_REG			(0x1104)
+#define EXYNOS5433_RESET_CMU_TOP_SYS_PWR_REG			(0x110C)
+#define EXYNOS5433_RESET_CPUCLKSTOP_SYS_PWR_REG			(0x111C)
+#define EXYNOS5433_CLKSTOP_CMU_MIF_SYS_PWR_REG			(0x1120)
+#define EXYNOS5433_CLKRUN_CMU_MIF_SYS_PWR_REG			(0x1124)
+#define EXYNOS5433_RESET_CMU_MIF_SYS_PWR_REG			(0x112C)
+#define EXYNOS5433_DDRPHY_DLLLOCK_SYS_PWR_REG			(0x1138)
+#define EXYNOS5433_DISABLE_PLL_CMU_TOP_SYS_PWR_REG		(0x1140)
+#define EXYNOS5433_DISABLE_PLL_AUD_PLL_SYS_PWR_REG		(0x1144)
+#define EXYNOS5433_DISABLE_PLL_CMU_MIF_SYS_PWR_REG		(0x1160)
+#define EXYNOS5433_TOP_BUS_SYS_PWR_REG				(0x1180)
+#define EXYNOS5433_TOP_RETENTION_SYS_PWR_REG			(0x1184)
+#define EXYNOS5433_TOP_PWR_SYS_PWR_REG				(0x1188)
+#define EXYNOS5433_TOP_BUS_MIF_SYS_PWR_REG			(0x1190)
+#define EXYNOS5433_TOP_RETENTION_MIF_SYS_PWR_REG		(0x1194)
+#define EXYNOS5433_TOP_PWR_MIF_SYS_PWR_REG			(0x1198)
+#define EXYNOS5433_LOGIC_RESET_SYS_PWR_REG			(0x11A0)
+#define EXYNOS5433_OSCCLK_GATE_SYS_PWR_REG			(0x11A4)
+#define EXYNOS5433_SLEEP_RESET_SYS_PWR_REG			(0x11A8)
+#define EXYNOS5433_LOGIC_RESET_MIF_SYS_PWR_REG			(0x11B0)
+#define EXYNOS5433_OSCCLK_GATE_MIF_SYS_PWR_REG			(0x11B4)
+#define EXYNOS5433_SLEEP_RESET_MIF_SYS_PWR_REG			(0x11B8)
+#define EXYNOS5433_MEMORY_TOP_SYS_PWR_REG			(0x11C0)
+#define EXYNOS5433_PAD_RETENTION_LPDDR3_SYS_PWR_REG		(0x1200)
+#define EXYNOS5433_PAD_RETENTION_JTAG_SYS_PWR_REG		(0x1208)
+#define EXYNOS5433_PAD_RETENTION_TOP_SYS_PWR_REG		(0x1220)
+#define EXYNOS5433_PAD_RETENTION_UART_SYS_PWR_REG		(0x1224)
+#define EXYNOS5433_PAD_RETENTION_EBIA_SYS_PWR_REG		(0x1230)
+#define EXYNOS5433_PAD_RETENTION_EBIB_SYS_PWR_REG		(0x1234)
+#define EXYNOS5433_PAD_RETENTION_SPI_SYS_PWR_REG		(0x1238)
+#define EXYNOS5433_PAD_RETENTION_MIF_SYS_PWR_REG		(0x123C)
+#define EXYNOS5433_PAD_ISOLATION_SYS_PWR_REG			(0x1240)
+#define EXYNOS5433_PAD_RETENTION_USBXTI_SYS_PWR_REG		(0x1244)
+#define EXYNOS5433_PAD_RETENTION_BOOTLDO_SYS_PWR_REG		(0x1248)
+#define EXYNOS5433_PAD_ISOLATION_MIF_SYS_PWR_REG		(0x1250)
+#define EXYNOS5433_PAD_RETENTION_FSYSGENIO_SYS_PWR_REG		(0x1254)
+#define EXYNOS5433_PAD_ALV_SEL_SYS_PWR_REG			(0x1260)
+#define EXYNOS5433_XXTI_SYS_PWR_REG				(0x1284)
+#define EXYNOS5433_XXTI26_SYS_PWR_REG				(0x1288)
+#define EXYNOS5433_EXT_REGULATOR_SYS_PWR_REG			(0x12C0)
+#define EXYNOS5433_GPIO_MODE_SYS_PWR_REG			(0x1300)
+#define EXYNOS5433_GPIO_MODE_FSYS0_SYS_PWR_REG			(0x1304)
+#define EXYNOS5433_GPIO_MODE_MIF_SYS_PWR_REG			(0x1320)
+#define EXYNOS5433_GPIO_MODE_AUD_SYS_PWR_REG			(0x1340)
+#define EXYNOS5433_GSCL_SYS_PWR_REG				(0x1400)
+#define EXYNOS5433_CAM0_SYS_PWR_REG				(0x1404)
+#define EXYNOS5433_MSCL_SYS_PWR_REG				(0x1408)
+#define EXYNOS5433_G3D_SYS_PWR_REG				(0x140C)
+#define EXYNOS5433_DISP_SYS_PWR_REG				(0x1410)
+#define EXYNOS5433_CAM1_SYS_PWR_REG				(0x1414)
+#define EXYNOS5433_AUD_SYS_PWR_REG				(0x1418)
+#define EXYNOS5433_FSYS_SYS_PWR_REG				(0x141C)
+#define EXYNOS5433_BUS2_SYS_PWR_REG				(0x1420)
+#define EXYNOS5433_G2D_SYS_PWR_REG				(0x1424)
+#define EXYNOS5433_ISP0_SYS_PWR_REG				(0x1428)
+#define EXYNOS5433_MFC_SYS_PWR_REG				(0x1430)
+#define EXYNOS5433_HEVC_SYS_PWR_REG				(0x1438)
+#define EXYNOS5433_RESET_SLEEP_FSYS_SYS_PWR_REG			(0x15DC)
+#define EXYNOS5433_RESET_SLEEP_BUS2_SYS_PWR_REG			(0x15E0)
+#define EXYNOS5433_ATLAS_CPU0_OPTION				(0x2008)
+#define EXYNOS5433_CPU_OPTION(_nr)				(EXYNOS5433_ATLAS_CPU0_OPTION + (_nr) * 0x80)
+#define EXYNOS5433_ATLAS_CPU0_DURATION0				(0x2010)
+#define EXYNOS5433_CPU_DURATION(_nr)				(EXYNOS5433_ATLAS_CPU0_DURATION0 + (_nr) * 0x80)
+#define EXYNOS5433_ATLAS_NONCPU_OPTION				(0x2408)
+#define EXYNOS5433_APOLLO_NONCPU_OPTION				(0x2428)
+#define EXYNOS5433_ATLAS_CPUSEQUENCER_OPTION			(0x2488)
+#define EXYNOS5433_ATLAS_L2_OPTION				(0x2608)
+#define EXYNOS5433_TOP_PWR_MIF_OPTION				(0x2CC8)
+#define EXYNOS5433_TOP_PWR_OPTION				(0x2C48)
+#define EXYNOS5433_PAD_RETENTION_LPDDR3_OPTION			(0x3008)
 #define EXYNOS5433_PAD_RETENTION_AUD_OPTION			(0x3028)
 #define EXYNOS5433_PAD_RETENTION_MMC2_OPTION			(0x30C8)
 #define EXYNOS5433_PAD_RETENTION_TOP_OPTION			(0x3108)
@@ -660,5 +763,50 @@
 #define EXYNOS5433_PAD_RETENTION_BOOTLDO_OPTION			(0x3248)
 #define EXYNOS5433_PAD_RETENTION_UFS_OPTION			(0x3268)
 #define EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION		(0x32A8)
+#define EXYNOS5433_PS_HOLD_CONTROL				(0x330C)
+#define EXYNOS5433_GSCL_OPTION					(0x4008)
+#define EXYNOS5433_CAM0_OPTION					(0x4028)
+#define EXYNOS5433_MSCL_OPTION					(0x4048)
+#define EXYNOS5433_G3D_OPTION					(0x4068)
+#define EXYNOS5433_DISP_OPTION					(0x4088)
+#define EXYNOS5433_AUD_OPTION					(0x40C8)
+#define EXYNOS5433_FSYS_OPTION					(0x40E8)
+#define EXYNOS5433_BUS2_OPTION					(0x4108)
+#define EXYNOS5433_G2D_OPTION					(0x4128)
+#define EXYNOS5433_ISP_OPTION					(0x4148)
+#define EXYNOS5433_MFC_OPTION					(0x4188)
+#define EXYNOS5433_HEVC_OPTION					(0x41C8)
+
+/* EXYNOS5433_PMU_SPARE0 */
+#define EXYNOS5433_EN_NONRET_RESET				(1 << 0)
+
+/* EXYNOS5433_CENTRAL_SEQ_CONFIGURATION */
+#define EXYNOS5433_CENTRALSEQ_PWR_CFG				(0x1 << 16)
+
+/* EXYNOS5433_ATLAS_L2_OPTION */
+#define EXYNOS5433_USE_DEACTIVATE_ACE				(0x1 << 19)
+#define EXYNOS5433_USE_DEACTIVATE_ACP				(0x1 << 18)
+#define EXYNOS5433_USE_AUTO_L2FLUSHREQ				(0x1 << 17)
+#define EXYNOS5433_USE_STANDBYWFIL2				(0x1 << 16)
+#define EXYNOS5433_USE_RETENTION				(0x1 << 4)
+
+/* EXYNOS5433_CPU_OPTION */
+#define EXYNOS5433_USE_SMPEN					(0x1 << 28)
+#define EXYNOS5433_USE_STANDBYWFE				(0x1 << 24)
+#define EXYNOS5433_USE_STANDBYWFI				(0x1 << 16)
+
+/* EXYNOS5433_PAD_RETENTION_*_OPTION */
+#define EXYNOS5433_INITIATE_WAKEUP_FROM_LOWPOWER		(0x1 << 28)
+
+/* EXYNOS5433_CPU_DURATION */
+#define EXYNOS5433_DUR_WAIT_RESET				(0xF << 20)
+#define EXYNOS5433_DUR_SCALL					(0xF << 4)
+#define EXYNOS5433_DUR_SCALL_VALUE				(0x1 << 4)
+
+/* EXYNOS5433_ATLAS_CPUSEQUENCER_OPTION */
+#define EXYNOS5433_SKIP_BLK_PWR_DOWN				(0x1 << 8)
+
+/* EXYNOS5433_UP_SCHEDULER */
+#define EXYNOS5433_ENABLE_ATLAS_CPU				(0x1 << 0)
 
 #endif /* __LINUX_SOC_EXYNOS_REGS_PMU_H */
-- 
1.9.1

Re: [PATCH 3/9] soc: samsung: pmu: Add the PMU data of exynos5433 to support low-power state

[Krzysztof Kozlowski]

On Tue, Jan 9, 2018 at 8:59 AM, Chanwoo Choi <cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> wrote:
> This patch adds the PMU (Power Management Unit) data of exynos5433 SoC
> in order to support the various power modes. Each power mode has
> the different value for reducing the power-consumption.
>
> Signed-off-by: Jonghwa Lee <jonghwa3.lee-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> Signed-off-by: Chanwoo Choi <cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> ---
>  arch/arm/mach-exynos/common.h               |   2 -
>  drivers/soc/samsung/Makefile                |   3 +-
>  drivers/soc/samsung/exynos-pmu.c            |   1 +
>  drivers/soc/samsung/exynos-pmu.h            |   2 +
>  drivers/soc/samsung/exynos5433-pmu.c        | 286 ++++++++++++++++++++++++++++
>  include/linux/soc/samsung/exynos-regs-pmu.h | 148 ++++++++++++++
>  6 files changed, 439 insertions(+), 3 deletions(-)
>  create mode 100644 drivers/soc/samsung/exynos5433-pmu.c
>
> diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
> index 098f84a149a3..afbc143a3d5d 100644
> --- a/arch/arm/mach-exynos/common.h
> +++ b/arch/arm/mach-exynos/common.h
> @@ -125,8 +125,6 @@ enum {
>  void exynos_set_boot_flag(unsigned int cpu, unsigned int mode);
>  void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode);
>
> -extern u32 exynos_get_eint_wake_mask(void);
> -

This does not look good. Does it compile without warnings on ARMv7 platforms?

>  #ifdef CONFIG_PM_SLEEP
>  extern void __init exynos_pm_init(void);
>  #else
> diff --git a/drivers/soc/samsung/Makefile b/drivers/soc/samsung/Makefile
> index 29f294baac6e..d2e637339a45 100644
> --- a/drivers/soc/samsung/Makefile
> +++ b/drivers/soc/samsung/Makefile
> @@ -2,5 +2,6 @@
>  obj-$(CONFIG_EXYNOS_PMU)       += exynos-pmu.o
>
>  obj-$(CONFIG_EXYNOS_PMU_ARM_DRIVERS)   += exynos3250-pmu.o exynos4-pmu.o \
> -                                       exynos5250-pmu.o exynos5420-pmu.o
> +                                       exynos5250-pmu.o exynos5420-pmu.o \
> +                                       exynos5433-pmu.o
>  obj-$(CONFIG_EXYNOS_PM_DOMAINS) += pm_domains.o
> diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsung/exynos-pmu.c
> index cfc9de518344..7112d7b2749b 100644
> --- a/drivers/soc/samsung/exynos-pmu.c
> +++ b/drivers/soc/samsung/exynos-pmu.c
> @@ -97,6 +97,7 @@ void exynos_sys_powerup_conf(enum sys_powerdown mode)
>                 .data = exynos_pmu_data_arm_ptr(exynos5420_pmu_data),
>         }, {
>                 .compatible = "samsung,exynos5433-pmu",
> +               .data = exynos_pmu_data_arm_ptr(exynos5433_pmu_data),
>         },
>         { /*sentinel*/ },
>  };
> diff --git a/drivers/soc/samsung/exynos-pmu.h b/drivers/soc/samsung/exynos-pmu.h
> index efbaf8929252..895c786a2f4c 100644
> --- a/drivers/soc/samsung/exynos-pmu.h
> +++ b/drivers/soc/samsung/exynos-pmu.h
> @@ -28,6 +28,7 @@ struct exynos_pmu_data {
>  };
>
>  extern void __iomem *pmu_base_addr;
> +extern u32 exynos_get_eint_wake_mask(void);
>
>  #ifdef CONFIG_EXYNOS_PMU_ARM_DRIVERS
>  /* list of all exported SoC specific data */
> @@ -36,6 +37,7 @@ struct exynos_pmu_data {
>  extern const struct exynos_pmu_data exynos4412_pmu_data;
>  extern const struct exynos_pmu_data exynos5250_pmu_data;
>  extern const struct exynos_pmu_data exynos5420_pmu_data;
> +extern const struct exynos_pmu_data exynos5433_pmu_data;
>  #endif
>
>  extern void pmu_raw_writel(u32 val, u32 offset);
> diff --git a/drivers/soc/samsung/exynos5433-pmu.c b/drivers/soc/samsung/exynos5433-pmu.c
> new file mode 100644
> index 000000000000..2571e61522f0
> --- /dev/null
> +++ b/drivers/soc/samsung/exynos5433-pmu.c
> @@ -0,0 +1,286 @@
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright (c) 2018 Samsung Electronics Co., Ltd.
> +// Copyright (c) Jonghwa Lee <jonghwa3.lee-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> +// Copyright (c) Chanwoo Choi <cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>

Did you want to add here authorship notice or personal copyrights?

> +//
> +// EXYNOS5433 - CPU PMU (Power Management Unit) support
> +
> +#include <linux/soc/samsung/exynos-regs-pmu.h>
> +#include <linux/soc/samsung/exynos-pmu.h>
> +
> +#include "exynos-pmu.h"
> +
> +static struct exynos_pmu_conf exynos5433_pmu_config[] = {

This should be also const.

> +       /* { .offset = address, .val = { AFTR, LPA, SLEEP } } */
> +       { EXYNOS5433_ATLAS_CPU0_SYS_PWR_REG,                    { 0x0, 0x0, 0x8 } },
> +       { EXYNOS5433_DIS_IRQ_ATLAS_CPU0_CENTRAL_SYS_PWR_REG,    { 0x0, 0x0, 0x0 } },
> +       { EXYNOS5433_ATLAS_CPU1_SYS_PWR_REG,                    { 0x0, 0x0, 0x8 } },
> +       { EXYNOS5433_DIS_IRQ_ATLAS_CPU1_CENTRAL_SYS_PWR_REG,    { 0x0, 0x0, 0x0 } },
> +       { EXYNOS5433_ATLAS_CPU2_SYS_PWR_REG,                    { 0x0, 0x0, 0x8 } },
> +       { EXYNOS5433_DIS_IRQ_ATLAS_CPU2_CENTRAL_SYS_PWR_REG,    { 0x0, 0x0, 0x0 } },
> +       { EXYNOS5433_ATLAS_CPU3_SYS_PWR_REG,                    { 0x0, 0x0, 0x8 } },
> +       { EXYNOS5433_DIS_IRQ_ATLAS_CPU3_CENTRAL_SYS_PWR_REG,    { 0x0, 0x0, 0x0 } },
> +       { EXYNOS5433_APOLLO_CPU0_SYS_PWR_REG,                   { 0x0, 0x0, 0x8 } },
> +       { EXYNOS5433_DIS_IRQ_APOLLO_CPU0_CENTRAL_SYS_PWR_REG,   { 0x0, 0x0, 0x0 } },
> +       { EXYNOS5433_APOLLO_CPU1_SYS_PWR_REG,                   { 0x0, 0x0, 0x8 } },
> +       { EXYNOS5433_DIS_IRQ_APOLLO_CPU1_CENTRAL_SYS_PWR_REG,   { 0x0, 0x0, 0x0 } },
> +       { EXYNOS5433_APOLLO_CPU2_SYS_PWR_REG,                   { 0x0, 0x0, 0x8 } },
> +       { EXYNOS5433_DIS_IRQ_APOLLO_CPU2_CENTRAL_SYS_PWR_REG,   { 0x0, 0x0, 0x0 } },
> +       { EXYNOS5433_APOLLO_CPU3_SYS_PWR_REG,                   { 0x0, 0x0, 0x8 } },
> +       { EXYNOS5433_DIS_IRQ_APOLLO_CPU3_CENTRAL_SYS_PWR_REG,   { 0x0, 0x0, 0x0 } },
> +       { EXYNOS5433_ATLAS_NONCPU_SYS_PWR_REG,                  { 0x0, 0x0, 0x8 } },
> +       { EXYNOS5433_APOLLO_NONCPU_SYS_PWR_REG,                 { 0x0, 0x0, 0x8 } },
> +       { EXYNOS5433_A5IS_SYS_PWR_REG,                          { 0x0, 0x0, 0x0 } },
> +       { EXYNOS5433_DIS_IRQ_A5IS_LOCAL_SYS_PWR_REG,            { 0x0, 0x0, 0x0 } },
> +       { EXYNOS5433_DIS_IRQ_A5IS_CENTRAL_SYS_PWR_REG,          { 0x0, 0x0, 0x0 } },
> +       { EXYNOS5433_ATLAS_L2_SYS_PWR_REG,                      { 0x0, 0x0, 0x7 } },
> +       { EXYNOS5433_APOLLO_L2_SYS_PWR_REG,                     { 0x0, 0x0, 0x7 } },
> +       { EXYNOS5433_CLKSTOP_CMU_TOP_SYS_PWR_REG,               { 0x1, 0x0, 0x0 } },
> +       { EXYNOS5433_CLKRUN_CMU_TOP_SYS_PWR_REG,                { 0x1, 0x0, 0x0 } },
> +       { EXYNOS5433_RESET_CMU_TOP_SYS_PWR_REG,                 { 0x1, 0x0, 0x0 } },
> +       { EXYNOS5433_RESET_CPUCLKSTOP_SYS_PWR_REG,              { 0x1, 0x1, 0x0 } },
> +       { EXYNOS5433_CLKSTOP_CMU_MIF_SYS_PWR_REG,               { 0x1, 0x0, 0x0 } },
> +       { EXYNOS5433_CLKRUN_CMU_MIF_SYS_PWR_REG,                { 0x1, 0x1, 0x0 } },
> +       { EXYNOS5433_RESET_CMU_MIF_SYS_PWR_REG,                 { 0x1, 0x0, 0x0 } },
> +       { EXYNOS5433_DDRPHY_DLLLOCK_SYS_PWR_REG,                { 0x1, 0x1, 0x1 } },
> +       { EXYNOS5433_DISABLE_PLL_CMU_TOP_SYS_PWR_REG,           { 0x1, 0x0, 0x0 } },
> +       { EXYNOS5433_DISABLE_PLL_AUD_PLL_SYS_PWR_REG,           { 0x1, 0x1, 0x0 } },
> +       { EXYNOS5433_DISABLE_PLL_CMU_MIF_SYS_PWR_REG,           { 0x1, 0x0, 0x0 } },
> +       { EXYNOS5433_TOP_BUS_SYS_PWR_REG,                       { 0x7, 0x0, 0x0 } },
> +       { EXYNOS5433_TOP_RETENTION_SYS_PWR_REG,                 { 0x1, 0x0, 0x1 } },
> +       { EXYNOS5433_TOP_PWR_SYS_PWR_REG,                       { 0x3, 0x0, 0x3 } },
> +       { EXYNOS5433_TOP_BUS_MIF_SYS_PWR_REG,                   { 0x7, 0x0, 0x0 } },
> +       { EXYNOS5433_TOP_RETENTION_MIF_SYS_PWR_REG,             { 0x1, 0x0, 0x1 } },
> +       { EXYNOS5433_TOP_PWR_MIF_SYS_PWR_REG,                   { 0x3, 0x0, 0x3 } },
> +       { EXYNOS5433_LOGIC_RESET_SYS_PWR_REG,                   { 0x1, 0x0, 0x0 } },
> +       { EXYNOS5433_OSCCLK_GATE_SYS_PWR_REG,                   { 0x1, 0x0, 0x1 } },
> +       { EXYNOS5433_SLEEP_RESET_SYS_PWR_REG,                   { 0x1, 0x1, 0x0 } },
> +       { EXYNOS5433_LOGIC_RESET_MIF_SYS_PWR_REG,               { 0x1, 0x0, 0x0 } },
> +       { EXYNOS5433_OSCCLK_GATE_MIF_SYS_PWR_REG,               { 0x1, 0x0, 0x1 } },
> +       { EXYNOS5433_SLEEP_RESET_MIF_SYS_PWR_REG,               { 0x1, 0x1, 0x0 } },
> +       { EXYNOS5433_MEMORY_TOP_SYS_PWR_REG,                    { 0x3, 0x0, 0x0 } },
> +       { EXYNOS5433_PAD_RETENTION_LPDDR3_SYS_PWR_REG,          { 0x1, 0x0, 0x0 } },
> +       { EXYNOS5433_PAD_RETENTION_JTAG_SYS_PWR_REG,            { 0x1, 0x0, 0x0 } },
> +       { EXYNOS5433_PAD_RETENTION_TOP_SYS_PWR_REG,             { 0x1, 0x0, 0x0 } },
> +       { EXYNOS5433_PAD_RETENTION_UART_SYS_PWR_REG,            { 0x1, 0x0, 0x0 } },
> +       { EXYNOS5433_PAD_RETENTION_EBIA_SYS_PWR_REG,            { 0x1, 0x0, 0x0 } },
> +       { EXYNOS5433_PAD_RETENTION_EBIB_SYS_PWR_REG,            { 0x1, 0x0, 0x0 } },
> +       { EXYNOS5433_PAD_RETENTION_SPI_SYS_PWR_REG,             { 0x1, 0x0, 0x0 } },
> +       { EXYNOS5433_PAD_RETENTION_MIF_SYS_PWR_REG,             { 0x1, 0x0, 0x0 } },
> +       { EXYNOS5433_PAD_ISOLATION_SYS_PWR_REG,                 { 0x1, 0x0, 0x1 } },
> +       { EXYNOS5433_PAD_RETENTION_USBXTI_SYS_PWR_REG,          { 0x1, 0x0, 0x0 } },
> +       { EXYNOS5433_PAD_RETENTION_BOOTLDO_SYS_PWR_REG,         { 0x1, 0x0, 0x0 } },
> +       { EXYNOS5433_PAD_ISOLATION_MIF_SYS_PWR_REG,             { 0x1, 0x0, 0x1 } },
> +       { EXYNOS5433_PAD_RETENTION_FSYSGENIO_SYS_PWR_REG,       { 0x1, 0x0, 0x0 } },
> +       { EXYNOS5433_PAD_ALV_SEL_SYS_PWR_REG,                   { 0x1, 0x0, 0x0 } },
> +       { EXYNOS5433_XXTI_SYS_PWR_REG,                          { 0x1, 0x1, 0x0 } },
> +       { EXYNOS5433_XXTI26_SYS_PWR_REG,                        { 0x1, 0x0, 0x0 } },
> +       { EXYNOS5433_EXT_REGULATOR_SYS_PWR_REG,                 { 0x1, 0x1, 0x0 } },
> +       { EXYNOS5433_GPIO_MODE_SYS_PWR_REG,                     { 0x1, 0x0, 0x0 } },
> +       { EXYNOS5433_GPIO_MODE_FSYS0_SYS_PWR_REG,               { 0x1, 0x0, 0x0 } },
> +       { EXYNOS5433_GPIO_MODE_MIF_SYS_PWR_REG,                 { 0x1, 0x0, 0x0 } },
> +       { EXYNOS5433_GPIO_MODE_AUD_SYS_PWR_REG,                 { 0x1, 0x1, 0x0 } },
> +       { EXYNOS5433_GSCL_SYS_PWR_REG,                          { 0xF, 0x0, 0x0 } },
> +       { EXYNOS5433_CAM0_SYS_PWR_REG,                          { 0xF, 0x0, 0x0 } },
> +       { EXYNOS5433_MSCL_SYS_PWR_REG,                          { 0xF, 0x0, 0x0 } },
> +       { EXYNOS5433_G3D_SYS_PWR_REG,                           { 0xF, 0x0, 0x0 } },
> +       { EXYNOS5433_DISP_SYS_PWR_REG,                          { 0xF, 0x0, 0x0 } },
> +       { EXYNOS5433_CAM1_SYS_PWR_REG,                          { 0xF, 0x0, 0x0 } },
> +       { EXYNOS5433_AUD_SYS_PWR_REG,                           { 0xF, 0xF, 0x0 } },
> +       { EXYNOS5433_FSYS_SYS_PWR_REG,                          { 0xF, 0x0, 0x0 } },
> +       { EXYNOS5433_BUS2_SYS_PWR_REG,                          { 0xF, 0x0, 0x0 } },
> +       { EXYNOS5433_G2D_SYS_PWR_REG,                           { 0xF, 0x0, 0x0 } },
> +       { EXYNOS5433_ISP0_SYS_PWR_REG,                          { 0xF, 0x0, 0x0 } },
> +       { EXYNOS5433_MFC_SYS_PWR_REG,                           { 0xF, 0x0, 0x0 } },
> +       { EXYNOS5433_HEVC_SYS_PWR_REG,                          { 0xF, 0x0, 0x0 } },
> +       { EXYNOS5433_RESET_SLEEP_FSYS_SYS_PWR_REG,              { 0x1, 0x1, 0x0 } },
> +       { EXYNOS5433_RESET_SLEEP_BUS2_SYS_PWR_REG,              { 0x1, 0x1, 0x0 } },
> +       { PMU_TABLE_END, },
> +};
> +
> +static unsigned int const exynos5433_list_feed[] = {
> +       EXYNOS5433_ATLAS_NONCPU_OPTION,
> +       EXYNOS5433_APOLLO_NONCPU_OPTION,
> +       EXYNOS5433_TOP_PWR_OPTION,
> +       EXYNOS5433_TOP_PWR_MIF_OPTION,
> +       EXYNOS5433_AUD_OPTION,
> +       EXYNOS5433_CAM0_OPTION,
> +       EXYNOS5433_DISP_OPTION,
> +       EXYNOS5433_G2D_OPTION,
> +       EXYNOS5433_G3D_OPTION,
> +       EXYNOS5433_HEVC_OPTION,
> +       EXYNOS5433_MSCL_OPTION,
> +       EXYNOS5433_MFC_OPTION,
> +       EXYNOS5433_GSCL_OPTION,
> +       EXYNOS5433_FSYS_OPTION,
> +       EXYNOS5433_ISP_OPTION,
> +       EXYNOS5433_BUS2_OPTION,
> +};
> +
> +static unsigned int const exynos5433_list_pad_retention[] = {
> +       EXYNOS5433_PAD_RETENTION_LPDDR3_OPTION,
> +       EXYNOS5433_PAD_RETENTION_AUD_OPTION,
> +       EXYNOS5433_PAD_RETENTION_MMC2_OPTION,
> +       EXYNOS5433_PAD_RETENTION_TOP_OPTION,
> +       EXYNOS5433_PAD_RETENTION_UART_OPTION,
> +       EXYNOS5433_PAD_RETENTION_MMC0_OPTION,
> +       EXYNOS5433_PAD_RETENTION_MMC1_OPTION,
> +       EXYNOS5433_PAD_RETENTION_EBIA_OPTION,
> +       EXYNOS5433_PAD_RETENTION_EBIB_OPTION,
> +       EXYNOS5433_PAD_RETENTION_SPI_OPTION,
> +       EXYNOS5433_PAD_RETENTION_MIF_OPTION,
> +       EXYNOS5433_PAD_RETENTION_USBXTI_OPTION,
> +       EXYNOS5433_PAD_RETENTION_BOOTLDO_OPTION,
> +       EXYNOS5433_PAD_RETENTION_UFS_OPTION,
> +       EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION,

Looks like conflicting with existing
drivers/pinctrl/samsung/pinctrl-exynos-arm64.c... and probably this
should be part of pinctrl driver's suspend/resume paths.

> +};
> +
> +static void exynos5433_set_wakeupmask(enum sys_powerdown mode)
> +{
> +       u32 intmask = 0;
> +
> +       pmu_raw_writel(exynos_get_eint_wake_mask(),
> +                                       EXYNOS5433_EINT_WAKEUP_MASK);
> +
> +       /* Disable WAKEUP event monitor */
> +       intmask = pmu_raw_readl(EXYNOS5433_WAKEUP_MASK);
> +       intmask &= ~(1 << 31);

This should have a define. Maybe it is an already defined field like
S5P_CORE_AUTOWAKEUP_EN or S5P_PS_HOLD_EN?

> +       pmu_raw_writel(intmask, EXYNOS5433_WAKEUP_MASK);
> +
> +       pmu_raw_writel(0xFFFF0000, EXYNOS5433_WAKEUP_MASK2);
> +       pmu_raw_writel(0xFFFF0000, EXYNOS5433_WAKEUP_MASK3);

Both need explaining what you are masking, preferably by appropriate
comment and maybe also define for raw constants.

> +}
> +
> +static void exynos5433_pmu_central_seq(bool enable)
> +{
> +       unsigned int tmp;
> +
> +       tmp = pmu_raw_readl(EXYNOS5433_CENTRAL_SEQ_CONFIGURATION);
> +       if (enable)
> +               tmp &= ~EXYNOS5433_CENTRALSEQ_PWR_CFG;
> +       else
> +               tmp |= EXYNOS5433_CENTRALSEQ_PWR_CFG;
> +       pmu_raw_writel(tmp, EXYNOS5433_CENTRAL_SEQ_CONFIGURATION);
> +
> +       tmp = pmu_raw_readl(EXYNOS5433_CENTRAL_SEQ_MIF_CONFIGURATION);
> +       if (enable)
> +               tmp &= ~EXYNOS5433_CENTRALSEQ_PWR_CFG;
> +       else
> +               tmp |= EXYNOS5433_CENTRALSEQ_PWR_CFG;
> +       pmu_raw_writel(tmp, EXYNOS5433_CENTRAL_SEQ_MIF_CONFIGURATION);
> +}
> +
> +static void exynos5433_pmu_pad_retention_release(void)
> +{
> +       unsigned int tmp;
> +       int i;

unsigned int i

> +
> +       for (i = 0 ; i < ARRAY_SIZE(exynos5433_list_pad_retention) ; i++) {
> +               tmp = pmu_raw_readl(exynos5433_list_pad_retention[i]);
> +               tmp |= EXYNOS5433_INITIATE_WAKEUP_FROM_LOWPOWER;
> +               pmu_raw_writel(tmp, exynos5433_list_pad_retention[i]);
> +       }
> +}
> +
> +static void exynos5433_pmu_init(void)
> +{
> +       unsigned int tmp;
> +       int i, cluster, cpu;

unsigned int i

> +
> +       /* Enable non retention flip-flop reset for wakeup */
> +       tmp = pmu_raw_readl(EXYNOS5433_PMU_SPARE0);
> +       tmp |= EXYNOS5433_EN_NONRET_RESET;
> +       pmu_raw_writel(tmp, EXYNOS5433_PMU_SPARE0);

This is spare register. Who is using it? Firmware? Please add its
usage also in Documentation/arm/Samsung/Bootloader-interface.txt.

> +
> +        /* Enable only SC_FEEDBACK for the register list */
> +       for (i = 0 ; i < ARRAY_SIZE(exynos5433_list_feed) ; i++) {
> +               tmp = pmu_raw_readl(exynos5433_list_feed[i]);
> +               tmp &= ~EXYNOS5_USE_SC_COUNTER;
> +               tmp |= EXYNOS5_USE_SC_FEEDBACK;
> +               pmu_raw_writel(tmp, exynos5433_list_feed[i]);
> +       }
> +
> +       /*
> +        * Disable automatic L2 flush, Disable L2 retention and
> +        * Enable STANDBYWFIL2, ACE/ACP
> +        */
> +       for (cluster = 0; cluster < 2; cluster++) {
> +               tmp = pmu_raw_readl(EXYNOS5433_ATLAS_L2_OPTION + (cluster * 0x20));

I would prefer to follow the convention for similar registers for cores, like:
EXYNOS_ARM_CORE_CONFIGURATION
EXYNOS_ARM_CORE_STATUS

This moves the offset into the header, along to other register offsets.

> +               tmp &= ~(EXYNOS5433_USE_AUTO_L2FLUSHREQ | EXYNOS5433_USE_RETENTION);
> +
> +               if (cluster == 0) {
> +                       tmp |= (EXYNOS5433_USE_STANDBYWFIL2 |
> +                               EXYNOS5433_USE_DEACTIVATE_ACE |
> +                               EXYNOS5433_USE_DEACTIVATE_ACP);
> +               }
> +               pmu_raw_writel(tmp, EXYNOS5433_ATLAS_L2_OPTION + (cluster * 0x20));
> +       }
> +
> +       /*
> +        * Enable both SC_COUNTER and SC_FEEDBACK for the CPUs
> +        * Use STANDBYWFI and SMPEN to indicate that core is ready to enter
> +        * low power mode
> +        */
> +       for (cpu = 0; cpu < 8; cpu++) {
> +               tmp = pmu_raw_readl(EXYNOS5433_CPU_OPTION(cpu));
> +               tmp |= (EXYNOS5_USE_SC_FEEDBACK | EXYNOS5_USE_SC_COUNTER);
> +               tmp |= EXYNOS5433_USE_SMPEN;
> +               tmp |= EXYNOS5433_USE_STANDBYWFI;
> +               tmp &= ~EXYNOS5433_USE_STANDBYWFE;
> +               pmu_raw_writel(tmp, EXYNOS5433_CPU_OPTION(cpu));
> +
> +               tmp = pmu_raw_readl(EXYNOS5433_CPU_DURATION(cpu));
> +               tmp |= EXYNOS5433_DUR_WAIT_RESET;
> +               tmp &= ~EXYNOS5433_DUR_SCALL;
> +               tmp |= EXYNOS5433_DUR_SCALL_VALUE;
> +               pmu_raw_writel(tmp, EXYNOS5433_CPU_DURATION(cpu));
> +       }
> +
> +       /* Skip atlas block power-off during automatic power down sequence */
> +       tmp = pmu_raw_readl(EXYNOS5433_ATLAS_CPUSEQUENCER_OPTION);
> +       tmp |= EXYNOS5433_SKIP_BLK_PWR_DOWN;
> +       pmu_raw_writel(tmp, EXYNOS5433_ATLAS_CPUSEQUENCER_OPTION);
> +
> +       /* Limit in-rush current during local power up of cores */
> +       tmp = pmu_raw_readl(EXYNOS5433_UP_SCHEDULER);
> +       tmp |= EXYNOS5433_ENABLE_ATLAS_CPU;
> +       pmu_raw_writel(tmp, EXYNOS5433_UP_SCHEDULER);
> +}
> +
> +static void exynos5433_powerdown_conf(enum sys_powerdown mode)
> +{
> +       switch (mode) {
> +       case SYS_SLEEP:
> +               exynos5433_set_wakeupmask(mode);
> +               exynos5433_pmu_central_seq(true);
> +               break;
> +       default:
> +               break;
> +       };
> +}
> +
> +static void exynos5433_powerup_conf(enum sys_powerdown mode)
> +{
> +       unsigned int wakeup;
> +
> +       switch (mode) {
> +       case SYS_SLEEP:
> +               wakeup = pmu_raw_readl(EXYNOS5433_CENTRAL_SEQ_CONFIGURATION);
> +               wakeup &= EXYNOS5433_CENTRALSEQ_PWR_CFG;
> +               if (wakeup)
> +                       exynos5433_pmu_pad_retention_release();
> +               else
> +                       exynos5433_pmu_central_seq(false);

I do not understand what you want to achieve here. Re-suspend?

> +               break;
> +       default:
> +               break;
> +       };
> +}
> +
> +const struct exynos_pmu_data exynos5433_pmu_data = {
> +       .pmu_config             = exynos5433_pmu_config,
> +       .pmu_init               = exynos5433_pmu_init,
> +       .powerdown_conf         = exynos5433_powerdown_conf,
> +       .powerup_conf           = exynos5433_powerup_conf,
> +};
> diff --git a/include/linux/soc/samsung/exynos-regs-pmu.h b/include/linux/soc/samsung/exynos-regs-pmu.h
> index bebdde5dccd6..93a52d133ba1 100644
> --- a/include/linux/soc/samsung/exynos-regs-pmu.h
> +++ b/include/linux/soc/samsung/exynos-regs-pmu.h
> @@ -645,7 +645,110 @@
>                                          | EXYNOS5420_KFC_USE_STANDBY_WFI3)
>
>  /* For EXYNOS5433 */
> +#define EXYNOS5433_UP_SCHEDULER                                        (0x0120)
> +#define EXYNOS5433_CENTRAL_SEQ_CONFIGURATION                   (0x0200)
> +#define EXYNOS5433_CENTRAL_SEQ_MIF_CONFIGURATION               (0x0240)
> +#define EXYNOS5433_EINT_WAKEUP_MASK                            (0x060C)
> +#define EXYNOS5433_WAKEUP_MASK                                 (0x0610)
> +#define EXYNOS5433_WAKEUP_MASK2                                        (0x0614)
> +#define EXYNOS5433_WAKEUP_MASK3                                        (0x0618)
> +#define EXYNOS5433_EINT_WAKEUP_MASK1                           (0x062C)
>  #define EXYNOS5433_USBHOST30_PHY_CONTROL                       (0x0728)
> +#define EXYNOS5433_PMU_SPARE0                                  (0x0900)
> +#define EXYNOS5433_ATLAS_CPU0_SYS_PWR_REG                      (0x1000)
> +#define EXYNOS5433_DIS_IRQ_ATLAS_CPU0_CENTRAL_SYS_PWR_REG      (0x1008)
> +#define EXYNOS5433_ATLAS_CPU1_SYS_PWR_REG                      (0x1010)
> +#define EXYNOS5433_DIS_IRQ_ATLAS_CPU1_CENTRAL_SYS_PWR_REG      (0x1018)
> +#define EXYNOS5433_ATLAS_CPU2_SYS_PWR_REG                      (0x1020)
> +#define EXYNOS5433_DIS_IRQ_ATLAS_CPU2_CENTRAL_SYS_PWR_REG      (0x1028)
> +#define EXYNOS5433_ATLAS_CPU3_SYS_PWR_REG                      (0x1030)
> +#define EXYNOS5433_DIS_IRQ_ATLAS_CPU3_CENTRAL_SYS_PWR_REG      (0x1038)
> +#define EXYNOS5433_APOLLO_CPU0_SYS_PWR_REG                     (0x1040)
> +#define EXYNOS5433_DIS_IRQ_APOLLO_CPU0_CENTRAL_SYS_PWR_REG     (0x1048)
> +#define EXYNOS5433_APOLLO_CPU1_SYS_PWR_REG                     (0x1050)
> +#define EXYNOS5433_DIS_IRQ_APOLLO_CPU1_CENTRAL_SYS_PWR_REG     (0x1058)
> +#define EXYNOS5433_APOLLO_CPU2_SYS_PWR_REG                     (0x1060)
> +#define EXYNOS5433_DIS_IRQ_APOLLO_CPU2_CENTRAL_SYS_PWR_REG     (0x1068)
> +#define EXYNOS5433_APOLLO_CPU3_SYS_PWR_REG                     (0x1070)
> +#define EXYNOS5433_DIS_IRQ_APOLLO_CPU3_CENTRAL_SYS_PWR_REG     (0x1078)
> +#define EXYNOS5433_ATLAS_NONCPU_SYS_PWR_REG                    (0x1080)
> +#define EXYNOS5433_ATLAS_L2_SYS_PWR_REG                                (0x10C0)
> +#define EXYNOS5433_APOLLO_L2_SYS_PWR_REG                       (0x10C4)
> +#define EXYNOS5433_APOLLO_NONCPU_SYS_PWR_REG                   (0x1084)
> +#define EXYNOS5433_A5IS_SYS_PWR_REG                            (0x10B0)
> +#define EXYNOS5433_DIS_IRQ_A5IS_LOCAL_SYS_PWR_REG              (0x10B4)
> +#define EXYNOS5433_DIS_IRQ_A5IS_CENTRAL_SYS_PWR_REG            (0x10B8)
> +#define EXYNOS5433_CLKSTOP_CMU_TOP_SYS_PWR_REG                 (0x1100)
> +#define EXYNOS5433_CLKRUN_CMU_TOP_SYS_PWR_REG                  (0x1104)
> +#define EXYNOS5433_RESET_CMU_TOP_SYS_PWR_REG                   (0x110C)
> +#define EXYNOS5433_RESET_CPUCLKSTOP_SYS_PWR_REG                        (0x111C)
> +#define EXYNOS5433_CLKSTOP_CMU_MIF_SYS_PWR_REG                 (0x1120)
> +#define EXYNOS5433_CLKRUN_CMU_MIF_SYS_PWR_REG                  (0x1124)
> +#define EXYNOS5433_RESET_CMU_MIF_SYS_PWR_REG                   (0x112C)
> +#define EXYNOS5433_DDRPHY_DLLLOCK_SYS_PWR_REG                  (0x1138)
> +#define EXYNOS5433_DISABLE_PLL_CMU_TOP_SYS_PWR_REG             (0x1140)
> +#define EXYNOS5433_DISABLE_PLL_AUD_PLL_SYS_PWR_REG             (0x1144)
> +#define EXYNOS5433_DISABLE_PLL_CMU_MIF_SYS_PWR_REG             (0x1160)
> +#define EXYNOS5433_TOP_BUS_SYS_PWR_REG                         (0x1180)
> +#define EXYNOS5433_TOP_RETENTION_SYS_PWR_REG                   (0x1184)
> +#define EXYNOS5433_TOP_PWR_SYS_PWR_REG                         (0x1188)
> +#define EXYNOS5433_TOP_BUS_MIF_SYS_PWR_REG                     (0x1190)
> +#define EXYNOS5433_TOP_RETENTION_MIF_SYS_PWR_REG               (0x1194)
> +#define EXYNOS5433_TOP_PWR_MIF_SYS_PWR_REG                     (0x1198)
> +#define EXYNOS5433_LOGIC_RESET_SYS_PWR_REG                     (0x11A0)
> +#define EXYNOS5433_OSCCLK_GATE_SYS_PWR_REG                     (0x11A4)
> +#define EXYNOS5433_SLEEP_RESET_SYS_PWR_REG                     (0x11A8)
> +#define EXYNOS5433_LOGIC_RESET_MIF_SYS_PWR_REG                 (0x11B0)
> +#define EXYNOS5433_OSCCLK_GATE_MIF_SYS_PWR_REG                 (0x11B4)
> +#define EXYNOS5433_SLEEP_RESET_MIF_SYS_PWR_REG                 (0x11B8)
> +#define EXYNOS5433_MEMORY_TOP_SYS_PWR_REG                      (0x11C0)
> +#define EXYNOS5433_PAD_RETENTION_LPDDR3_SYS_PWR_REG            (0x1200)
> +#define EXYNOS5433_PAD_RETENTION_JTAG_SYS_PWR_REG              (0x1208)
> +#define EXYNOS5433_PAD_RETENTION_TOP_SYS_PWR_REG               (0x1220)
> +#define EXYNOS5433_PAD_RETENTION_UART_SYS_PWR_REG              (0x1224)
> +#define EXYNOS5433_PAD_RETENTION_EBIA_SYS_PWR_REG              (0x1230)
> +#define EXYNOS5433_PAD_RETENTION_EBIB_SYS_PWR_REG              (0x1234)
> +#define EXYNOS5433_PAD_RETENTION_SPI_SYS_PWR_REG               (0x1238)
> +#define EXYNOS5433_PAD_RETENTION_MIF_SYS_PWR_REG               (0x123C)
> +#define EXYNOS5433_PAD_ISOLATION_SYS_PWR_REG                   (0x1240)
> +#define EXYNOS5433_PAD_RETENTION_USBXTI_SYS_PWR_REG            (0x1244)
> +#define EXYNOS5433_PAD_RETENTION_BOOTLDO_SYS_PWR_REG           (0x1248)
> +#define EXYNOS5433_PAD_ISOLATION_MIF_SYS_PWR_REG               (0x1250)
> +#define EXYNOS5433_PAD_RETENTION_FSYSGENIO_SYS_PWR_REG         (0x1254)
> +#define EXYNOS5433_PAD_ALV_SEL_SYS_PWR_REG                     (0x1260)
> +#define EXYNOS5433_XXTI_SYS_PWR_REG                            (0x1284)
> +#define EXYNOS5433_XXTI26_SYS_PWR_REG                          (0x1288)
> +#define EXYNOS5433_EXT_REGULATOR_SYS_PWR_REG                   (0x12C0)
> +#define EXYNOS5433_GPIO_MODE_SYS_PWR_REG                       (0x1300)
> +#define EXYNOS5433_GPIO_MODE_FSYS0_SYS_PWR_REG                 (0x1304)
> +#define EXYNOS5433_GPIO_MODE_MIF_SYS_PWR_REG                   (0x1320)
> +#define EXYNOS5433_GPIO_MODE_AUD_SYS_PWR_REG                   (0x1340)
> +#define EXYNOS5433_GSCL_SYS_PWR_REG                            (0x1400)
> +#define EXYNOS5433_CAM0_SYS_PWR_REG                            (0x1404)
> +#define EXYNOS5433_MSCL_SYS_PWR_REG                            (0x1408)
> +#define EXYNOS5433_G3D_SYS_PWR_REG                             (0x140C)
> +#define EXYNOS5433_DISP_SYS_PWR_REG                            (0x1410)
> +#define EXYNOS5433_CAM1_SYS_PWR_REG                            (0x1414)
> +#define EXYNOS5433_AUD_SYS_PWR_REG                             (0x1418)
> +#define EXYNOS5433_FSYS_SYS_PWR_REG                            (0x141C)
> +#define EXYNOS5433_BUS2_SYS_PWR_REG                            (0x1420)
> +#define EXYNOS5433_G2D_SYS_PWR_REG                             (0x1424)
> +#define EXYNOS5433_ISP0_SYS_PWR_REG                            (0x1428)
> +#define EXYNOS5433_MFC_SYS_PWR_REG                             (0x1430)
> +#define EXYNOS5433_HEVC_SYS_PWR_REG                            (0x1438)
> +#define EXYNOS5433_RESET_SLEEP_FSYS_SYS_PWR_REG                        (0x15DC)
> +#define EXYNOS5433_RESET_SLEEP_BUS2_SYS_PWR_REG                        (0x15E0)
> +#define EXYNOS5433_ATLAS_CPU0_OPTION                           (0x2008)
> +#define EXYNOS5433_CPU_OPTION(_nr)                             (EXYNOS5433_ATLAS_CPU0_OPTION + (_nr) * 0x80)
> +#define EXYNOS5433_ATLAS_CPU0_DURATION0                                (0x2010)
> +#define EXYNOS5433_CPU_DURATION(_nr)                           (EXYNOS5433_ATLAS_CPU0_DURATION0 + (_nr) * 0x80)
> +#define EXYNOS5433_ATLAS_NONCPU_OPTION                         (0x2408)
> +#define EXYNOS5433_APOLLO_NONCPU_OPTION                                (0x2428)
> +#define EXYNOS5433_ATLAS_CPUSEQUENCER_OPTION                   (0x2488)
> +#define EXYNOS5433_ATLAS_L2_OPTION                             (0x2608)
> +#define EXYNOS5433_TOP_PWR_MIF_OPTION                          (0x2CC8)
> +#define EXYNOS5433_TOP_PWR_OPTION                              (0x2C48)
> +#define EXYNOS5433_PAD_RETENTION_LPDDR3_OPTION                 (0x3008)
>  #define EXYNOS5433_PAD_RETENTION_AUD_OPTION                    (0x3028)
>  #define EXYNOS5433_PAD_RETENTION_MMC2_OPTION                   (0x30C8)
>  #define EXYNOS5433_PAD_RETENTION_TOP_OPTION                    (0x3108)
> @@ -660,5 +763,50 @@
>  #define EXYNOS5433_PAD_RETENTION_BOOTLDO_OPTION                        (0x3248)
>  #define EXYNOS5433_PAD_RETENTION_UFS_OPTION                    (0x3268)
>  #define EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION              (0x32A8)
> +#define EXYNOS5433_PS_HOLD_CONTROL                             (0x330C)
> +#define EXYNOS5433_GSCL_OPTION                                 (0x4008)
> +#define EXYNOS5433_CAM0_OPTION                                 (0x4028)
> +#define EXYNOS5433_MSCL_OPTION                                 (0x4048)
> +#define EXYNOS5433_G3D_OPTION                                  (0x4068)
> +#define EXYNOS5433_DISP_OPTION                                 (0x4088)
> +#define EXYNOS5433_AUD_OPTION                                  (0x40C8)
> +#define EXYNOS5433_FSYS_OPTION                                 (0x40E8)
> +#define EXYNOS5433_BUS2_OPTION                                 (0x4108)
> +#define EXYNOS5433_G2D_OPTION                                  (0x4128)
> +#define EXYNOS5433_ISP_OPTION                                  (0x4148)
> +#define EXYNOS5433_MFC_OPTION                                  (0x4188)
> +#define EXYNOS5433_HEVC_OPTION                                 (0x41C8)
> +
> +/* EXYNOS5433_PMU_SPARE0 */
> +#define EXYNOS5433_EN_NONRET_RESET                             (1 << 0)

Use BIT(0) here and in other places.

Best regards,
Krzysztof

> +
> +/* EXYNOS5433_CENTRAL_SEQ_CONFIGURATION */
> +#define EXYNOS5433_CENTRALSEQ_PWR_CFG                          (0x1 << 16)
> +
> +/* EXYNOS5433_ATLAS_L2_OPTION */
> +#define EXYNOS5433_USE_DEACTIVATE_ACE                          (0x1 << 19)
> +#define EXYNOS5433_USE_DEACTIVATE_ACP                          (0x1 << 18)
> +#define EXYNOS5433_USE_AUTO_L2FLUSHREQ                         (0x1 << 17)
> +#define EXYNOS5433_USE_STANDBYWFIL2                            (0x1 << 16)
> +#define EXYNOS5433_USE_RETENTION                               (0x1 << 4)
> +
> +/* EXYNOS5433_CPU_OPTION */
> +#define EXYNOS5433_USE_SMPEN                                   (0x1 << 28)
> +#define EXYNOS5433_USE_STANDBYWFE                              (0x1 << 24)
> +#define EXYNOS5433_USE_STANDBYWFI                              (0x1 << 16)
> +
> +/* EXYNOS5433_PAD_RETENTION_*_OPTION */
> +#define EXYNOS5433_INITIATE_WAKEUP_FROM_LOWPOWER               (0x1 << 28)
> +
> +/* EXYNOS5433_CPU_DURATION */
> +#define EXYNOS5433_DUR_WAIT_RESET                              (0xF << 20)
> +#define EXYNOS5433_DUR_SCALL                                   (0xF << 4)
> +#define EXYNOS5433_DUR_SCALL_VALUE                             (0x1 << 4)
> +
> +/* EXYNOS5433_ATLAS_CPUSEQUENCER_OPTION */
> +#define EXYNOS5433_SKIP_BLK_PWR_DOWN                           (0x1 << 8)
> +
> +/* EXYNOS5433_UP_SCHEDULER */
> +#define EXYNOS5433_ENABLE_ATLAS_CPU                            (0x1 << 0)
>
>  #endif /* __LINUX_SOC_EXYNOS_REGS_PMU_H */
> --
> 1.9.1
>
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Re: [PATCH 3/9] soc: samsung: pmu: Add the PMU data of exynos5433 to support low-power state

[Chanwoo Choi]

On 2018년 01월 09일 21:23, Krzysztof Kozlowski wrote:
> On Tue, Jan 9, 2018 at 8:59 AM, Chanwoo Choi <cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> wrote:
>> This patch adds the PMU (Power Management Unit) data of exynos5433 SoC
>> in order to support the various power modes. Each power mode has
>> the different value for reducing the power-consumption.
>>
>> Signed-off-by: Jonghwa Lee <jonghwa3.lee-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
>> Signed-off-by: Chanwoo Choi <cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
>> ---
>>  arch/arm/mach-exynos/common.h               |   2 -
>>  drivers/soc/samsung/Makefile                |   3 +-
>>  drivers/soc/samsung/exynos-pmu.c            |   1 +
>>  drivers/soc/samsung/exynos-pmu.h            |   2 +
>>  drivers/soc/samsung/exynos5433-pmu.c        | 286 ++++++++++++++++++++++++++++
>>  include/linux/soc/samsung/exynos-regs-pmu.h | 148 ++++++++++++++
>>  6 files changed, 439 insertions(+), 3 deletions(-)
>>  create mode 100644 drivers/soc/samsung/exynos5433-pmu.c
>>
>> diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
>> index 098f84a149a3..afbc143a3d5d 100644
>> --- a/arch/arm/mach-exynos/common.h
>> +++ b/arch/arm/mach-exynos/common.h
>> @@ -125,8 +125,6 @@ enum {
>>  void exynos_set_boot_flag(unsigned int cpu, unsigned int mode);
>>  void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode);
>>
>> -extern u32 exynos_get_eint_wake_mask(void);
>> -
> 
> This does not look good. Does it compile without warnings on ARMv7 platforms?

I'll try to consolidate suspend-related code. I'll rework.

> 
>>  #ifdef CONFIG_PM_SLEEP
>>  extern void __init exynos_pm_init(void);
>>  #else
>> diff --git a/drivers/soc/samsung/Makefile b/drivers/soc/samsung/Makefile
>> index 29f294baac6e..d2e637339a45 100644
>> --- a/drivers/soc/samsung/Makefile
>> +++ b/drivers/soc/samsung/Makefile
>> @@ -2,5 +2,6 @@
>>  obj-$(CONFIG_EXYNOS_PMU)       += exynos-pmu.o
>>
>>  obj-$(CONFIG_EXYNOS_PMU_ARM_DRIVERS)   += exynos3250-pmu.o exynos4-pmu.o \
>> -                                       exynos5250-pmu.o exynos5420-pmu.o
>> +                                       exynos5250-pmu.o exynos5420-pmu.o \
>> +                                       exynos5433-pmu.o
>>  obj-$(CONFIG_EXYNOS_PM_DOMAINS) += pm_domains.o
>> diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsung/exynos-pmu.c
>> index cfc9de518344..7112d7b2749b 100644
>> --- a/drivers/soc/samsung/exynos-pmu.c
>> +++ b/drivers/soc/samsung/exynos-pmu.c
>> @@ -97,6 +97,7 @@ void exynos_sys_powerup_conf(enum sys_powerdown mode)
>>                 .data = exynos_pmu_data_arm_ptr(exynos5420_pmu_data),
>>         }, {
>>                 .compatible = "samsung,exynos5433-pmu",
>> +               .data = exynos_pmu_data_arm_ptr(exynos5433_pmu_data),
>>         },
>>         { /*sentinel*/ },
>>  };
>> diff --git a/drivers/soc/samsung/exynos-pmu.h b/drivers/soc/samsung/exynos-pmu.h
>> index efbaf8929252..895c786a2f4c 100644
>> --- a/drivers/soc/samsung/exynos-pmu.h
>> +++ b/drivers/soc/samsung/exynos-pmu.h
>> @@ -28,6 +28,7 @@ struct exynos_pmu_data {
>>  };
>>
>>  extern void __iomem *pmu_base_addr;
>> +extern u32 exynos_get_eint_wake_mask(void);
>>
>>  #ifdef CONFIG_EXYNOS_PMU_ARM_DRIVERS
>>  /* list of all exported SoC specific data */
>> @@ -36,6 +37,7 @@ struct exynos_pmu_data {
>>  extern const struct exynos_pmu_data exynos4412_pmu_data;
>>  extern const struct exynos_pmu_data exynos5250_pmu_data;
>>  extern const struct exynos_pmu_data exynos5420_pmu_data;
>> +extern const struct exynos_pmu_data exynos5433_pmu_data;
>>  #endif
>>
>>  extern void pmu_raw_writel(u32 val, u32 offset);
>> diff --git a/drivers/soc/samsung/exynos5433-pmu.c b/drivers/soc/samsung/exynos5433-pmu.c
>> new file mode 100644
>> index 000000000000..2571e61522f0
>> --- /dev/null
>> +++ b/drivers/soc/samsung/exynos5433-pmu.c
>> @@ -0,0 +1,286 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +//
>> +// Copyright (c) 2018 Samsung Electronics Co., Ltd.
>> +// Copyright (c) Jonghwa Lee <jonghwa3.lee-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
>> +// Copyright (c) Chanwoo Choi <cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> 
> Did you want to add here authorship notice or personal copyrights?

Remove personal info.

> 
>> +//
>> +// EXYNOS5433 - CPU PMU (Power Management Unit) support
>> +
>> +#include <linux/soc/samsung/exynos-regs-pmu.h>
>> +#include <linux/soc/samsung/exynos-pmu.h>
>> +
>> +#include "exynos-pmu.h"
>> +
>> +static struct exynos_pmu_conf exynos5433_pmu_config[] = {
> 
> This should be also const.

OK.

> 
>> +       /* { .offset = address, .val = { AFTR, LPA, SLEEP } } */
>> +       { EXYNOS5433_ATLAS_CPU0_SYS_PWR_REG,                    { 0x0, 0x0, 0x8 } },
>> +       { EXYNOS5433_DIS_IRQ_ATLAS_CPU0_CENTRAL_SYS_PWR_REG,    { 0x0, 0x0, 0x0 } },
>> +       { EXYNOS5433_ATLAS_CPU1_SYS_PWR_REG,                    { 0x0, 0x0, 0x8 } },
>> +       { EXYNOS5433_DIS_IRQ_ATLAS_CPU1_CENTRAL_SYS_PWR_REG,    { 0x0, 0x0, 0x0 } },
>> +       { EXYNOS5433_ATLAS_CPU2_SYS_PWR_REG,                    { 0x0, 0x0, 0x8 } },
>> +       { EXYNOS5433_DIS_IRQ_ATLAS_CPU2_CENTRAL_SYS_PWR_REG,    { 0x0, 0x0, 0x0 } },
>> +       { EXYNOS5433_ATLAS_CPU3_SYS_PWR_REG,                    { 0x0, 0x0, 0x8 } },
>> +       { EXYNOS5433_DIS_IRQ_ATLAS_CPU3_CENTRAL_SYS_PWR_REG,    { 0x0, 0x0, 0x0 } },
>> +       { EXYNOS5433_APOLLO_CPU0_SYS_PWR_REG,                   { 0x0, 0x0, 0x8 } },
>> +       { EXYNOS5433_DIS_IRQ_APOLLO_CPU0_CENTRAL_SYS_PWR_REG,   { 0x0, 0x0, 0x0 } },
>> +       { EXYNOS5433_APOLLO_CPU1_SYS_PWR_REG,                   { 0x0, 0x0, 0x8 } },
>> +       { EXYNOS5433_DIS_IRQ_APOLLO_CPU1_CENTRAL_SYS_PWR_REG,   { 0x0, 0x0, 0x0 } },
>> +       { EXYNOS5433_APOLLO_CPU2_SYS_PWR_REG,                   { 0x0, 0x0, 0x8 } },
>> +       { EXYNOS5433_DIS_IRQ_APOLLO_CPU2_CENTRAL_SYS_PWR_REG,   { 0x0, 0x0, 0x0 } },
>> +       { EXYNOS5433_APOLLO_CPU3_SYS_PWR_REG,                   { 0x0, 0x0, 0x8 } },
>> +       { EXYNOS5433_DIS_IRQ_APOLLO_CPU3_CENTRAL_SYS_PWR_REG,   { 0x0, 0x0, 0x0 } },
>> +       { EXYNOS5433_ATLAS_NONCPU_SYS_PWR_REG,                  { 0x0, 0x0, 0x8 } },
>> +       { EXYNOS5433_APOLLO_NONCPU_SYS_PWR_REG,                 { 0x0, 0x0, 0x8 } },
>> +       { EXYNOS5433_A5IS_SYS_PWR_REG,                          { 0x0, 0x0, 0x0 } },
>> +       { EXYNOS5433_DIS_IRQ_A5IS_LOCAL_SYS_PWR_REG,            { 0x0, 0x0, 0x0 } },
>> +       { EXYNOS5433_DIS_IRQ_A5IS_CENTRAL_SYS_PWR_REG,          { 0x0, 0x0, 0x0 } },
>> +       { EXYNOS5433_ATLAS_L2_SYS_PWR_REG,                      { 0x0, 0x0, 0x7 } },
>> +       { EXYNOS5433_APOLLO_L2_SYS_PWR_REG,                     { 0x0, 0x0, 0x7 } },
>> +       { EXYNOS5433_CLKSTOP_CMU_TOP_SYS_PWR_REG,               { 0x1, 0x0, 0x0 } },
>> +       { EXYNOS5433_CLKRUN_CMU_TOP_SYS_PWR_REG,                { 0x1, 0x0, 0x0 } },
>> +       { EXYNOS5433_RESET_CMU_TOP_SYS_PWR_REG,                 { 0x1, 0x0, 0x0 } },
>> +       { EXYNOS5433_RESET_CPUCLKSTOP_SYS_PWR_REG,              { 0x1, 0x1, 0x0 } },
>> +       { EXYNOS5433_CLKSTOP_CMU_MIF_SYS_PWR_REG,               { 0x1, 0x0, 0x0 } },
>> +       { EXYNOS5433_CLKRUN_CMU_MIF_SYS_PWR_REG,                { 0x1, 0x1, 0x0 } },
>> +       { EXYNOS5433_RESET_CMU_MIF_SYS_PWR_REG,                 { 0x1, 0x0, 0x0 } },
>> +       { EXYNOS5433_DDRPHY_DLLLOCK_SYS_PWR_REG,                { 0x1, 0x1, 0x1 } },
>> +       { EXYNOS5433_DISABLE_PLL_CMU_TOP_SYS_PWR_REG,           { 0x1, 0x0, 0x0 } },
>> +       { EXYNOS5433_DISABLE_PLL_AUD_PLL_SYS_PWR_REG,           { 0x1, 0x1, 0x0 } },
>> +       { EXYNOS5433_DISABLE_PLL_CMU_MIF_SYS_PWR_REG,           { 0x1, 0x0, 0x0 } },
>> +       { EXYNOS5433_TOP_BUS_SYS_PWR_REG,                       { 0x7, 0x0, 0x0 } },
>> +       { EXYNOS5433_TOP_RETENTION_SYS_PWR_REG,                 { 0x1, 0x0, 0x1 } },
>> +       { EXYNOS5433_TOP_PWR_SYS_PWR_REG,                       { 0x3, 0x0, 0x3 } },
>> +       { EXYNOS5433_TOP_BUS_MIF_SYS_PWR_REG,                   { 0x7, 0x0, 0x0 } },
>> +       { EXYNOS5433_TOP_RETENTION_MIF_SYS_PWR_REG,             { 0x1, 0x0, 0x1 } },
>> +       { EXYNOS5433_TOP_PWR_MIF_SYS_PWR_REG,                   { 0x3, 0x0, 0x3 } },
>> +       { EXYNOS5433_LOGIC_RESET_SYS_PWR_REG,                   { 0x1, 0x0, 0x0 } },
>> +       { EXYNOS5433_OSCCLK_GATE_SYS_PWR_REG,                   { 0x1, 0x0, 0x1 } },
>> +       { EXYNOS5433_SLEEP_RESET_SYS_PWR_REG,                   { 0x1, 0x1, 0x0 } },
>> +       { EXYNOS5433_LOGIC_RESET_MIF_SYS_PWR_REG,               { 0x1, 0x0, 0x0 } },
>> +       { EXYNOS5433_OSCCLK_GATE_MIF_SYS_PWR_REG,               { 0x1, 0x0, 0x1 } },
>> +       { EXYNOS5433_SLEEP_RESET_MIF_SYS_PWR_REG,               { 0x1, 0x1, 0x0 } },
>> +       { EXYNOS5433_MEMORY_TOP_SYS_PWR_REG,                    { 0x3, 0x0, 0x0 } },
>> +       { EXYNOS5433_PAD_RETENTION_LPDDR3_SYS_PWR_REG,          { 0x1, 0x0, 0x0 } },
>> +       { EXYNOS5433_PAD_RETENTION_JTAG_SYS_PWR_REG,            { 0x1, 0x0, 0x0 } },
>> +       { EXYNOS5433_PAD_RETENTION_TOP_SYS_PWR_REG,             { 0x1, 0x0, 0x0 } },
>> +       { EXYNOS5433_PAD_RETENTION_UART_SYS_PWR_REG,            { 0x1, 0x0, 0x0 } },
>> +       { EXYNOS5433_PAD_RETENTION_EBIA_SYS_PWR_REG,            { 0x1, 0x0, 0x0 } },
>> +       { EXYNOS5433_PAD_RETENTION_EBIB_SYS_PWR_REG,            { 0x1, 0x0, 0x0 } },
>> +       { EXYNOS5433_PAD_RETENTION_SPI_SYS_PWR_REG,             { 0x1, 0x0, 0x0 } },
>> +       { EXYNOS5433_PAD_RETENTION_MIF_SYS_PWR_REG,             { 0x1, 0x0, 0x0 } },
>> +       { EXYNOS5433_PAD_ISOLATION_SYS_PWR_REG,                 { 0x1, 0x0, 0x1 } },
>> +       { EXYNOS5433_PAD_RETENTION_USBXTI_SYS_PWR_REG,          { 0x1, 0x0, 0x0 } },
>> +       { EXYNOS5433_PAD_RETENTION_BOOTLDO_SYS_PWR_REG,         { 0x1, 0x0, 0x0 } },
>> +       { EXYNOS5433_PAD_ISOLATION_MIF_SYS_PWR_REG,             { 0x1, 0x0, 0x1 } },
>> +       { EXYNOS5433_PAD_RETENTION_FSYSGENIO_SYS_PWR_REG,       { 0x1, 0x0, 0x0 } },
>> +       { EXYNOS5433_PAD_ALV_SEL_SYS_PWR_REG,                   { 0x1, 0x0, 0x0 } },
>> +       { EXYNOS5433_XXTI_SYS_PWR_REG,                          { 0x1, 0x1, 0x0 } },
>> +       { EXYNOS5433_XXTI26_SYS_PWR_REG,                        { 0x1, 0x0, 0x0 } },
>> +       { EXYNOS5433_EXT_REGULATOR_SYS_PWR_REG,                 { 0x1, 0x1, 0x0 } },
>> +       { EXYNOS5433_GPIO_MODE_SYS_PWR_REG,                     { 0x1, 0x0, 0x0 } },
>> +       { EXYNOS5433_GPIO_MODE_FSYS0_SYS_PWR_REG,               { 0x1, 0x0, 0x0 } },
>> +       { EXYNOS5433_GPIO_MODE_MIF_SYS_PWR_REG,                 { 0x1, 0x0, 0x0 } },
>> +       { EXYNOS5433_GPIO_MODE_AUD_SYS_PWR_REG,                 { 0x1, 0x1, 0x0 } },
>> +       { EXYNOS5433_GSCL_SYS_PWR_REG,                          { 0xF, 0x0, 0x0 } },
>> +       { EXYNOS5433_CAM0_SYS_PWR_REG,                          { 0xF, 0x0, 0x0 } },
>> +       { EXYNOS5433_MSCL_SYS_PWR_REG,                          { 0xF, 0x0, 0x0 } },
>> +       { EXYNOS5433_G3D_SYS_PWR_REG,                           { 0xF, 0x0, 0x0 } },
>> +       { EXYNOS5433_DISP_SYS_PWR_REG,                          { 0xF, 0x0, 0x0 } },
>> +       { EXYNOS5433_CAM1_SYS_PWR_REG,                          { 0xF, 0x0, 0x0 } },
>> +       { EXYNOS5433_AUD_SYS_PWR_REG,                           { 0xF, 0xF, 0x0 } },
>> +       { EXYNOS5433_FSYS_SYS_PWR_REG,                          { 0xF, 0x0, 0x0 } },
>> +       { EXYNOS5433_BUS2_SYS_PWR_REG,                          { 0xF, 0x0, 0x0 } },
>> +       { EXYNOS5433_G2D_SYS_PWR_REG,                           { 0xF, 0x0, 0x0 } },
>> +       { EXYNOS5433_ISP0_SYS_PWR_REG,                          { 0xF, 0x0, 0x0 } },
>> +       { EXYNOS5433_MFC_SYS_PWR_REG,                           { 0xF, 0x0, 0x0 } },
>> +       { EXYNOS5433_HEVC_SYS_PWR_REG,                          { 0xF, 0x0, 0x0 } },
>> +       { EXYNOS5433_RESET_SLEEP_FSYS_SYS_PWR_REG,              { 0x1, 0x1, 0x0 } },
>> +       { EXYNOS5433_RESET_SLEEP_BUS2_SYS_PWR_REG,              { 0x1, 0x1, 0x0 } },
>> +       { PMU_TABLE_END, },
>> +};
>> +
>> +static unsigned int const exynos5433_list_feed[] = {
>> +       EXYNOS5433_ATLAS_NONCPU_OPTION,
>> +       EXYNOS5433_APOLLO_NONCPU_OPTION,
>> +       EXYNOS5433_TOP_PWR_OPTION,
>> +       EXYNOS5433_TOP_PWR_MIF_OPTION,
>> +       EXYNOS5433_AUD_OPTION,
>> +       EXYNOS5433_CAM0_OPTION,
>> +       EXYNOS5433_DISP_OPTION,
>> +       EXYNOS5433_G2D_OPTION,
>> +       EXYNOS5433_G3D_OPTION,
>> +       EXYNOS5433_HEVC_OPTION,
>> +       EXYNOS5433_MSCL_OPTION,
>> +       EXYNOS5433_MFC_OPTION,
>> +       EXYNOS5433_GSCL_OPTION,
>> +       EXYNOS5433_FSYS_OPTION,
>> +       EXYNOS5433_ISP_OPTION,
>> +       EXYNOS5433_BUS2_OPTION,
>> +};
>> +
>> +static unsigned int const exynos5433_list_pad_retention[] = {
>> +       EXYNOS5433_PAD_RETENTION_LPDDR3_OPTION,
>> +       EXYNOS5433_PAD_RETENTION_AUD_OPTION,
>> +       EXYNOS5433_PAD_RETENTION_MMC2_OPTION,
>> +       EXYNOS5433_PAD_RETENTION_TOP_OPTION,
>> +       EXYNOS5433_PAD_RETENTION_UART_OPTION,
>> +       EXYNOS5433_PAD_RETENTION_MMC0_OPTION,
>> +       EXYNOS5433_PAD_RETENTION_MMC1_OPTION,
>> +       EXYNOS5433_PAD_RETENTION_EBIA_OPTION,
>> +       EXYNOS5433_PAD_RETENTION_EBIB_OPTION,
>> +       EXYNOS5433_PAD_RETENTION_SPI_OPTION,
>> +       EXYNOS5433_PAD_RETENTION_MIF_OPTION,
>> +       EXYNOS5433_PAD_RETENTION_USBXTI_OPTION,
>> +       EXYNOS5433_PAD_RETENTION_BOOTLDO_OPTION,
>> +       EXYNOS5433_PAD_RETENTION_UFS_OPTION,
>> +       EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION,
> 
> Looks like conflicting with existing
> drivers/pinctrl/samsung/pinctrl-exynos-arm64.c... and probably this
> should be part of pinctrl driver's suspend/resume paths.

OK. I'll remove it from this driver and then I'll handle PAD_RETENTION on pinctrl driver.

> 
>> +};
>> +
>> +static void exynos5433_set_wakeupmask(enum sys_powerdown mode)
>> +{
>> +       u32 intmask = 0;
>> +
>> +       pmu_raw_writel(exynos_get_eint_wake_mask(),
>> +                                       EXYNOS5433_EINT_WAKEUP_MASK);
>> +
>> +       /* Disable WAKEUP event monitor */
>> +       intmask = pmu_raw_readl(EXYNOS5433_WAKEUP_MASK);
>> +       intmask &= ~(1 << 31);
> 
> This should have a define. Maybe it is an already defined field like
> S5P_CORE_AUTOWAKEUP_EN or S5P_PS_HOLD_EN?

[31] bit of WAKEUP_MASK is the reserved bit on TRM.
But, when I checked it on released code from Samsung,
it is used to disable the wakeup event monitoring circuit.
I'll define it for readability.

> 
>> +       pmu_raw_writel(intmask, EXYNOS5433_WAKEUP_MASK);
>> +
>> +       pmu_raw_writel(0xFFFF0000, EXYNOS5433_WAKEUP_MASK2);
>> +       pmu_raw_writel(0xFFFF0000, EXYNOS5433_WAKEUP_MASK3);
> 
> Both need explaining what you are masking, preferably by appropriate
> comment and maybe also define for raw constants.

Initialize the reset value to EXYNOS5433_WAKEUP_MASK2/MASK3 which have
the 0xffff000 as the reset value on Exynos5433's TRM. I'll add the comment.

> 
>> +}
>> +
>> +static void exynos5433_pmu_central_seq(bool enable)
>> +{
>> +       unsigned int tmp;
>> +
>> +       tmp = pmu_raw_readl(EXYNOS5433_CENTRAL_SEQ_CONFIGURATION);
>> +       if (enable)
>> +               tmp &= ~EXYNOS5433_CENTRALSEQ_PWR_CFG;
>> +       else
>> +               tmp |= EXYNOS5433_CENTRALSEQ_PWR_CFG;
>> +       pmu_raw_writel(tmp, EXYNOS5433_CENTRAL_SEQ_CONFIGURATION);
>> +
>> +       tmp = pmu_raw_readl(EXYNOS5433_CENTRAL_SEQ_MIF_CONFIGURATION);
>> +       if (enable)
>> +               tmp &= ~EXYNOS5433_CENTRALSEQ_PWR_CFG;
>> +       else
>> +               tmp |= EXYNOS5433_CENTRALSEQ_PWR_CFG;
>> +       pmu_raw_writel(tmp, EXYNOS5433_CENTRAL_SEQ_MIF_CONFIGURATION);
>> +}
>> +
>> +static void exynos5433_pmu_pad_retention_release(void)
>> +{
>> +       unsigned int tmp;
>> +       int i;
> 
> unsigned int i

OK.

> 
>> +
>> +       for (i = 0 ; i < ARRAY_SIZE(exynos5433_list_pad_retention) ; i++) {
>> +               tmp = pmu_raw_readl(exynos5433_list_pad_retention[i]);
>> +               tmp |= EXYNOS5433_INITIATE_WAKEUP_FROM_LOWPOWER;
>> +               pmu_raw_writel(tmp, exynos5433_list_pad_retention[i]);
>> +       }
>> +}
>> +
>> +static void exynos5433_pmu_init(void)
>> +{
>> +       unsigned int tmp;
>> +       int i, cluster, cpu;
> 
> unsigned int i

OK.

> 
>> +
>> +       /* Enable non retention flip-flop reset for wakeup */
>> +       tmp = pmu_raw_readl(EXYNOS5433_PMU_SPARE0);
>> +       tmp |= EXYNOS5433_EN_NONRET_RESET;
>> +       pmu_raw_writel(tmp, EXYNOS5433_PMU_SPARE0);
> 
> This is spare register. Who is using it? Firmware? Please add its
> usage also in Documentation/arm/Samsung/Bootloader-interface.txt.

Unfortunately, when I checked the bootloader for the PMU_SPARE0 register,
the bootloader doesn't read/write for PMU_SPARE0. I fount this code
on code released by Samsung. The document doesn't include the detailed role.

> 
>> +
>> +        /* Enable only SC_FEEDBACK for the register list */
>> +       for (i = 0 ; i < ARRAY_SIZE(exynos5433_list_feed) ; i++) {
>> +               tmp = pmu_raw_readl(exynos5433_list_feed[i]);
>> +               tmp &= ~EXYNOS5_USE_SC_COUNTER;
>> +               tmp |= EXYNOS5_USE_SC_FEEDBACK;
>> +               pmu_raw_writel(tmp, exynos5433_list_feed[i]);
>> +       }
>> +
>> +       /*
>> +        * Disable automatic L2 flush, Disable L2 retention and
>> +        * Enable STANDBYWFIL2, ACE/ACP
>> +        */
>> +       for (cluster = 0; cluster < 2; cluster++) {
>> +               tmp = pmu_raw_readl(EXYNOS5433_ATLAS_L2_OPTION + (cluster * 0x20));
> 
> I would prefer to follow the convention for similar registers for cores, like:
> EXYNOS_ARM_CORE_CONFIGURATION
> EXYNOS_ARM_CORE_STATUS
> 
> This moves the offset into the header, along to other register offsets.

OK.

> 
>> +               tmp &= ~(EXYNOS5433_USE_AUTO_L2FLUSHREQ | EXYNOS5433_USE_RETENTION);
>> +
>> +               if (cluster == 0) {
>> +                       tmp |= (EXYNOS5433_USE_STANDBYWFIL2 |
>> +                               EXYNOS5433_USE_DEACTIVATE_ACE |
>> +                               EXYNOS5433_USE_DEACTIVATE_ACP);
>> +               }
>> +               pmu_raw_writel(tmp, EXYNOS5433_ATLAS_L2_OPTION + (cluster * 0x20));
>> +       }
>> +
>> +       /*
>> +        * Enable both SC_COUNTER and SC_FEEDBACK for the CPUs
>> +        * Use STANDBYWFI and SMPEN to indicate that core is ready to enter
>> +        * low power mode
>> +        */
>> +       for (cpu = 0; cpu < 8; cpu++) {
>> +               tmp = pmu_raw_readl(EXYNOS5433_CPU_OPTION(cpu));
>> +               tmp |= (EXYNOS5_USE_SC_FEEDBACK | EXYNOS5_USE_SC_COUNTER);
>> +               tmp |= EXYNOS5433_USE_SMPEN;
>> +               tmp |= EXYNOS5433_USE_STANDBYWFI;
>> +               tmp &= ~EXYNOS5433_USE_STANDBYWFE;
>> +               pmu_raw_writel(tmp, EXYNOS5433_CPU_OPTION(cpu));
>> +
>> +               tmp = pmu_raw_readl(EXYNOS5433_CPU_DURATION(cpu));
>> +               tmp |= EXYNOS5433_DUR_WAIT_RESET;
>> +               tmp &= ~EXYNOS5433_DUR_SCALL;
>> +               tmp |= EXYNOS5433_DUR_SCALL_VALUE;
>> +               pmu_raw_writel(tmp, EXYNOS5433_CPU_DURATION(cpu));
>> +       }
>> +
>> +       /* Skip atlas block power-off during automatic power down sequence */
>> +       tmp = pmu_raw_readl(EXYNOS5433_ATLAS_CPUSEQUENCER_OPTION);
>> +       tmp |= EXYNOS5433_SKIP_BLK_PWR_DOWN;
>> +       pmu_raw_writel(tmp, EXYNOS5433_ATLAS_CPUSEQUENCER_OPTION);
>> +
>> +       /* Limit in-rush current during local power up of cores */
>> +       tmp = pmu_raw_readl(EXYNOS5433_UP_SCHEDULER);
>> +       tmp |= EXYNOS5433_ENABLE_ATLAS_CPU;
>> +       pmu_raw_writel(tmp, EXYNOS5433_UP_SCHEDULER);
>> +}
>> +
>> +static void exynos5433_powerdown_conf(enum sys_powerdown mode)
>> +{
>> +       switch (mode) {
>> +       case SYS_SLEEP:
>> +               exynos5433_set_wakeupmask(mode);
>> +               exynos5433_pmu_central_seq(true);
>> +               break;
>> +       default:
>> +               break;
>> +       };
>> +}
>> +
>> +static void exynos5433_powerup_conf(enum sys_powerdown mode)
>> +{
>> +       unsigned int wakeup;
>> +
>> +       switch (mode) {
>> +       case SYS_SLEEP:
>> +               wakeup = pmu_raw_readl(EXYNOS5433_CENTRAL_SEQ_CONFIGURATION);
>> +               wakeup &= EXYNOS5433_CENTRALSEQ_PWR_CFG;
>> +               if (wakeup)
>> +                       exynos5433_pmu_pad_retention_release();
>> +               else
>> +                       exynos5433_pmu_central_seq(false);
> 
> I do not understand what you want to achieve here. Re-suspend?

The powerup_conf is unneeded anymore. So, I'll remove the powerup_conf.
Because 
- pad_retention should be handled in pinctrl driver according to your comment.
- exynos5433_pmu_central_seq(false) set the high for SYS_PWR_CFG field
of CENTRAL_SEQ_CONFIGURATION. But, When system-level low-power mode,
SYS_PWR_CFG field of CENTRAL_SEQ_CONFIGURATION register is automatically
cleared to high. So, exynos5433_pmu_central_seq(false) call is unneeded.

> 
>> +               break;
>> +       default:
>> +               break;
>> +       };
>> +}
>> +
>> +const struct exynos_pmu_data exynos5433_pmu_data = {
>> +       .pmu_config             = exynos5433_pmu_config,
>> +       .pmu_init               = exynos5433_pmu_init,
>> +       .powerdown_conf         = exynos5433_powerdown_conf,
>> +       .powerup_conf           = exynos5433_powerup_conf,
>> +};
>> diff --git a/include/linux/soc/samsung/exynos-regs-pmu.h b/include/linux/soc/samsung/exynos-regs-pmu.h
>> index bebdde5dccd6..93a52d133ba1 100644
>> --- a/include/linux/soc/samsung/exynos-regs-pmu.h
>> +++ b/include/linux/soc/samsung/exynos-regs-pmu.h
>> @@ -645,7 +645,110 @@
>>                                          | EXYNOS5420_KFC_USE_STANDBY_WFI3)
>>
>>  /* For EXYNOS5433 */
>> +#define EXYNOS5433_UP_SCHEDULER                                        (0x0120)
>> +#define EXYNOS5433_CENTRAL_SEQ_CONFIGURATION                   (0x0200)
>> +#define EXYNOS5433_CENTRAL_SEQ_MIF_CONFIGURATION               (0x0240)
>> +#define EXYNOS5433_EINT_WAKEUP_MASK                            (0x060C)
>> +#define EXYNOS5433_WAKEUP_MASK                                 (0x0610)
>> +#define EXYNOS5433_WAKEUP_MASK2                                        (0x0614)
>> +#define EXYNOS5433_WAKEUP_MASK3                                        (0x0618)
>> +#define EXYNOS5433_EINT_WAKEUP_MASK1                           (0x062C)
>>  #define EXYNOS5433_USBHOST30_PHY_CONTROL                       (0x0728)
>> +#define EXYNOS5433_PMU_SPARE0                                  (0x0900)
>> +#define EXYNOS5433_ATLAS_CPU0_SYS_PWR_REG                      (0x1000)
>> +#define EXYNOS5433_DIS_IRQ_ATLAS_CPU0_CENTRAL_SYS_PWR_REG      (0x1008)
>> +#define EXYNOS5433_ATLAS_CPU1_SYS_PWR_REG                      (0x1010)
>> +#define EXYNOS5433_DIS_IRQ_ATLAS_CPU1_CENTRAL_SYS_PWR_REG      (0x1018)
>> +#define EXYNOS5433_ATLAS_CPU2_SYS_PWR_REG                      (0x1020)
>> +#define EXYNOS5433_DIS_IRQ_ATLAS_CPU2_CENTRAL_SYS_PWR_REG      (0x1028)
>> +#define EXYNOS5433_ATLAS_CPU3_SYS_PWR_REG                      (0x1030)
>> +#define EXYNOS5433_DIS_IRQ_ATLAS_CPU3_CENTRAL_SYS_PWR_REG      (0x1038)
>> +#define EXYNOS5433_APOLLO_CPU0_SYS_PWR_REG                     (0x1040)
>> +#define EXYNOS5433_DIS_IRQ_APOLLO_CPU0_CENTRAL_SYS_PWR_REG     (0x1048)
>> +#define EXYNOS5433_APOLLO_CPU1_SYS_PWR_REG                     (0x1050)
>> +#define EXYNOS5433_DIS_IRQ_APOLLO_CPU1_CENTRAL_SYS_PWR_REG     (0x1058)
>> +#define EXYNOS5433_APOLLO_CPU2_SYS_PWR_REG                     (0x1060)
>> +#define EXYNOS5433_DIS_IRQ_APOLLO_CPU2_CENTRAL_SYS_PWR_REG     (0x1068)
>> +#define EXYNOS5433_APOLLO_CPU3_SYS_PWR_REG                     (0x1070)
>> +#define EXYNOS5433_DIS_IRQ_APOLLO_CPU3_CENTRAL_SYS_PWR_REG     (0x1078)
>> +#define EXYNOS5433_ATLAS_NONCPU_SYS_PWR_REG                    (0x1080)
>> +#define EXYNOS5433_ATLAS_L2_SYS_PWR_REG                                (0x10C0)
>> +#define EXYNOS5433_APOLLO_L2_SYS_PWR_REG                       (0x10C4)
>> +#define EXYNOS5433_APOLLO_NONCPU_SYS_PWR_REG                   (0x1084)
>> +#define EXYNOS5433_A5IS_SYS_PWR_REG                            (0x10B0)
>> +#define EXYNOS5433_DIS_IRQ_A5IS_LOCAL_SYS_PWR_REG              (0x10B4)
>> +#define EXYNOS5433_DIS_IRQ_A5IS_CENTRAL_SYS_PWR_REG            (0x10B8)
>> +#define EXYNOS5433_CLKSTOP_CMU_TOP_SYS_PWR_REG                 (0x1100)
>> +#define EXYNOS5433_CLKRUN_CMU_TOP_SYS_PWR_REG                  (0x1104)
>> +#define EXYNOS5433_RESET_CMU_TOP_SYS_PWR_REG                   (0x110C)
>> +#define EXYNOS5433_RESET_CPUCLKSTOP_SYS_PWR_REG                        (0x111C)
>> +#define EXYNOS5433_CLKSTOP_CMU_MIF_SYS_PWR_REG                 (0x1120)
>> +#define EXYNOS5433_CLKRUN_CMU_MIF_SYS_PWR_REG                  (0x1124)
>> +#define EXYNOS5433_RESET_CMU_MIF_SYS_PWR_REG                   (0x112C)
>> +#define EXYNOS5433_DDRPHY_DLLLOCK_SYS_PWR_REG                  (0x1138)
>> +#define EXYNOS5433_DISABLE_PLL_CMU_TOP_SYS_PWR_REG             (0x1140)
>> +#define EXYNOS5433_DISABLE_PLL_AUD_PLL_SYS_PWR_REG             (0x1144)
>> +#define EXYNOS5433_DISABLE_PLL_CMU_MIF_SYS_PWR_REG             (0x1160)
>> +#define EXYNOS5433_TOP_BUS_SYS_PWR_REG                         (0x1180)
>> +#define EXYNOS5433_TOP_RETENTION_SYS_PWR_REG                   (0x1184)
>> +#define EXYNOS5433_TOP_PWR_SYS_PWR_REG                         (0x1188)
>> +#define EXYNOS5433_TOP_BUS_MIF_SYS_PWR_REG                     (0x1190)
>> +#define EXYNOS5433_TOP_RETENTION_MIF_SYS_PWR_REG               (0x1194)
>> +#define EXYNOS5433_TOP_PWR_MIF_SYS_PWR_REG                     (0x1198)
>> +#define EXYNOS5433_LOGIC_RESET_SYS_PWR_REG                     (0x11A0)
>> +#define EXYNOS5433_OSCCLK_GATE_SYS_PWR_REG                     (0x11A4)
>> +#define EXYNOS5433_SLEEP_RESET_SYS_PWR_REG                     (0x11A8)
>> +#define EXYNOS5433_LOGIC_RESET_MIF_SYS_PWR_REG                 (0x11B0)
>> +#define EXYNOS5433_OSCCLK_GATE_MIF_SYS_PWR_REG                 (0x11B4)
>> +#define EXYNOS5433_SLEEP_RESET_MIF_SYS_PWR_REG                 (0x11B8)
>> +#define EXYNOS5433_MEMORY_TOP_SYS_PWR_REG                      (0x11C0)
>> +#define EXYNOS5433_PAD_RETENTION_LPDDR3_SYS_PWR_REG            (0x1200)
>> +#define EXYNOS5433_PAD_RETENTION_JTAG_SYS_PWR_REG              (0x1208)
>> +#define EXYNOS5433_PAD_RETENTION_TOP_SYS_PWR_REG               (0x1220)
>> +#define EXYNOS5433_PAD_RETENTION_UART_SYS_PWR_REG              (0x1224)
>> +#define EXYNOS5433_PAD_RETENTION_EBIA_SYS_PWR_REG              (0x1230)
>> +#define EXYNOS5433_PAD_RETENTION_EBIB_SYS_PWR_REG              (0x1234)
>> +#define EXYNOS5433_PAD_RETENTION_SPI_SYS_PWR_REG               (0x1238)
>> +#define EXYNOS5433_PAD_RETENTION_MIF_SYS_PWR_REG               (0x123C)
>> +#define EXYNOS5433_PAD_ISOLATION_SYS_PWR_REG                   (0x1240)
>> +#define EXYNOS5433_PAD_RETENTION_USBXTI_SYS_PWR_REG            (0x1244)
>> +#define EXYNOS5433_PAD_RETENTION_BOOTLDO_SYS_PWR_REG           (0x1248)
>> +#define EXYNOS5433_PAD_ISOLATION_MIF_SYS_PWR_REG               (0x1250)
>> +#define EXYNOS5433_PAD_RETENTION_FSYSGENIO_SYS_PWR_REG         (0x1254)
>> +#define EXYNOS5433_PAD_ALV_SEL_SYS_PWR_REG                     (0x1260)
>> +#define EXYNOS5433_XXTI_SYS_PWR_REG                            (0x1284)
>> +#define EXYNOS5433_XXTI26_SYS_PWR_REG                          (0x1288)
>> +#define EXYNOS5433_EXT_REGULATOR_SYS_PWR_REG                   (0x12C0)
>> +#define EXYNOS5433_GPIO_MODE_SYS_PWR_REG                       (0x1300)
>> +#define EXYNOS5433_GPIO_MODE_FSYS0_SYS_PWR_REG                 (0x1304)
>> +#define EXYNOS5433_GPIO_MODE_MIF_SYS_PWR_REG                   (0x1320)
>> +#define EXYNOS5433_GPIO_MODE_AUD_SYS_PWR_REG                   (0x1340)
>> +#define EXYNOS5433_GSCL_SYS_PWR_REG                            (0x1400)
>> +#define EXYNOS5433_CAM0_SYS_PWR_REG                            (0x1404)
>> +#define EXYNOS5433_MSCL_SYS_PWR_REG                            (0x1408)
>> +#define EXYNOS5433_G3D_SYS_PWR_REG                             (0x140C)
>> +#define EXYNOS5433_DISP_SYS_PWR_REG                            (0x1410)
>> +#define EXYNOS5433_CAM1_SYS_PWR_REG                            (0x1414)
>> +#define EXYNOS5433_AUD_SYS_PWR_REG                             (0x1418)
>> +#define EXYNOS5433_FSYS_SYS_PWR_REG                            (0x141C)
>> +#define EXYNOS5433_BUS2_SYS_PWR_REG                            (0x1420)
>> +#define EXYNOS5433_G2D_SYS_PWR_REG                             (0x1424)
>> +#define EXYNOS5433_ISP0_SYS_PWR_REG                            (0x1428)
>> +#define EXYNOS5433_MFC_SYS_PWR_REG                             (0x1430)
>> +#define EXYNOS5433_HEVC_SYS_PWR_REG                            (0x1438)
>> +#define EXYNOS5433_RESET_SLEEP_FSYS_SYS_PWR_REG                        (0x15DC)
>> +#define EXYNOS5433_RESET_SLEEP_BUS2_SYS_PWR_REG                        (0x15E0)
>> +#define EXYNOS5433_ATLAS_CPU0_OPTION                           (0x2008)
>> +#define EXYNOS5433_CPU_OPTION(_nr)                             (EXYNOS5433_ATLAS_CPU0_OPTION + (_nr) * 0x80)
>> +#define EXYNOS5433_ATLAS_CPU0_DURATION0                                (0x2010)
>> +#define EXYNOS5433_CPU_DURATION(_nr)                           (EXYNOS5433_ATLAS_CPU0_DURATION0 + (_nr) * 0x80)
>> +#define EXYNOS5433_ATLAS_NONCPU_OPTION                         (0x2408)
>> +#define EXYNOS5433_APOLLO_NONCPU_OPTION                                (0x2428)
>> +#define EXYNOS5433_ATLAS_CPUSEQUENCER_OPTION                   (0x2488)
>> +#define EXYNOS5433_ATLAS_L2_OPTION                             (0x2608)
>> +#define EXYNOS5433_TOP_PWR_MIF_OPTION                          (0x2CC8)
>> +#define EXYNOS5433_TOP_PWR_OPTION                              (0x2C48)
>> +#define EXYNOS5433_PAD_RETENTION_LPDDR3_OPTION                 (0x3008)
>>  #define EXYNOS5433_PAD_RETENTION_AUD_OPTION                    (0x3028)
>>  #define EXYNOS5433_PAD_RETENTION_MMC2_OPTION                   (0x30C8)
>>  #define EXYNOS5433_PAD_RETENTION_TOP_OPTION                    (0x3108)
>> @@ -660,5 +763,50 @@
>>  #define EXYNOS5433_PAD_RETENTION_BOOTLDO_OPTION                        (0x3248)
>>  #define EXYNOS5433_PAD_RETENTION_UFS_OPTION                    (0x3268)
>>  #define EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION              (0x32A8)
>> +#define EXYNOS5433_PS_HOLD_CONTROL                             (0x330C)
>> +#define EXYNOS5433_GSCL_OPTION                                 (0x4008)
>> +#define EXYNOS5433_CAM0_OPTION                                 (0x4028)
>> +#define EXYNOS5433_MSCL_OPTION                                 (0x4048)
>> +#define EXYNOS5433_G3D_OPTION                                  (0x4068)
>> +#define EXYNOS5433_DISP_OPTION                                 (0x4088)
>> +#define EXYNOS5433_AUD_OPTION                                  (0x40C8)
>> +#define EXYNOS5433_FSYS_OPTION                                 (0x40E8)
>> +#define EXYNOS5433_BUS2_OPTION                                 (0x4108)
>> +#define EXYNOS5433_G2D_OPTION                                  (0x4128)
>> +#define EXYNOS5433_ISP_OPTION                                  (0x4148)
>> +#define EXYNOS5433_MFC_OPTION                                  (0x4188)
>> +#define EXYNOS5433_HEVC_OPTION                                 (0x41C8)
>> +
>> +/* EXYNOS5433_PMU_SPARE0 */
>> +#define EXYNOS5433_EN_NONRET_RESET                             (1 << 0)
> 
> Use BIT(0) here and in other places.

OK.

[snip]

Thanks for the review.

-- 
Best Regards,
Chanwoo Choi
Samsung Electronics
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Re: [PATCH 3/9] soc: samsung: pmu: Add the PMU data of exynos5433 to support low-power state

[Krzysztof Kozlowski]

On Tue, Jan 9, 2018 at 8:59 AM, Chanwoo Choi <cw00.choi@samsung.com> wrote:
> This patch adds the PMU (Power Management Unit) data of exynos5433 SoC
> in order to support the various power modes. Each power mode has
> the different value for reducing the power-consumption.
>
> Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> ---
>  arch/arm/mach-exynos/common.h               |   2 -
>  drivers/soc/samsung/Makefile                |   3 +-
>  drivers/soc/samsung/exynos-pmu.c            |   1 +
>  drivers/soc/samsung/exynos-pmu.h            |   2 +
>  drivers/soc/samsung/exynos5433-pmu.c        | 286 ++++++++++++++++++++++++++++
>  include/linux/soc/samsung/exynos-regs-pmu.h | 148 ++++++++++++++
>  6 files changed, 439 insertions(+), 3 deletions(-)
>  create mode 100644 drivers/soc/samsung/exynos5433-pmu.c
>
> diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
> index 098f84a149a3..afbc143a3d5d 100644
> --- a/arch/arm/mach-exynos/common.h
> +++ b/arch/arm/mach-exynos/common.h
> @@ -125,8 +125,6 @@ enum {
>  void exynos_set_boot_flag(unsigned int cpu, unsigned int mode);
>  void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode);
>
> -extern u32 exynos_get_eint_wake_mask(void);
> -
>  #ifdef CONFIG_PM_SLEEP
>  extern void __init exynos_pm_init(void);
>  #else
> diff --git a/drivers/soc/samsung/Makefile b/drivers/soc/samsung/Makefile
> index 29f294baac6e..d2e637339a45 100644
> --- a/drivers/soc/samsung/Makefile
> +++ b/drivers/soc/samsung/Makefile
> @@ -2,5 +2,6 @@
>  obj-$(CONFIG_EXYNOS_PMU)       += exynos-pmu.o
>
>  obj-$(CONFIG_EXYNOS_PMU_ARM_DRIVERS)   += exynos3250-pmu.o exynos4-pmu.o \
> -                                       exynos5250-pmu.o exynos5420-pmu.o
> +                                       exynos5250-pmu.o exynos5420-pmu.o \
> +                                       exynos5433-pmu.o

... ah, I forgot. No. Exynos5433 is not ARMv7.

 Best regards,
Krzysztof

Re: [PATCH 3/9] soc: samsung: pmu: Add the PMU data of exynos5433 to support low-power state

[Sudeep Holla]

On 09/01/18 07:59, Chanwoo Choi wrote:
> This patch adds the PMU (Power Management Unit) data of exynos5433 SoC
> in order to support the various power modes. Each power mode has
> the different value for reducing the power-consumption.
> 
> Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> ---
>  arch/arm/mach-exynos/common.h               |   2 -
>  drivers/soc/samsung/Makefile                |   3 +-
>  drivers/soc/samsung/exynos-pmu.c            |   1 +
>  drivers/soc/samsung/exynos-pmu.h            |   2 +
>  drivers/soc/samsung/exynos5433-pmu.c        | 286 ++++++++++++++++++++++++++++
>  include/linux/soc/samsung/exynos-regs-pmu.h | 148 ++++++++++++++
>  6 files changed, 439 insertions(+), 3 deletions(-)
>  create mode 100644 drivers/soc/samsung/exynos5433-pmu.c
> 

> diff --git a/drivers/soc/samsung/exynos5433-pmu.c b/drivers/soc/samsung/exynos5433-pmu.c
> new file mode 100644
> index 000000000000..2571e61522f0
> --- /dev/null
> +++ b/drivers/soc/samsung/exynos5433-pmu.c
> @@ -0,0 +1,286 @@
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright (c) 2018 Samsung Electronics Co., Ltd.
> +// Copyright (c) Jonghwa Lee <jonghwa3.lee@samsung.com>
> +// Copyright (c) Chanwoo Choi <cw00.choi@samsung.com>
> +//
> +// EXYNOS5433 - CPU PMU (Power Management Unit) support
> +
> +#include <linux/soc/samsung/exynos-regs-pmu.h>
> +#include <linux/soc/samsung/exynos-pmu.h>
> +
> +#include "exynos-pmu.h"
> +
> +static struct exynos_pmu_conf exynos5433_pmu_config[] = {
> +	/* { .offset = address,	.val = { AFTR, LPA, SLEEP } } */
> +	{ EXYNOS5433_ATLAS_CPU0_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
> +	{ EXYNOS5433_DIS_IRQ_ATLAS_CPU0_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0 } },
> +	{ EXYNOS5433_ATLAS_CPU1_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
> +	{ EXYNOS5433_DIS_IRQ_ATLAS_CPU1_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0 } },
> +	{ EXYNOS5433_ATLAS_CPU2_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
> +	{ EXYNOS5433_DIS_IRQ_ATLAS_CPU2_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0 } },
> +	{ EXYNOS5433_ATLAS_CPU3_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
> +	{ EXYNOS5433_DIS_IRQ_ATLAS_CPU3_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0 } },
> +	{ EXYNOS5433_APOLLO_CPU0_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
> +	{ EXYNOS5433_DIS_IRQ_APOLLO_CPU0_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0 } },
> +	{ EXYNOS5433_APOLLO_CPU1_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
> +	{ EXYNOS5433_DIS_IRQ_APOLLO_CPU1_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0 } },
> +	{ EXYNOS5433_APOLLO_CPU2_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
> +	{ EXYNOS5433_DIS_IRQ_APOLLO_CPU2_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0 } },
> +	{ EXYNOS5433_APOLLO_CPU3_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
> +	{ EXYNOS5433_DIS_IRQ_APOLLO_CPU3_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0 } },
> +	{ EXYNOS5433_ATLAS_NONCPU_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
> +	{ EXYNOS5433_APOLLO_NONCPU_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },


1. First of all why do you need any of these CPU related PMU config
   registers in kernel ? From the information I gathered this is ARM64
   SoC using PSCI. These are needed just in PSCI implementation and not
   in kernel. So can you elaborate on why there are present here ?

2. Are there any public documents that these names map to ?
   If there is none, please replace these codenames(ATLAS, APOLLO) with
   appropriately.

Sorry if these are already answered, just point me to those threads.

-- 
Regards,
Sudeep

Re: [PATCH 3/9] soc: samsung: pmu: Add the PMU data of exynos5433 to support low-power state

[Chanwoo Choi]

On 2018년 01월 09일 23:11, Sudeep Holla wrote:
> 
> 
> On 09/01/18 07:59, Chanwoo Choi wrote:
>> This patch adds the PMU (Power Management Unit) data of exynos5433 SoC
>> in order to support the various power modes. Each power mode has
>> the different value for reducing the power-consumption.
>>
>> Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>> ---
>>  arch/arm/mach-exynos/common.h               |   2 -
>>  drivers/soc/samsung/Makefile                |   3 +-
>>  drivers/soc/samsung/exynos-pmu.c            |   1 +
>>  drivers/soc/samsung/exynos-pmu.h            |   2 +
>>  drivers/soc/samsung/exynos5433-pmu.c        | 286 ++++++++++++++++++++++++++++
>>  include/linux/soc/samsung/exynos-regs-pmu.h | 148 ++++++++++++++
>>  6 files changed, 439 insertions(+), 3 deletions(-)
>>  create mode 100644 drivers/soc/samsung/exynos5433-pmu.c
>>
> 
>> diff --git a/drivers/soc/samsung/exynos5433-pmu.c b/drivers/soc/samsung/exynos5433-pmu.c
>> new file mode 100644
>> index 000000000000..2571e61522f0
>> --- /dev/null
>> +++ b/drivers/soc/samsung/exynos5433-pmu.c
>> @@ -0,0 +1,286 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +//
>> +// Copyright (c) 2018 Samsung Electronics Co., Ltd.
>> +// Copyright (c) Jonghwa Lee <jonghwa3.lee@samsung.com>
>> +// Copyright (c) Chanwoo Choi <cw00.choi@samsung.com>
>> +//
>> +// EXYNOS5433 - CPU PMU (Power Management Unit) support
>> +
>> +#include <linux/soc/samsung/exynos-regs-pmu.h>
>> +#include <linux/soc/samsung/exynos-pmu.h>
>> +
>> +#include "exynos-pmu.h"
>> +
>> +static struct exynos_pmu_conf exynos5433_pmu_config[] = {
>> +	/* { .offset = address,	.val = { AFTR, LPA, SLEEP } } */
>> +	{ EXYNOS5433_ATLAS_CPU0_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
>> +	{ EXYNOS5433_DIS_IRQ_ATLAS_CPU0_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0 } },
>> +	{ EXYNOS5433_ATLAS_CPU1_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
>> +	{ EXYNOS5433_DIS_IRQ_ATLAS_CPU1_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0 } },
>> +	{ EXYNOS5433_ATLAS_CPU2_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
>> +	{ EXYNOS5433_DIS_IRQ_ATLAS_CPU2_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0 } },
>> +	{ EXYNOS5433_ATLAS_CPU3_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
>> +	{ EXYNOS5433_DIS_IRQ_ATLAS_CPU3_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0 } },
>> +	{ EXYNOS5433_APOLLO_CPU0_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
>> +	{ EXYNOS5433_DIS_IRQ_APOLLO_CPU0_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0 } },
>> +	{ EXYNOS5433_APOLLO_CPU1_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
>> +	{ EXYNOS5433_DIS_IRQ_APOLLO_CPU1_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0 } },
>> +	{ EXYNOS5433_APOLLO_CPU2_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
>> +	{ EXYNOS5433_DIS_IRQ_APOLLO_CPU2_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0 } },
>> +	{ EXYNOS5433_APOLLO_CPU3_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
>> +	{ EXYNOS5433_DIS_IRQ_APOLLO_CPU3_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0 } },
>> +	{ EXYNOS5433_ATLAS_NONCPU_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
>> +	{ EXYNOS5433_APOLLO_NONCPU_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
> 
> 
> 1. First of all why do you need any of these CPU related PMU config
>    registers in kernel ? From the information I gathered this is ARM64
>    SoC using PSCI. These are needed just in PSCI implementation and not
>    in kernel. So can you elaborate on why there are present here ?

The 32bit Exynos used the 'smc' call to enter the suspend mode
and need to handle the PMU registers.

Even if PSCI replaces the 'smc' call on the Exynos5433,
the Exynos5433's document requires the handling of PMU config
related to CPU for the suspend mode.

IMHO, If the secure OS implemented the all something related to CPU,
it might be unnecessary to handle the PMU registers. I think that
it depend on how to design the SoC by H/W Architect. This is just my opinion.

> 
> 2. Are there any public documents that these names map to ?

There is no public document. It is confidential.

>    If there is none, please replace these codenames(ATLAS, APOLLO) with
>    appropriately.

In the Exynos5433, 'apollo' indicates the LITTLE cores (cpu0-3, cortex-a53)
and 'atlas' indicates the big cores (cpu4-7, cortex-a57)

Exynos5433 already used the 'apollo' and 'atlas' on clk-exynos5433.c driver
and thermal device-tree node. It is better to use the original register name
in the document in order to reduce the confusion of the change of register name
even if document is not public.

Also, exynos7 used the 'atlas' word for big cores.

> 
> Sorry if these are already answered, just point me to those threads.
> 


-- 
Best Regards,
Chanwoo Choi
Samsung Electronics

Re: [PATCH 3/9] soc: samsung: pmu: Add the PMU data of exynos5433 to support low-power state

[Sudeep Holla]

On 10/01/18 01:46, Chanwoo Choi wrote:
> On 2018년 01월 09일 23:11, Sudeep Holla wrote:
>>
>>
>> On 09/01/18 07:59, Chanwoo Choi wrote:
>>> This patch adds the PMU (Power Management Unit) data of exynos5433 SoC
>>> in order to support the various power modes. Each power mode has
>>> the different value for reducing the power-consumption.
>>>
>>> Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>> ---
>>>  arch/arm/mach-exynos/common.h               |   2 -
>>>  drivers/soc/samsung/Makefile                |   3 +-
>>>  drivers/soc/samsung/exynos-pmu.c            |   1 +
>>>  drivers/soc/samsung/exynos-pmu.h            |   2 +
>>>  drivers/soc/samsung/exynos5433-pmu.c        | 286 ++++++++++++++++++++++++++++
>>>  include/linux/soc/samsung/exynos-regs-pmu.h | 148 ++++++++++++++
>>>  6 files changed, 439 insertions(+), 3 deletions(-)
>>>  create mode 100644 drivers/soc/samsung/exynos5433-pmu.c
>>>
>>
>>> diff --git a/drivers/soc/samsung/exynos5433-pmu.c b/drivers/soc/samsung/exynos5433-pmu.c
>>> new file mode 100644
>>> index 000000000000..2571e61522f0
>>> --- /dev/null
>>> +++ b/drivers/soc/samsung/exynos5433-pmu.c
>>> @@ -0,0 +1,286 @@
>>> +// SPDX-License-Identifier: GPL-2.0
>>> +//
>>> +// Copyright (c) 2018 Samsung Electronics Co., Ltd.
>>> +// Copyright (c) Jonghwa Lee <jonghwa3.lee@samsung.com>
>>> +// Copyright (c) Chanwoo Choi <cw00.choi@samsung.com>
>>> +//
>>> +// EXYNOS5433 - CPU PMU (Power Management Unit) support
>>> +
>>> +#include <linux/soc/samsung/exynos-regs-pmu.h>
>>> +#include <linux/soc/samsung/exynos-pmu.h>
>>> +
>>> +#include "exynos-pmu.h"
>>> +
>>> +static struct exynos_pmu_conf exynos5433_pmu_config[] = {
>>> +	/* { .offset = address,	.val = { AFTR, LPA, SLEEP } } */
>>> +	{ EXYNOS5433_ATLAS_CPU0_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
>>> +	{ EXYNOS5433_DIS_IRQ_ATLAS_CPU0_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0 } },
>>> +	{ EXYNOS5433_ATLAS_CPU1_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
>>> +	{ EXYNOS5433_DIS_IRQ_ATLAS_CPU1_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0 } },
>>> +	{ EXYNOS5433_ATLAS_CPU2_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
>>> +	{ EXYNOS5433_DIS_IRQ_ATLAS_CPU2_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0 } },
>>> +	{ EXYNOS5433_ATLAS_CPU3_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
>>> +	{ EXYNOS5433_DIS_IRQ_ATLAS_CPU3_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0 } },
>>> +	{ EXYNOS5433_APOLLO_CPU0_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
>>> +	{ EXYNOS5433_DIS_IRQ_APOLLO_CPU0_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0 } },
>>> +	{ EXYNOS5433_APOLLO_CPU1_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
>>> +	{ EXYNOS5433_DIS_IRQ_APOLLO_CPU1_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0 } },
>>> +	{ EXYNOS5433_APOLLO_CPU2_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
>>> +	{ EXYNOS5433_DIS_IRQ_APOLLO_CPU2_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0 } },
>>> +	{ EXYNOS5433_APOLLO_CPU3_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
>>> +	{ EXYNOS5433_DIS_IRQ_APOLLO_CPU3_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0 } },
>>> +	{ EXYNOS5433_ATLAS_NONCPU_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
>>> +	{ EXYNOS5433_APOLLO_NONCPU_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
>>
>>
>> 1. First of all why do you need any of these CPU related PMU config
>>    registers in kernel ? From the information I gathered this is ARM64
>>    SoC using PSCI. These are needed just in PSCI implementation and not
>>    in kernel. So can you elaborate on why there are present here ?
> 
> The 32bit Exynos used the 'smc' call to enter the suspend mode
> and need to handle the PMU registers.
> 

OK

> Even if PSCI replaces the 'smc' call on the Exynos5433,
> the Exynos5433's document requires the handling of PMU config
> related to CPU for the suspend mode.
>

OK but does it state it needs to be in kernel ?(i.e. in EL1 NS)

> IMHO, If the secure OS implemented the all something related to CPU,
> it might be unnecessary to handle the PMU registers. I think that
> it depend on how to design the SoC by H/W Architect. This is just my opinion.
> 

Even if it can be accessed in kernel, better to keep all these in PSCI
implementation that does the actual power state management. Mixing them
in both kernel and PSCI implementation is just a mess TBH and not easy
to maintain the platform if some issues pop up.

>>
>> 2. Are there any public documents that these names map to ?
> 
> There is no public document. It is confidential.
> 

I guessed so and hence raised to remove it.

>>    If there is none, please replace these codenames(ATLAS, APOLLO) with
>>    appropriately.
> 
> In the Exynos5433, 'apollo' indicates the LITTLE cores (cpu0-3, cortex-a53)
> and 'atlas' indicates the big cores (cpu4-7, cortex-a57)
> 
> Exynos5433 already used the 'apollo' and 'atlas' on clk-exynos5433.c driver
> and thermal device-tree node. It is better to use the original register name
> in the document in order to reduce the confusion of the change of register name
> even if document is not public.
> 
> Also, exynos7 used the 'atlas' word for big cores.
> 

I disagree. If you don't have any public documents, then better use
names other developers are used to and not some code names which
otherwise is not seen in any other part of the code base. Grepping
just shows Exynos using these code names which are generally restricted
for internal use.

-- 
Regards,
Sudeep

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 3/9] soc: samsung: pmu: Add the PMU data of exynos5433 to support low-power state

[Chanwoo Choi]

On 2018년 01월 10일 19:53, Sudeep Holla wrote:
> 
> 
> On 10/01/18 01:46, Chanwoo Choi wrote:
>> On 2018년 01월 09일 23:11, Sudeep Holla wrote:
>>>
>>>
>>> On 09/01/18 07:59, Chanwoo Choi wrote:
>>>> This patch adds the PMU (Power Management Unit) data of exynos5433 SoC
>>>> in order to support the various power modes. Each power mode has
>>>> the different value for reducing the power-consumption.
>>>>
>>>> Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
>>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>>> ---
>>>>  arch/arm/mach-exynos/common.h               |   2 -
>>>>  drivers/soc/samsung/Makefile                |   3 +-
>>>>  drivers/soc/samsung/exynos-pmu.c            |   1 +
>>>>  drivers/soc/samsung/exynos-pmu.h            |   2 +
>>>>  drivers/soc/samsung/exynos5433-pmu.c        | 286 ++++++++++++++++++++++++++++
>>>>  include/linux/soc/samsung/exynos-regs-pmu.h | 148 ++++++++++++++
>>>>  6 files changed, 439 insertions(+), 3 deletions(-)
>>>>  create mode 100644 drivers/soc/samsung/exynos5433-pmu.c
>>>>
>>>
>>>> diff --git a/drivers/soc/samsung/exynos5433-pmu.c b/drivers/soc/samsung/exynos5433-pmu.c
>>>> new file mode 100644
>>>> index 000000000000..2571e61522f0
>>>> --- /dev/null
>>>> +++ b/drivers/soc/samsung/exynos5433-pmu.c
>>>> @@ -0,0 +1,286 @@
>>>> +// SPDX-License-Identifier: GPL-2.0
>>>> +//
>>>> +// Copyright (c) 2018 Samsung Electronics Co., Ltd.
>>>> +// Copyright (c) Jonghwa Lee <jonghwa3.lee@samsung.com>
>>>> +// Copyright (c) Chanwoo Choi <cw00.choi@samsung.com>
>>>> +//
>>>> +// EXYNOS5433 - CPU PMU (Power Management Unit) support
>>>> +
>>>> +#include <linux/soc/samsung/exynos-regs-pmu.h>
>>>> +#include <linux/soc/samsung/exynos-pmu.h>
>>>> +
>>>> +#include "exynos-pmu.h"
>>>> +
>>>> +static struct exynos_pmu_conf exynos5433_pmu_config[] = {
>>>> +	/* { .offset = address,	.val = { AFTR, LPA, SLEEP } } */
>>>> +	{ EXYNOS5433_ATLAS_CPU0_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
>>>> +	{ EXYNOS5433_DIS_IRQ_ATLAS_CPU0_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0 } },
>>>> +	{ EXYNOS5433_ATLAS_CPU1_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
>>>> +	{ EXYNOS5433_DIS_IRQ_ATLAS_CPU1_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0 } },
>>>> +	{ EXYNOS5433_ATLAS_CPU2_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
>>>> +	{ EXYNOS5433_DIS_IRQ_ATLAS_CPU2_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0 } },
>>>> +	{ EXYNOS5433_ATLAS_CPU3_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
>>>> +	{ EXYNOS5433_DIS_IRQ_ATLAS_CPU3_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0 } },
>>>> +	{ EXYNOS5433_APOLLO_CPU0_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
>>>> +	{ EXYNOS5433_DIS_IRQ_APOLLO_CPU0_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0 } },
>>>> +	{ EXYNOS5433_APOLLO_CPU1_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
>>>> +	{ EXYNOS5433_DIS_IRQ_APOLLO_CPU1_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0 } },
>>>> +	{ EXYNOS5433_APOLLO_CPU2_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
>>>> +	{ EXYNOS5433_DIS_IRQ_APOLLO_CPU2_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0 } },
>>>> +	{ EXYNOS5433_APOLLO_CPU3_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
>>>> +	{ EXYNOS5433_DIS_IRQ_APOLLO_CPU3_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0 } },
>>>> +	{ EXYNOS5433_ATLAS_NONCPU_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
>>>> +	{ EXYNOS5433_APOLLO_NONCPU_SYS_PWR_REG,			{ 0x0, 0x0, 0x8 } },
>>>
>>>
>>> 1. First of all why do you need any of these CPU related PMU config
>>>    registers in kernel ? From the information I gathered this is ARM64
>>>    SoC using PSCI. These are needed just in PSCI implementation and not
>>>    in kernel. So can you elaborate on why there are present here ?
>>
>> The 32bit Exynos used the 'smc' call to enter the suspend mode
>> and need to handle the PMU registers.
>>
> 
> OK
> 
>> Even if PSCI replaces the 'smc' call on the Exynos5433,
>> the Exynos5433's document requires the handling of PMU config
>> related to CPU for the suspend mode.
>>
> 
> OK but does it state it needs to be in kernel ?(i.e. in EL1 NS)
> 
>> IMHO, If the secure OS implemented the all something related to CPU,
>> it might be unnecessary to handle the PMU registers. I think that
>> it depend on how to design the SoC by H/W Architect. This is just my opinion.
>>
> 
> Even if it can be accessed in kernel, better to keep all these in PSCI
> implementation that does the actual power state management. Mixing them
> in both kernel and PSCI implementation is just a mess TBH and not easy
> to maintain the platform if some issues pop up.
> 
>>>
>>> 2. Are there any public documents that these names map to ?
>>
>> There is no public document. It is confidential.
>>
> 
> I guessed so and hence raised to remove it.
> 
>>>    If there is none, please replace these codenames(ATLAS, APOLLO) with
>>>    appropriately.
>>
>> In the Exynos5433, 'apollo' indicates the LITTLE cores (cpu0-3, cortex-a53)
>> and 'atlas' indicates the big cores (cpu4-7, cortex-a57)
>>
>> Exynos5433 already used the 'apollo' and 'atlas' on clk-exynos5433.c driver
>> and thermal device-tree node. It is better to use the original register name
>> in the document in order to reduce the confusion of the change of register name
>> even if document is not public.
>>
>> Also, exynos7 used the 'atlas' word for big cores.
>>
> 
> I disagree. If you don't have any public documents, then better use
> names other developers are used to and not some code names which
> otherwise is not seen in any other part of the code base. Grepping
> just shows Exynos using these code names which are generally restricted

I mentioned, these words were already used on other device drivers.
Exynos5433 used them to indicate the big.LITTLE cores consistently.
They are an alias for big.LITTLE. Latest Exynos SoC must use these words continuously.
I think that each vendor SoC could define the alias or expression for their SoC.

-- 
Best Regards,
Chanwoo Choi
Samsung Electronics

[RFC PATCH 4/9] soc: samsung: Add generic power-management driver for Exynos

[Chanwoo Choi]

To enter suspend, Exynos SoC requires the some machine dependent procedures.
This patch introduces the generic power-management driver to support
those requirements and generic interface for power state management.

Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
 arch/arm/mach-exynos/common.h         |   1 -
 arch/arm/mach-exynos/exynos.c         |  23 +----
 drivers/soc/samsung/Makefile          |   2 +-
 drivers/soc/samsung/exynos-pm.c       | 176 ++++++++++++++++++++++++++++++++++
 include/linux/soc/samsung/exynos-pm.h |  21 ++++
 5 files changed, 199 insertions(+), 24 deletions(-)
 create mode 100644 drivers/soc/samsung/exynos-pm.c
 create mode 100644 include/linux/soc/samsung/exynos-pm.h

diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index afbc143a3d5d..ad482c0fc131 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -119,7 +119,6 @@ enum {
  * Magic values for bootloader indicating chosen low power mode.
  * See also Documentation/arm/Samsung/Bootloader-interface.txt
  */
-#define EXYNOS_SLEEP_MAGIC	0x00000bad
 #define EXYNOS_AFTR_MAGIC	0xfcba0d10

 void exynos_set_boot_flag(unsigned int cpu, unsigned int mode);
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index fbd108ce8745..0d5265d175c4 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -12,6 +12,7 @@
 #include <linux/of_fdt.h>
 #include <linux/platform_device.h>
 #include <linux/irqchip.h>
+#include <linux/soc/samsung/exynos-pm.h>
 #include <linux/soc/samsung/exynos-regs-pmu.h>

 #include <asm/cacheflush.h>
@@ -41,28 +42,6 @@
 	.id                = -1,
 };

-void __iomem *sysram_base_addr __ro_after_init;
-void __iomem *sysram_ns_base_addr __ro_after_init;
-
-void __init exynos_sysram_init(void)
-{
-	struct device_node *node;
-
-	for_each_compatible_node(node, NULL, "samsung,exynos4210-sysram") {
-		if (!of_device_is_available(node))
-			continue;
-		sysram_base_addr = of_iomap(node, 0);
-		break;
-	}
-
-	for_each_compatible_node(node, NULL, "samsung,exynos4210-sysram-ns") {
-		if (!of_device_is_available(node))
-			continue;
-		sysram_ns_base_addr = of_iomap(node, 0);
-		break;
-	}
-}
-
 static void __init exynos_init_late(void)
 {
 	if (of_machine_is_compatible("samsung,exynos5440"))
diff --git a/drivers/soc/samsung/Makefile b/drivers/soc/samsung/Makefile
index d2e637339a45..58ca5bdabf1f 100644
--- a/drivers/soc/samsung/Makefile
+++ b/drivers/soc/samsung/Makefile
@@ -1,5 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_EXYNOS_PMU)	+= exynos-pmu.o
+obj-$(CONFIG_EXYNOS_PMU)	+= exynos-pmu.o exynos-pm.o

 obj-$(CONFIG_EXYNOS_PMU_ARM_DRIVERS)	+= exynos3250-pmu.o exynos4-pmu.o \
 					exynos5250-pmu.o exynos5420-pmu.o \
diff --git a/drivers/soc/samsung/exynos-pm.c b/drivers/soc/samsung/exynos-pm.c
new file mode 100644
index 000000000000..45d84bbe5e61
--- /dev/null
+++ b/drivers/soc/samsung/exynos-pm.c
@@ -0,0 +1,176 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// based on arch/arm/mach-exynos/suspend.c
+// Copyright (c) 2018 Samsung Electronics Co., Ltd.
+//
+// Exynos Power Management support driver
+
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_fdt.h>
+#include <linux/kernel.h>
+#include <linux/regulator/machine.h>
+#include <linux/syscore_ops.h>
+#include <linux/suspend.h>
+
+#include <asm/cpuidle.h>
+#include <asm/io.h>
+#include <asm/suspend.h>
+
+#include <linux/soc/samsung/exynos-pm.h>
+#include <linux/soc/samsung/exynos-pmu.h>
+
+/*
+ * The struct exynos_pm_data contains the callbacks of
+ * both struct platform_suspend_ops and syscore_ops.
+ * This structure is listed according to the call order,
+ * because the callback call order for the two structures is mixed.
+ */
+struct exynos_pm_data {
+	int (*prepare)(void);			/* for platform_suspend_ops */
+	int (*suspend)(void);			/* for syscore_ops */
+	int (*enter)(suspend_state_t state);	/* for platform_suspend_ops */
+	void (*resume)(void);			/* for syscore_ops */
+	void (*finish)(void);			/* for platform_suspend_ops */
+};
+
+static struct platform_suspend_ops exynos_pm_suspend_ops;
+static struct syscore_ops exynos_pm_syscore_ops;
+static const struct exynos_pm_data *pm_data  __ro_after_init;
+
+void __iomem *sysram_base_addr __ro_after_init;
+void __iomem *sysram_ns_base_addr __ro_after_init;
+
+static int exynos_pm_prepare(void)
+{
+	int ret;
+
+	/*
+	 * REVISIT: It would be better if struct platform_suspend_ops
+	 * .prepare handler get the suspend_state_t as a parameter to
+	 * avoid hard-coding the suspend to mem state. It's safe to do
+	 * it now only because the suspend_valid_only_mem function is
+	 * used as the .valid callback used to check if a given state
+	 * is supported by the platform anyways.
+	 */
+	ret = regulator_suspend_prepare(PM_SUSPEND_MEM);
+	if (ret) {
+		pr_err("Failed to prepare regulators for suspend (%d)\n", ret);
+		return ret;
+	}
+
+	if (pm_data->prepare) {
+		ret = pm_data->prepare();
+		if (ret) {
+			pr_err("Failed to prepare for suspend (%d)\n", ret);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+static int exynos_pm_suspend(void)
+{
+	if (pm_data->suspend)
+		return pm_data->suspend();
+
+	return 0;
+}
+
+static int exynos_pm_enter(suspend_state_t state)
+{
+	int ret;
+
+	exynos_sys_powerdown_conf(SYS_SLEEP);
+
+	ret = pm_data->enter(state);
+	if (ret) {
+		pr_err("Failed to enter sleep\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static void exynos_pm_resume(void)
+{
+	exynos_sys_powerup_conf(SYS_SLEEP);
+
+	if (pm_data->resume)
+		pm_data->resume();
+}
+
+static void exynos_pm_finish(void)
+{
+	int ret;
+
+	ret = regulator_suspend_finish();
+	if (ret)
+		pr_warn("Failed to resume regulators from suspend (%d)\n", ret);
+
+	if (pm_data->finish)
+		pm_data->finish();
+}
+
+/*
+ * Split the data between ARM architectures because it is relatively big
+ * and useless on other arch.
+ */
+#ifdef CONFIG_EXYNOS_PMU_ARM_DRIVERS
+#define exynos_pm_data_arm_ptr(data)	(&data)
+#else
+#define exynos_pm_data_arm_ptr(data)	NULL
+#endif
+
+static const struct of_device_id exynos_pm_of_device_ids[] = {
+	{ /*sentinel*/ },
+};
+
+void __init exynos_sysram_init(void)
+{
+	struct device_node *np;
+
+	for_each_compatible_node(np, NULL, "samsung,exynos4210-sysram") {
+		if (!of_device_is_available(np))
+			continue;
+		sysram_base_addr = of_iomap(np, 0);
+		break;
+	}
+
+	for_each_compatible_node(np, NULL, "samsung,exynos4210-sysram-ns") {
+		if (!of_device_is_available(np))
+			continue;
+		sysram_ns_base_addr = of_iomap(np, 0);
+		break;
+	}
+}
+
+static int __init exynos_pm_init(void)
+{
+	const struct of_device_id *match;
+	struct device_node *np;
+
+	np = of_find_matching_node_and_match(NULL,
+					exynos_pm_of_device_ids, &match);
+	if (!np) {
+		pr_err("Failed to find PMU node for Exynos Power-Management\n");
+		return -ENODEV;
+	}
+	pm_data = (const struct exynos_pm_data *) match->data;
+
+	exynos_sysram_init();
+
+	exynos_pm_suspend_ops.valid	= suspend_valid_only_mem;
+	exynos_pm_suspend_ops.prepare	= exynos_pm_prepare;
+	exynos_pm_syscore_ops.suspend	= exynos_pm_suspend;
+	exynos_pm_suspend_ops.enter	= exynos_pm_enter;
+	exynos_pm_syscore_ops.resume	= exynos_pm_resume;
+	exynos_pm_suspend_ops.finish	= exynos_pm_finish;
+
+	register_syscore_ops(&exynos_pm_syscore_ops);
+	suspend_set_ops(&exynos_pm_suspend_ops);
+
+	return 0;
+}
+postcore_initcall(exynos_pm_init);
diff --git a/include/linux/soc/samsung/exynos-pm.h b/include/linux/soc/samsung/exynos-pm.h
new file mode 100644
index 000000000000..b1afe95ed10c
--- /dev/null
+++ b/include/linux/soc/samsung/exynos-pm.h
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2018 Samsung Electronics Co., Ltd.
+//
+// Header for Exynos Power-Management support driver
+
+#ifndef __LINUX_SOC_EXYNOS_PM_H
+#define __LINUX_SOC_EXYNOS_PM_H
+
+/*
+ * Magic values for bootloader indicating chosen low power mode.
+ * See also Documentation/arm/Samsung/Bootloader-interface.txt
+ */
+#define EXYNOS_SLEEP_MAGIC	0x00000bad
+
+extern void __iomem *sysram_base_addr;
+extern void __iomem *sysram_ns_base_addr;
+
+extern void exynos_sysram_init(void);
+
+#endif /* __LINUX_SOC_EXYNOS_PMU_H */
--
1.9.1

Re: [RFC PATCH 4/9] soc: samsung: Add generic power-management driver for Exynos

[Krzysztof Kozlowski]

On Tue, Jan 9, 2018 at 8:59 AM, Chanwoo Choi <cw00.choi@samsung.com> wrote:
> To enter suspend, Exynos SoC requires the some machine dependent procedures.
> This patch introduces the generic power-management driver to support
> those requirements and generic interface for power state management.
>
> Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> ---
>  arch/arm/mach-exynos/common.h         |   1 -
>  arch/arm/mach-exynos/exynos.c         |  23 +----
>  drivers/soc/samsung/Makefile          |   2 +-
>  drivers/soc/samsung/exynos-pm.c       | 176 ++++++++++++++++++++++++++++++++++
>  include/linux/soc/samsung/exynos-pm.h |  21 ++++
>  5 files changed, 199 insertions(+), 24 deletions(-)
>  create mode 100644 drivers/soc/samsung/exynos-pm.c
>  create mode 100644 include/linux/soc/samsung/exynos-pm.h
>
> diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
> index afbc143a3d5d..ad482c0fc131 100644
> --- a/arch/arm/mach-exynos/common.h
> +++ b/arch/arm/mach-exynos/common.h
> @@ -119,7 +119,6 @@ enum {
>   * Magic values for bootloader indicating chosen low power mode.
>   * See also Documentation/arm/Samsung/Bootloader-interface.txt
>   */
> -#define EXYNOS_SLEEP_MAGIC     0x00000bad
>  #define EXYNOS_AFTR_MAGIC      0xfcba0d10
>
>  void exynos_set_boot_flag(unsigned int cpu, unsigned int mode);
> diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
> index fbd108ce8745..0d5265d175c4 100644
> --- a/arch/arm/mach-exynos/exynos.c
> +++ b/arch/arm/mach-exynos/exynos.c
> @@ -12,6 +12,7 @@
>  #include <linux/of_fdt.h>

of_address.h might be not needed anymore.

>  #include <linux/platform_device.h>
>  #include <linux/irqchip.h>
> +#include <linux/soc/samsung/exynos-pm.h>
>  #include <linux/soc/samsung/exynos-regs-pmu.h>
>
>  #include <asm/cacheflush.h>
> @@ -41,28 +42,6 @@
>         .id                = -1,
>  };
>
> -void __iomem *sysram_base_addr __ro_after_init;
> -void __iomem *sysram_ns_base_addr __ro_after_init;
> -
> -void __init exynos_sysram_init(void)
> -{
> -       struct device_node *node;
> -
> -       for_each_compatible_node(node, NULL, "samsung,exynos4210-sysram") {
> -               if (!of_device_is_available(node))
> -                       continue;
> -               sysram_base_addr = of_iomap(node, 0);
> -               break;
> -       }
> -
> -       for_each_compatible_node(node, NULL, "samsung,exynos4210-sysram-ns") {
> -               if (!of_device_is_available(node))
> -                       continue;
> -               sysram_ns_base_addr = of_iomap(node, 0);
> -               break;
> -       }
> -}
> -
>  static void __init exynos_init_late(void)
>  {
>         if (of_machine_is_compatible("samsung,exynos5440"))
> diff --git a/drivers/soc/samsung/Makefile b/drivers/soc/samsung/Makefile
> index d2e637339a45..58ca5bdabf1f 100644
> --- a/drivers/soc/samsung/Makefile
> +++ b/drivers/soc/samsung/Makefile
> @@ -1,5 +1,5 @@
>  # SPDX-License-Identifier: GPL-2.0
> -obj-$(CONFIG_EXYNOS_PMU)       += exynos-pmu.o
> +obj-$(CONFIG_EXYNOS_PMU)       += exynos-pmu.o exynos-pm.o
>
>  obj-$(CONFIG_EXYNOS_PMU_ARM_DRIVERS)   += exynos3250-pmu.o exynos4-pmu.o \
>                                         exynos5250-pmu.o exynos5420-pmu.o \
> diff --git a/drivers/soc/samsung/exynos-pm.c b/drivers/soc/samsung/exynos-pm.c
> new file mode 100644
> index 000000000000..45d84bbe5e61
> --- /dev/null
> +++ b/drivers/soc/samsung/exynos-pm.c
> @@ -0,0 +1,176 @@
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// based on arch/arm/mach-exynos/suspend.c
> +// Copyright (c) 2018 Samsung Electronics Co., Ltd.
> +//
> +// Exynos Power Management support driver
> +
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_fdt.h>
> +#include <linux/kernel.h>
> +#include <linux/regulator/machine.h>
> +#include <linux/syscore_ops.h>
> +#include <linux/suspend.h>
> +
> +#include <asm/cpuidle.h>
> +#include <asm/io.h>
> +#include <asm/suspend.h>
> +
> +#include <linux/soc/samsung/exynos-pm.h>
> +#include <linux/soc/samsung/exynos-pmu.h>
> +
> +/*
> + * The struct exynos_pm_data contains the callbacks of
> + * both struct platform_suspend_ops and syscore_ops.
> + * This structure is listed according to the call order,
> + * because the callback call order for the two structures is mixed.
> + */
> +struct exynos_pm_data {
> +       int (*prepare)(void);                   /* for platform_suspend_ops */
> +       int (*suspend)(void);                   /* for syscore_ops */
> +       int (*enter)(suspend_state_t state);    /* for platform_suspend_ops */
> +       void (*resume)(void);                   /* for syscore_ops */
> +       void (*finish)(void);                   /* for platform_suspend_ops */
> +};
> +
> +static struct platform_suspend_ops exynos_pm_suspend_ops;
> +static struct syscore_ops exynos_pm_syscore_ops;
> +static const struct exynos_pm_data *pm_data  __ro_after_init;

It is already const, so __initconst?

> +
> +void __iomem *sysram_base_addr __ro_after_init;
> +void __iomem *sysram_ns_base_addr __ro_after_init;
> +
> +static int exynos_pm_prepare(void)
> +{
> +       int ret;
> +
> +       /*
> +        * REVISIT: It would be better if struct platform_suspend_ops
> +        * .prepare handler get the suspend_state_t as a parameter to
> +        * avoid hard-coding the suspend to mem state. It's safe to do
> +        * it now only because the suspend_valid_only_mem function is
> +        * used as the .valid callback used to check if a given state
> +        * is supported by the platform anyways.
> +        */
> +       ret = regulator_suspend_prepare(PM_SUSPEND_MEM);
> +       if (ret) {
> +               pr_err("Failed to prepare regulators for suspend (%d)\n", ret);
> +               return ret;
> +       }
> +
> +       if (pm_data->prepare) {
> +               ret = pm_data->prepare();
> +               if (ret) {
> +                       pr_err("Failed to prepare for suspend (%d)\n", ret);
> +                       return ret;
> +               }
> +       }
> +
> +       return 0;
> +}
> +
> +static int exynos_pm_suspend(void)
> +{
> +       if (pm_data->suspend)
> +               return pm_data->suspend();
> +
> +       return 0;
> +}
> +
> +static int exynos_pm_enter(suspend_state_t state)
> +{
> +       int ret;
> +
> +       exynos_sys_powerdown_conf(SYS_SLEEP);
> +
> +       ret = pm_data->enter(state);
> +       if (ret) {
> +               pr_err("Failed to enter sleep\n");
> +               return ret;
> +       }
> +
> +       return 0;
> +}
> +
> +static void exynos_pm_resume(void)
> +{
> +       exynos_sys_powerup_conf(SYS_SLEEP);
> +
> +       if (pm_data->resume)
> +               pm_data->resume();
> +}
> +
> +static void exynos_pm_finish(void)
> +{
> +       int ret;
> +
> +       ret = regulator_suspend_finish();
> +       if (ret)
> +               pr_warn("Failed to resume regulators from suspend (%d)\n", ret);
> +
> +       if (pm_data->finish)
> +               pm_data->finish();
> +}
> +
> +/*
> + * Split the data between ARM architectures because it is relatively big
> + * and useless on other arch.
> + */
> +#ifdef CONFIG_EXYNOS_PMU_ARM_DRIVERS
> +#define exynos_pm_data_arm_ptr(data)   (&data)
> +#else
> +#define exynos_pm_data_arm_ptr(data)   NULL
> +#endif
> +
> +static const struct of_device_id exynos_pm_of_device_ids[] = {
> +       { /*sentinel*/ },
> +};
> +
> +void __init exynos_sysram_init(void)
> +{
> +       struct device_node *np;
> +
> +       for_each_compatible_node(np, NULL, "samsung,exynos4210-sysram") {
> +               if (!of_device_is_available(np))
> +                       continue;
> +               sysram_base_addr = of_iomap(np, 0);
> +               break;
> +       }
> +
> +       for_each_compatible_node(np, NULL, "samsung,exynos4210-sysram-ns") {
> +               if (!of_device_is_available(np))
> +                       continue;
> +               sysram_ns_base_addr = of_iomap(np, 0);
> +               break;
> +       }
> +}
> +
> +static int __init exynos_pm_init(void)
> +{
> +       const struct of_device_id *match;
> +       struct device_node *np;
> +
> +       np = of_find_matching_node_and_match(NULL,
> +                                       exynos_pm_of_device_ids, &match);
> +       if (!np) {
> +               pr_err("Failed to find PMU node for Exynos Power-Management\n");
> +               return -ENODEV;
> +       }
> +       pm_data = (const struct exynos_pm_data *) match->data;
> +
> +       exynos_sysram_init();
> +
> +       exynos_pm_suspend_ops.valid     = suspend_valid_only_mem;
> +       exynos_pm_suspend_ops.prepare   = exynos_pm_prepare;
> +       exynos_pm_syscore_ops.suspend   = exynos_pm_suspend;
> +       exynos_pm_suspend_ops.enter     = exynos_pm_enter;
> +       exynos_pm_syscore_ops.resume    = exynos_pm_resume;
> +       exynos_pm_suspend_ops.finish    = exynos_pm_finish;
> +
> +       register_syscore_ops(&exynos_pm_syscore_ops);
> +       suspend_set_ops(&exynos_pm_suspend_ops);
> +
> +       return 0;
> +}
> +postcore_initcall(exynos_pm_init);

As I mentioned in cover letter, please move here first ARMv7 code. Now
it looks like duplicating the existing code.

> diff --git a/include/linux/soc/samsung/exynos-pm.h b/include/linux/soc/samsung/exynos-pm.h
> new file mode 100644
> index 000000000000..b1afe95ed10c
> --- /dev/null
> +++ b/include/linux/soc/samsung/exynos-pm.h
> @@ -0,0 +1,21 @@
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright (c) 2018 Samsung Electronics Co., Ltd.
> +//
> +// Header for Exynos Power-Management support driver

Use header-style SPDX and comment.

Best regards,
Krzysztof

> +
> +#ifndef __LINUX_SOC_EXYNOS_PM_H
> +#define __LINUX_SOC_EXYNOS_PM_H
> +
> +/*
> + * Magic values for bootloader indicating chosen low power mode.
> + * See also Documentation/arm/Samsung/Bootloader-interface.txt
> + */
> +#define EXYNOS_SLEEP_MAGIC     0x00000bad
> +
> +extern void __iomem *sysram_base_addr;
> +extern void __iomem *sysram_ns_base_addr;

Since these are now global symbols, they need nice exynos prefix.
Also, probably they should not be globally modifiable. Only
exynos_sysram_init() should write there. Instead export a global
accessor (get()) and rest should use that one.

Best regards,
Krzysztof

> +
> +extern void exynos_sysram_init(void);
> +
> +#endif /* __LINUX_SOC_EXYNOS_PMU_H */
> --
> 1.9.1
>

Re: [RFC PATCH 4/9] soc: samsung: Add generic power-management driver for Exynos

[Chanwoo Choi]

Dear Krzysztof,

I'll try to consolidate the pm code for both arm and arm64.
So, drop this patch and then I'll start to move the code
from arch/arm/mach-exynos/* to drivers/soc/samsung/*.

But, I'm not sure it is possible to move all codes
to drivers/soc/samsung/*. I'll try it.

Best Regards,
Chanwoo Choi
Samsung Electronics

On 2018년 01월 09일 21:37, Krzysztof Kozlowski wrote:
> On Tue, Jan 9, 2018 at 8:59 AM, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>> To enter suspend, Exynos SoC requires the some machine dependent procedures.
>> This patch introduces the generic power-management driver to support
>> those requirements and generic interface for power state management.
>>
>> Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>> ---
>>  arch/arm/mach-exynos/common.h         |   1 -
>>  arch/arm/mach-exynos/exynos.c         |  23 +----
>>  drivers/soc/samsung/Makefile          |   2 +-
>>  drivers/soc/samsung/exynos-pm.c       | 176 ++++++++++++++++++++++++++++++++++
>>  include/linux/soc/samsung/exynos-pm.h |  21 ++++
>>  5 files changed, 199 insertions(+), 24 deletions(-)
>>  create mode 100644 drivers/soc/samsung/exynos-pm.c
>>  create mode 100644 include/linux/soc/samsung/exynos-pm.h
>>
>> diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
>> index afbc143a3d5d..ad482c0fc131 100644
>> --- a/arch/arm/mach-exynos/common.h
>> +++ b/arch/arm/mach-exynos/common.h
>> @@ -119,7 +119,6 @@ enum {
>>   * Magic values for bootloader indicating chosen low power mode.
>>   * See also Documentation/arm/Samsung/Bootloader-interface.txt
>>   */
>> -#define EXYNOS_SLEEP_MAGIC     0x00000bad
>>  #define EXYNOS_AFTR_MAGIC      0xfcba0d10
>>
>>  void exynos_set_boot_flag(unsigned int cpu, unsigned int mode);
>> diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
>> index fbd108ce8745..0d5265d175c4 100644
>> --- a/arch/arm/mach-exynos/exynos.c
>> +++ b/arch/arm/mach-exynos/exynos.c
>> @@ -12,6 +12,7 @@
>>  #include <linux/of_fdt.h>
> 
> of_address.h might be not needed anymore.
> 
>>  #include <linux/platform_device.h>
>>  #include <linux/irqchip.h>
>> +#include <linux/soc/samsung/exynos-pm.h>
>>  #include <linux/soc/samsung/exynos-regs-pmu.h>
>>
>>  #include <asm/cacheflush.h>
>> @@ -41,28 +42,6 @@
>>         .id                = -1,
>>  };
>>
>> -void __iomem *sysram_base_addr __ro_after_init;
>> -void __iomem *sysram_ns_base_addr __ro_after_init;
>> -
>> -void __init exynos_sysram_init(void)
>> -{
>> -       struct device_node *node;
>> -
>> -       for_each_compatible_node(node, NULL, "samsung,exynos4210-sysram") {
>> -               if (!of_device_is_available(node))
>> -                       continue;
>> -               sysram_base_addr = of_iomap(node, 0);
>> -               break;
>> -       }
>> -
>> -       for_each_compatible_node(node, NULL, "samsung,exynos4210-sysram-ns") {
>> -               if (!of_device_is_available(node))
>> -                       continue;
>> -               sysram_ns_base_addr = of_iomap(node, 0);
>> -               break;
>> -       }
>> -}
>> -
>>  static void __init exynos_init_late(void)
>>  {
>>         if (of_machine_is_compatible("samsung,exynos5440"))
>> diff --git a/drivers/soc/samsung/Makefile b/drivers/soc/samsung/Makefile
>> index d2e637339a45..58ca5bdabf1f 100644
>> --- a/drivers/soc/samsung/Makefile
>> +++ b/drivers/soc/samsung/Makefile
>> @@ -1,5 +1,5 @@
>>  # SPDX-License-Identifier: GPL-2.0
>> -obj-$(CONFIG_EXYNOS_PMU)       += exynos-pmu.o
>> +obj-$(CONFIG_EXYNOS_PMU)       += exynos-pmu.o exynos-pm.o
>>
>>  obj-$(CONFIG_EXYNOS_PMU_ARM_DRIVERS)   += exynos3250-pmu.o exynos4-pmu.o \
>>                                         exynos5250-pmu.o exynos5420-pmu.o \
>> diff --git a/drivers/soc/samsung/exynos-pm.c b/drivers/soc/samsung/exynos-pm.c
>> new file mode 100644
>> index 000000000000..45d84bbe5e61
>> --- /dev/null
>> +++ b/drivers/soc/samsung/exynos-pm.c
>> @@ -0,0 +1,176 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +//
>> +// based on arch/arm/mach-exynos/suspend.c
>> +// Copyright (c) 2018 Samsung Electronics Co., Ltd.
>> +//
>> +// Exynos Power Management support driver
>> +
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
>> +#include <linux/of_fdt.h>
>> +#include <linux/kernel.h>
>> +#include <linux/regulator/machine.h>
>> +#include <linux/syscore_ops.h>
>> +#include <linux/suspend.h>
>> +
>> +#include <asm/cpuidle.h>
>> +#include <asm/io.h>
>> +#include <asm/suspend.h>
>> +
>> +#include <linux/soc/samsung/exynos-pm.h>
>> +#include <linux/soc/samsung/exynos-pmu.h>
>> +
>> +/*
>> + * The struct exynos_pm_data contains the callbacks of
>> + * both struct platform_suspend_ops and syscore_ops.
>> + * This structure is listed according to the call order,
>> + * because the callback call order for the two structures is mixed.
>> + */
>> +struct exynos_pm_data {
>> +       int (*prepare)(void);                   /* for platform_suspend_ops */
>> +       int (*suspend)(void);                   /* for syscore_ops */
>> +       int (*enter)(suspend_state_t state);    /* for platform_suspend_ops */
>> +       void (*resume)(void);                   /* for syscore_ops */
>> +       void (*finish)(void);                   /* for platform_suspend_ops */
>> +};
>> +
>> +static struct platform_suspend_ops exynos_pm_suspend_ops;
>> +static struct syscore_ops exynos_pm_syscore_ops;
>> +static const struct exynos_pm_data *pm_data  __ro_after_init;
> 
> It is already const, so __initconst?
> 
>> +
>> +void __iomem *sysram_base_addr __ro_after_init;
>> +void __iomem *sysram_ns_base_addr __ro_after_init;
>> +
>> +static int exynos_pm_prepare(void)
>> +{
>> +       int ret;
>> +
>> +       /*
>> +        * REVISIT: It would be better if struct platform_suspend_ops
>> +        * .prepare handler get the suspend_state_t as a parameter to
>> +        * avoid hard-coding the suspend to mem state. It's safe to do
>> +        * it now only because the suspend_valid_only_mem function is
>> +        * used as the .valid callback used to check if a given state
>> +        * is supported by the platform anyways.
>> +        */
>> +       ret = regulator_suspend_prepare(PM_SUSPEND_MEM);
>> +       if (ret) {
>> +               pr_err("Failed to prepare regulators for suspend (%d)\n", ret);
>> +               return ret;
>> +       }
>> +
>> +       if (pm_data->prepare) {
>> +               ret = pm_data->prepare();
>> +               if (ret) {
>> +                       pr_err("Failed to prepare for suspend (%d)\n", ret);
>> +                       return ret;
>> +               }
>> +       }
>> +
>> +       return 0;
>> +}
>> +
>> +static int exynos_pm_suspend(void)
>> +{
>> +       if (pm_data->suspend)
>> +               return pm_data->suspend();
>> +
>> +       return 0;
>> +}
>> +
>> +static int exynos_pm_enter(suspend_state_t state)
>> +{
>> +       int ret;
>> +
>> +       exynos_sys_powerdown_conf(SYS_SLEEP);
>> +
>> +       ret = pm_data->enter(state);
>> +       if (ret) {
>> +               pr_err("Failed to enter sleep\n");
>> +               return ret;
>> +       }
>> +
>> +       return 0;
>> +}
>> +
>> +static void exynos_pm_resume(void)
>> +{
>> +       exynos_sys_powerup_conf(SYS_SLEEP);
>> +
>> +       if (pm_data->resume)
>> +               pm_data->resume();
>> +}
>> +
>> +static void exynos_pm_finish(void)
>> +{
>> +       int ret;
>> +
>> +       ret = regulator_suspend_finish();
>> +       if (ret)
>> +               pr_warn("Failed to resume regulators from suspend (%d)\n", ret);
>> +
>> +       if (pm_data->finish)
>> +               pm_data->finish();
>> +}
>> +
>> +/*
>> + * Split the data between ARM architectures because it is relatively big
>> + * and useless on other arch.
>> + */
>> +#ifdef CONFIG_EXYNOS_PMU_ARM_DRIVERS
>> +#define exynos_pm_data_arm_ptr(data)   (&data)
>> +#else
>> +#define exynos_pm_data_arm_ptr(data)   NULL
>> +#endif
>> +
>> +static const struct of_device_id exynos_pm_of_device_ids[] = {
>> +       { /*sentinel*/ },
>> +};
>> +
>> +void __init exynos_sysram_init(void)
>> +{
>> +       struct device_node *np;
>> +
>> +       for_each_compatible_node(np, NULL, "samsung,exynos4210-sysram") {
>> +               if (!of_device_is_available(np))
>> +                       continue;
>> +               sysram_base_addr = of_iomap(np, 0);
>> +               break;
>> +       }
>> +
>> +       for_each_compatible_node(np, NULL, "samsung,exynos4210-sysram-ns") {
>> +               if (!of_device_is_available(np))
>> +                       continue;
>> +               sysram_ns_base_addr = of_iomap(np, 0);
>> +               break;
>> +       }
>> +}
>> +
>> +static int __init exynos_pm_init(void)
>> +{
>> +       const struct of_device_id *match;
>> +       struct device_node *np;
>> +
>> +       np = of_find_matching_node_and_match(NULL,
>> +                                       exynos_pm_of_device_ids, &match);
>> +       if (!np) {
>> +               pr_err("Failed to find PMU node for Exynos Power-Management\n");
>> +               return -ENODEV;
>> +       }
>> +       pm_data = (const struct exynos_pm_data *) match->data;
>> +
>> +       exynos_sysram_init();
>> +
>> +       exynos_pm_suspend_ops.valid     = suspend_valid_only_mem;
>> +       exynos_pm_suspend_ops.prepare   = exynos_pm_prepare;
>> +       exynos_pm_syscore_ops.suspend   = exynos_pm_suspend;
>> +       exynos_pm_suspend_ops.enter     = exynos_pm_enter;
>> +       exynos_pm_syscore_ops.resume    = exynos_pm_resume;
>> +       exynos_pm_suspend_ops.finish    = exynos_pm_finish;
>> +
>> +       register_syscore_ops(&exynos_pm_syscore_ops);
>> +       suspend_set_ops(&exynos_pm_suspend_ops);
>> +
>> +       return 0;
>> +}
>> +postcore_initcall(exynos_pm_init);
> 
> As I mentioned in cover letter, please move here first ARMv7 code. Now
> it looks like duplicating the existing code.
> 
>> diff --git a/include/linux/soc/samsung/exynos-pm.h b/include/linux/soc/samsung/exynos-pm.h
>> new file mode 100644
>> index 000000000000..b1afe95ed10c
>> --- /dev/null
>> +++ b/include/linux/soc/samsung/exynos-pm.h
>> @@ -0,0 +1,21 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +//
>> +// Copyright (c) 2018 Samsung Electronics Co., Ltd.
>> +//
>> +// Header for Exynos Power-Management support driver
> 
> Use header-style SPDX and comment.
> 
> Best regards,
> Krzysztof
> 
>> +
>> +#ifndef __LINUX_SOC_EXYNOS_PM_H
>> +#define __LINUX_SOC_EXYNOS_PM_H
>> +
>> +/*
>> + * Magic values for bootloader indicating chosen low power mode.
>> + * See also Documentation/arm/Samsung/Bootloader-interface.txt
>> + */
>> +#define EXYNOS_SLEEP_MAGIC     0x00000bad
>> +
>> +extern void __iomem *sysram_base_addr;
>> +extern void __iomem *sysram_ns_base_addr;
> 
> Since these are now global symbols, they need nice exynos prefix.
> Also, probably they should not be globally modifiable. Only
> exynos_sysram_init() should write there. Instead export a global
> accessor (get()) and rest should use that one.
> 
> Best regards,
> Krzysztof
> 
>> +
>> +extern void exynos_sysram_init(void);
>> +
>> +#endif /* __LINUX_SOC_EXYNOS_PMU_H */
>> --
>> 1.9.1
>>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 
> 
> 

[RFC PATCH 5/9] soc: samsung: pm: Add support for suspend-to-ram of Exynos5433

[Chanwoo Choi]

This patch adds the specific exynos_pm_data instance for Exynos5433
in order to support the suspend-to-ram. Exynos5433 SoC need to write
the 'cpu_resume' poiter address and the specific magic number
for suspend mode.

Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
 drivers/soc/samsung/exynos-pm.c | 38 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/drivers/soc/samsung/exynos-pm.c b/drivers/soc/samsung/exynos-pm.c
index 45d84bbe5e61..70d949ba5cab 100644
--- a/drivers/soc/samsung/exynos-pm.c
+++ b/drivers/soc/samsung/exynos-pm.c
@@ -12,6 +12,7 @@
 #include <linux/regulator/machine.h>
 #include <linux/syscore_ops.h>
 #include <linux/suspend.h>
+#include <linux/psci.h>

 #include <asm/cpuidle.h>
 #include <asm/io.h>
@@ -123,7 +124,44 @@ static void exynos_pm_finish(void)
 #define exynos_pm_data_arm_ptr(data)	NULL
 #endif

+static int exynos5433_pm_suspend(unsigned long unused)
+{
+	/*
+	 * Exynos5433 uses PSCI v0.1 which provides the only one
+	 * entry point (psci_ops.cpu_suspend) for both cpuidle and
+	 * suspend-to-RAM. Also, PSCI v0.1 needs the specific 'power_state'
+	 * parameter for the suspend mode. In order to enter suspend mode,
+	 * Exynos5433 calls the 'psci_ops.cpu_suspend' with '0x3010000'
+	 * power_state parameter.
+	 *
+	 * '0x3010000' means that both cluster and system are going to enter
+	 * the power-down state as following:
+	 * - [25:24] 0x3 : Indicate the cluster and system.
+	 * - [16]    0x1 : Indicate power-down state.
+	 */
+	return psci_ops.cpu_suspend(0x3010000, __pa_symbol(cpu_resume));
+}
+
+static int exynos5433_pm_suspend_enter(suspend_state_t state)
+{
+	if (!sysram_ns_base_addr)
+		return -EINVAL;
+
+	__raw_writel(virt_to_phys(cpu_resume), sysram_ns_base_addr + 0x8);
+	__raw_writel(EXYNOS_SLEEP_MAGIC, sysram_ns_base_addr + 0xc);
+
+	return cpu_suspend(0, exynos5433_pm_suspend);
+}
+
+const struct exynos_pm_data exynos5433_pm_data = {
+	.enter		= exynos5433_pm_suspend_enter,
+};
+
 static const struct of_device_id exynos_pm_of_device_ids[] = {
+	{
+		.compatible = "samsung,exynos5433-pmu",
+		.data = exynos_pm_data_arm_ptr(exynos5433_pm_data),
+	},
 	{ /*sentinel*/ },
 };

--
1.9.1

Re: [RFC PATCH 5/9] soc: samsung: pm: Add support for suspend-to-ram of Exynos5433

[Krzysztof Kozlowski]

On Tue, Jan 9, 2018 at 8:59 AM, Chanwoo Choi <cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> wrote:
> This patch adds the specific exynos_pm_data instance for Exynos5433
> in order to support the suspend-to-ram. Exynos5433 SoC need to write
> the 'cpu_resume' poiter address and the specific magic number
> for suspend mode.
>
> Signed-off-by: Jonghwa Lee <jonghwa3.lee-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> Signed-off-by: Chanwoo Choi <cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> ---
>  drivers/soc/samsung/exynos-pm.c | 38 ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 38 insertions(+)
>
> diff --git a/drivers/soc/samsung/exynos-pm.c b/drivers/soc/samsung/exynos-pm.c
> index 45d84bbe5e61..70d949ba5cab 100644
> --- a/drivers/soc/samsung/exynos-pm.c
> +++ b/drivers/soc/samsung/exynos-pm.c
> @@ -12,6 +12,7 @@
>  #include <linux/regulator/machine.h>
>  #include <linux/syscore_ops.h>
>  #include <linux/suspend.h>
> +#include <linux/psci.h>
>
>  #include <asm/cpuidle.h>
>  #include <asm/io.h>
> @@ -123,7 +124,44 @@ static void exynos_pm_finish(void)
>  #define exynos_pm_data_arm_ptr(data)   NULL
>  #endif
>
> +static int exynos5433_pm_suspend(unsigned long unused)
> +{
> +       /*
> +        * Exynos5433 uses PSCI v0.1 which provides the only one
> +        * entry point (psci_ops.cpu_suspend) for both cpuidle and
> +        * suspend-to-RAM. Also, PSCI v0.1 needs the specific 'power_state'
> +        * parameter for the suspend mode. In order to enter suspend mode,
> +        * Exynos5433 calls the 'psci_ops.cpu_suspend' with '0x3010000'
> +        * power_state parameter.
> +        *
> +        * '0x3010000' means that both cluster and system are going to enter
> +        * the power-down state as following:
> +        * - [25:24] 0x3 : Indicate the cluster and system.
> +        * - [16]    0x1 : Indicate power-down state.

Define them, it will be more readable (name of define given just as an example):

EXYNOS5433_PCSI_SUSPEND_SYSTEM (0x3 << 24)
(or even split per system and cluser and use BIT() if this is real meaning)
and probably reuse existing S5P_CENTRAL_LOWPWR_CFG

> +        */
> +       return psci_ops.cpu_suspend(0x3010000, __pa_symbol(cpu_resume));
> +}
> +
> +static int exynos5433_pm_suspend_enter(suspend_state_t state)
> +{
> +       if (!sysram_ns_base_addr)
> +               return -EINVAL;
> +
> +       __raw_writel(virt_to_phys(cpu_resume), sysram_ns_base_addr + 0x8);
> +       __raw_writel(EXYNOS_SLEEP_MAGIC, sysram_ns_base_addr + 0xc);

Document them in Documentation/arm/Samsung/Bootloader-interface.txt.

Best regards,
Krzysztof

> +
> +       return cpu_suspend(0, exynos5433_pm_suspend);
> +}
> +
> +const struct exynos_pm_data exynos5433_pm_data = {
> +       .enter          = exynos5433_pm_suspend_enter,
> +};
> +
>  static const struct of_device_id exynos_pm_of_device_ids[] = {
> +       {
> +               .compatible = "samsung,exynos5433-pmu",
> +               .data = exynos_pm_data_arm_ptr(exynos5433_pm_data),
> +       },
>         { /*sentinel*/ },
>  };
>
> --
> 1.9.1
>
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Re: [RFC PATCH 5/9] soc: samsung: pm: Add support for suspend-to-ram of Exynos5433

[Chanwoo Choi]

On 2018년 01월 09일 21:45, Krzysztof Kozlowski wrote:
> On Tue, Jan 9, 2018 at 8:59 AM, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>> This patch adds the specific exynos_pm_data instance for Exynos5433
>> in order to support the suspend-to-ram. Exynos5433 SoC need to write
>> the 'cpu_resume' poiter address and the specific magic number
>> for suspend mode.
>>
>> Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>> ---
>>  drivers/soc/samsung/exynos-pm.c | 38 ++++++++++++++++++++++++++++++++++++++
>>  1 file changed, 38 insertions(+)
>>
>> diff --git a/drivers/soc/samsung/exynos-pm.c b/drivers/soc/samsung/exynos-pm.c
>> index 45d84bbe5e61..70d949ba5cab 100644
>> --- a/drivers/soc/samsung/exynos-pm.c
>> +++ b/drivers/soc/samsung/exynos-pm.c
>> @@ -12,6 +12,7 @@
>>  #include <linux/regulator/machine.h>
>>  #include <linux/syscore_ops.h>
>>  #include <linux/suspend.h>
>> +#include <linux/psci.h>
>>
>>  #include <asm/cpuidle.h>
>>  #include <asm/io.h>
>> @@ -123,7 +124,44 @@ static void exynos_pm_finish(void)
>>  #define exynos_pm_data_arm_ptr(data)   NULL
>>  #endif
>>
>> +static int exynos5433_pm_suspend(unsigned long unused)
>> +{
>> +       /*
>> +        * Exynos5433 uses PSCI v0.1 which provides the only one
>> +        * entry point (psci_ops.cpu_suspend) for both cpuidle and
>> +        * suspend-to-RAM. Also, PSCI v0.1 needs the specific 'power_state'
>> +        * parameter for the suspend mode. In order to enter suspend mode,
>> +        * Exynos5433 calls the 'psci_ops.cpu_suspend' with '0x3010000'
>> +        * power_state parameter.
>> +        *
>> +        * '0x3010000' means that both cluster and system are going to enter
>> +        * the power-down state as following:
>> +        * - [25:24] 0x3 : Indicate the cluster and system.
>> +        * - [16]    0x1 : Indicate power-down state.
> 
> Define them, it will be more readable (name of define given just as an example):
> 
> EXYNOS5433_PCSI_SUSPEND_SYSTEM (0x3 << 24)
> (or even split per system and cluser and use BIT() if this is real meaning)
> and probably reuse existing S5P_CENTRAL_LOWPWR_CFG

OK. I'll define it as the constant.

> 
>> +        */
>> +       return psci_ops.cpu_suspend(0x3010000, __pa_symbol(cpu_resume));
>> +}
>> +
>> +static int exynos5433_pm_suspend_enter(suspend_state_t state)
>> +{
>> +       if (!sysram_ns_base_addr)
>> +               return -EINVAL;
>> +
>> +       __raw_writel(virt_to_phys(cpu_resume), sysram_ns_base_addr + 0x8);
>> +       __raw_writel(EXYNOS_SLEEP_MAGIC, sysram_ns_base_addr + 0xc);
> 
> Document them in Documentation/arm/Samsung/Bootloader-interface.txt.

OK.

> 
> Best regards,
> Krzysztof
> 
>> +
>> +       return cpu_suspend(0, exynos5433_pm_suspend);
>> +}
>> +
>> +const struct exynos_pm_data exynos5433_pm_data = {
>> +       .enter          = exynos5433_pm_suspend_enter,
>> +};
>> +
>>  static const struct of_device_id exynos_pm_of_device_ids[] = {
>> +       {
>> +               .compatible = "samsung,exynos5433-pmu",
>> +               .data = exynos_pm_data_arm_ptr(exynos5433_pm_data),
>> +       },
>>         { /*sentinel*/ },
>>  };
>>
>> --
>> 1.9.1
>>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 
> 
> 


-- 
Best Regards,
Chanwoo Choi
Samsung Electronics

[PATCH 6/9] arm64: dts: exynos: Add iRAM device-tree node for Exynos5433

[Chanwoo Choi]

This patch adds the iRAM device-tree node of Exynos5433 which
defines the memory map of iRAM as following and it is used for suspend.
- address: 0x0202_0000 ~ 0x3000_0000

Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
 arch/arm64/boot/dts/exynos/exynos5433.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 62f276970174..77f4321b247c 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -262,6 +262,20 @@
 			interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
 		};
 
+		sysram@02020000 {
+			compatible = "mmio-sram";
+			reg = <0x02020000 0x5c000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x02020000 0x5c000>;
+			status = "okay";
+
+			smp-sysram@5b000 {
+				compatible = "samsung,exynos4210-sysram-ns";
+				reg = <0x5b000 0x1000>;
+			};
+		};
+
 		chipid@10000000 {
 			compatible = "samsung,exynos4210-chipid";
 			reg = <0x10000000 0x100>;
-- 
1.9.1

Re: [PATCH 6/9] arm64: dts: exynos: Add iRAM device-tree node for Exynos5433

[Krzysztof Kozlowski]

On Tue, Jan 9, 2018 at 8:59 AM, Chanwoo Choi <cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> wrote:
> This patch adds the iRAM device-tree node of Exynos5433 which
> defines the memory map of iRAM as following and it is used for suspend.
> - address: 0x0202_0000 ~ 0x3000_0000
>
> Signed-off-by: Jonghwa Lee <jonghwa3.lee-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> Signed-off-by: Chanwoo Choi <cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> ---
>  arch/arm64/boot/dts/exynos/exynos5433.dtsi | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> index 62f276970174..77f4321b247c 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> @@ -262,6 +262,20 @@
>                         interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
>                 };
>
> +               sysram@02020000 {

Remove leading 0.

Best regards,
Krzysztof

> +                       compatible = "mmio-sram";
> +                       reg = <0x02020000 0x5c000>;
> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +                       ranges = <0 0x02020000 0x5c000>;
> +                       status = "okay";
> +
> +                       smp-sysram@5b000 {
> +                               compatible = "samsung,exynos4210-sysram-ns";
> +                               reg = <0x5b000 0x1000>;
> +                       };
> +               };
> +
>                 chipid@10000000 {
>                         compatible = "samsung,exynos4210-chipid";
>                         reg = <0x10000000 0x100>;
> --
> 1.9.1
>
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[PATCH 7/9] arm64: dts: exynos: Use power key as a wakeup source on TM2/TM2E board

[Chanwoo Choi]

This patch uses the power-key as a wakeup source from suspend/freeze state.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
 arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
index a77462da4a36..26de0add1254 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
@@ -60,6 +60,7 @@
 			linux,code = <KEY_POWER>;
 			label = "power key";
 			debounce-interval = <10>;
+			wakeup-source;
 		};
 
 		volume-up-key {
-- 
1.9.1

[PATCH 8/9] arm64: dts: exynos: Add cpu_suspend property of PSCI for exynos5433

[Chanwoo Choi]

The ARM64 Exynos5433 supports PSCI(Power State Coordinate Interface)[1] v0.1.
When PSCI v0.1 is used, the device-tree should contain the specific entry
point such as cpu_suspend. This patch adds the 'cpu_suspend' property
in order to support the cpuidle and suspend execution on Exynos5433 SoC.

The 'cpu_suspend' of psci is originally intended for use in idle subsystems.
Although the cpuidle and suspend-to-RAM framework have separate routine
in order to enter the low-power state, PSCI v0.1 doesn't support
the separate the entry point such as 'system_suspend' on PSCI v1.0.

So, the 'cpu_suspend' of PSCI v0.1 on Exynos5433 is used for both
cpuidle and suspend-to-RAM.

[1] http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf

Signed-off-by: Chanwoo Choi <cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
 arch/arm64/boot/dts/exynos/exynos5433.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 77f4321b247c..0d99ded21202 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -227,6 +227,7 @@
 	psci {
 		compatible = "arm,psci";
 		method = "smc";
+		cpu_suspend = <0xc4000001>;
 		cpu_off = <0x84000002>;
 		cpu_on = <0xC4000003>;
 	};
-- 
1.9.1

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[PATCH 9/9] arm64: dts: exynos: Add cpu topology information for Exynos5433 SoC

[Chanwoo Choi]

This patch adds the 'cpu-map' for the cpu topology information
of Exynos5433 which has the following two clusters.
- cluster0 contains the four LITTLE cores (cpu0-3).
- cluster1 contains the four big cores (cpu4-7).

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
 arch/arm64/boot/dts/exynos/exynos5433.dtsi | 32 ++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 0d99ded21202..ea54022f4f44 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -27,6 +27,38 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+				core1 {
+					cpu = <&cpu1>;
+				};
+				core2 {
+					cpu = <&cpu2>;
+				};
+				core3 {
+					cpu = <&cpu3>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&cpu4>;
+				};
+				core1 {
+					cpu = <&cpu5>;
+				};
+				core2 {
+					cpu = <&cpu6>;
+				};
+				core3 {
+					cpu = <&cpu7>;
+				};
+			};
+		};
+
 		cpu0: cpu@100 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53", "arm,armv8";
-- 
1.9.1

Re: [RFC PATCH 0/9] soc: samsung: Add support of suspend-to-RAM on Exynos5433

[Krzysztof Kozlowski]

On Tue, Jan 9, 2018 at 8:58 AM, Chanwoo Choi <cw00.choi@samsung.com> wrote:
> In the mainline, there is no case to support the suspend-to-RAM for Samsung
> Exynos SoC. This patchset support the suspend-to-RAM for 64bit Exynos SoC.
>
> For 32bit, arch/arm/mach-exynos/* directoy contains the suspend-related
> codes such as suspend.c/exynos.c. But, 64bit Exynos should contain
> the suspend-related codes in the drivers/soc/samsung/*. So, this patchset
> develop the patch4/5 for drivers/soc/samsung/exynos-pm.c. to support suspend
> 64bit Exynos SoC.
>
> But, I'm not sure what is proper approach for both 32/64bit Exynos.
> - Approach1 : Split out the supend-related codes between 32/64bit.
>   : arch/arm/mach-exynos/* contains the suspend-related codes for 32bit.
>   : drivers/soc/samsung/* contains the suspend-related codes for 64bit.
> - Approach2 : Consolidate the all suspend-related codes to drivers/soc/samsung/.

I prefer approach #2 - consolidate the code... unless this creates
some unmaintainable monster :)

Best regards,
Krzysztof

>
> Please let us know your opinion.
>
> The patch1/2/3 and 6/7/8/9 is just general patch. So, I add 'RFC' prefix to
> only cover-letter, patch4/5. If you want to add the 'RFC' prefix to all
> patches, I'll add 'RFC' prefix on v2.
>
> Based on:
> - git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git (branch: for-next)
>
> Need to discuss patch4/5:
> - patch4: soc: samsung: Add generic power-management driver for Exynos
> - patch5: soc: samsung: pm: Add support for suspend-to-ram of Exynos5433
>
> [Remaining Issues]
> - The hang-out happen when disabling the MMC clocks on dw_mmc.c.
>   I reported to Jaehoon Chung. He is checking this issue. To test the
>   suspend-to-ram temporarily, you need to add CLK_IS_CRITICAL flag to
>   'aclk_mmc2/aclk_mmc0/sclk_mmc2/sclk_mmc0'.
> - I enabled the at least kernel configuration in order to test
>   the suspend-to-RAM. So, I need to test it more time with DRM/Multimedia
>   and other. But, the suspend-to-RAM of cpu is successful.
> - Exynos5433 SoC has two EXYNOS5433_EINT_WAKEUP_MASKx registers. The
>   pinctr-exynos.c need to handle the extra EINT_WAKEUP_MASKx for Exynos5433.
>   The suspend-to-ram test is failed on first time and then next tryout is ok.
>   I'm developing it.
>
> Chanwoo Choi (9):
>   clk: samsung: exynos5433: Add clock flag to support suspend-to-ram
>   soc: samsung: pmu: Add powerup_conf callback
>   soc: samsung: pmu: Add the PMU data of exynos5433 to support low-power state
>   soc: samsung: Add generic power-management driver for Exynos
>   soc: samsung: pm: Add support for suspend-to-ram of Exynos5433
>   arm64: dts: exynos: Add iRAM device-tree node for Exynos5433
>   arm64: dts: exynos: Use power key as a wakeup source on TM2/TM2E board
>   arm64: dts: exynos: Add cpu_suspend property of PSCI for exynos5433
>   arm64: dts: exynos: Add cpu topology information for Exynos5433 SoC
>
>  arch/arm/mach-exynos/common.h                      |   3 -
>  arch/arm/mach-exynos/exynos.c                      |  23 +-
>  .../boot/dts/exynos/exynos5433-tm2-common.dtsi     |   1 +
>  arch/arm64/boot/dts/exynos/exynos5433.dtsi         |  47 ++++
>  drivers/clk/samsung/clk-exynos5433.c               |  22 +-
>  drivers/soc/samsung/Makefile                       |   5 +-
>  drivers/soc/samsung/exynos-pm.c                    | 214 +++++++++++++++
>  drivers/soc/samsung/exynos-pmu.c                   |   9 +
>  drivers/soc/samsung/exynos-pmu.h                   |   3 +
>  drivers/soc/samsung/exynos5433-pmu.c               | 286 +++++++++++++++++++++
>  include/linux/soc/samsung/exynos-pm.h              |  21 ++
>  include/linux/soc/samsung/exynos-pmu.h             |   1 +
>  include/linux/soc/samsung/exynos-regs-pmu.h        | 148 +++++++++++
>  13 files changed, 745 insertions(+), 38 deletions(-)
>  create mode 100644 drivers/soc/samsung/exynos-pm.c
>  create mode 100644 drivers/soc/samsung/exynos5433-pmu.c
>  create mode 100644 include/linux/soc/samsung/exynos-pm.h
>
> --
> 1.9.1
>

Re: [RFC PATCH 0/9] soc: samsung: Add support of suspend-to-RAM on Exynos5433

[Chanwoo Choi]

On 2018년 01월 09일 20:56, Krzysztof Kozlowski wrote:
> On Tue, Jan 9, 2018 at 8:58 AM, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>> In the mainline, there is no case to support the suspend-to-RAM for Samsung
>> Exynos SoC. This patchset support the suspend-to-RAM for 64bit Exynos SoC.
>>
>> For 32bit, arch/arm/mach-exynos/* directoy contains the suspend-related
>> codes such as suspend.c/exynos.c. But, 64bit Exynos should contain
>> the suspend-related codes in the drivers/soc/samsung/*. So, this patchset
>> develop the patch4/5 for drivers/soc/samsung/exynos-pm.c. to support suspend
>> 64bit Exynos SoC.
>>
>> But, I'm not sure what is proper approach for both 32/64bit Exynos.
>> - Approach1 : Split out the supend-related codes between 32/64bit.
>>   : arch/arm/mach-exynos/* contains the suspend-related codes for 32bit.
>>   : drivers/soc/samsung/* contains the suspend-related codes for 64bit.
>> - Approach2 : Consolidate the all suspend-related codes to drivers/soc/samsung/.
> 
> I prefer approach #2 - consolidate the code... unless this creates
> some unmaintainable monster :)

I'll try to consolidate code.

[snip]

-- 
Best Regards,
Chanwoo Choi
Samsung Electronics