* [PATCH 1/3] dt-bindings: mfd: ti,j721e-system-controller: Add clock property
2022-05-27 8:35 [PATCH 0/3] Enable RPi header on j721e sk Rahul T R
@ 2022-05-27 8:35 ` Rahul T R
2022-05-29 14:14 ` Krzysztof Kozlowski
2022-05-27 8:35 ` [PATCH 2/3] arm64: dts: ti: k3-j721e-*: Add dts nodes for EHRPWMs Rahul T R
2022-05-27 8:35 ` [PATCH 3/3] arm64: dts: ti: k3-j721e-sk: Add pinmux for RPi Header Rahul T R
2 siblings, 1 reply; 6+ messages in thread
From: Rahul T R @ 2022-05-27 8:35 UTC (permalink / raw)
To: robh+dt, nm, vigneshr, kishon, krzysztof.kozlowski+dt
Cc: lee.jones, rogerq, devicetree, kristo, linux-arm-kernel,
linux-kernel, s-anna, Rahul T R
Add a pattern property for clock, also update the example with
a clock node
Signed-off-by: Rahul T R <r-ravikumar@ti.com>
---
.../bindings/mfd/ti,j721e-system-controller.yaml | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
index fa86691ebf16..e774a7f0bb08 100644
--- a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
+++ b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
@@ -48,6 +48,12 @@ patternProperties:
description:
This is the SERDES lane control mux.
+ "^clock@[0-9a-f]+$":
+ type: object
+ $ref: ../clock/ti,am654-ehrpwm-tbclk.yaml#
+ description:
+ This is TI syscon gate clk.
+
required:
- compatible
- reg
@@ -79,5 +85,11 @@ examples:
<0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
/* SERDES4 lane0/1/2/3 select */
};
+
+ ehrpwm_tbclk: clock@4140 {
+ compatible = "ti,am654-ehrpwm-tbclk", "syscon";
+ reg = <0x4140 0x18>;
+ #clock-cells = <1>;
+ };
};
...
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH 1/3] dt-bindings: mfd: ti,j721e-system-controller: Add clock property
2022-05-27 8:35 ` [PATCH 1/3] dt-bindings: mfd: ti,j721e-system-controller: Add clock property Rahul T R
@ 2022-05-29 14:14 ` Krzysztof Kozlowski
2022-05-30 7:33 ` Rahul T R
0 siblings, 1 reply; 6+ messages in thread
From: Krzysztof Kozlowski @ 2022-05-29 14:14 UTC (permalink / raw)
To: Rahul T R, robh+dt, nm, vigneshr, kishon, krzysztof.kozlowski+dt
Cc: lee.jones, rogerq, devicetree, kristo, linux-arm-kernel,
linux-kernel, s-anna
On 27/05/2022 10:35, Rahul T R wrote:
> Add a pattern property for clock, also update the example with
> a clock node
>
> Signed-off-by: Rahul T R <r-ravikumar@ti.com>
> ---
> .../bindings/mfd/ti,j721e-system-controller.yaml | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
> index fa86691ebf16..e774a7f0bb08 100644
> --- a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
> +++ b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
> @@ -48,6 +48,12 @@ patternProperties:
> description:
> This is the SERDES lane control mux.
>
> + "^clock@[0-9a-f]+$":
> + type: object
> + $ref: ../clock/ti,am654-ehrpwm-tbclk.yaml#
Full path please, so /schemas/clock/.......
> + description:
> + This is TI syscon gate clk.
Don't use "This is". Just describe it without need of full sentence.
"syscon gate clock" is a bit unspecific and actually looks like you
describe "clocks" property...
> +
> required:
> - compatible
> - reg
> @@ -79,5 +85,11 @@ examples:
> <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
> /* SERDES4 lane0/1/2/3 select */
> };
> +
> + ehrpwm_tbclk: clock@4140 {
No need for label.
> + compatible = "ti,am654-ehrpwm-tbclk", "syscon";
Messed up indentation.
> + reg = <0x4140 0x18>;
> + #clock-cells = <1>;
> + };
> };
> ...
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH 1/3] dt-bindings: mfd: ti,j721e-system-controller: Add clock property
2022-05-29 14:14 ` Krzysztof Kozlowski
@ 2022-05-30 7:33 ` Rahul T R
0 siblings, 0 replies; 6+ messages in thread
From: Rahul T R @ 2022-05-30 7:33 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: robh+dt, nm, vigneshr, kishon, krzysztof.kozlowski+dt, lee.jones,
rogerq, devicetree, kristo, linux-arm-kernel, linux-kernel,
s-anna
On 16:14-20220529, Krzysztof Kozlowski wrote:
> On 27/05/2022 10:35, Rahul T R wrote:
> > Add a pattern property for clock, also update the example with
> > a clock node
> >
> > Signed-off-by: Rahul T R <r-ravikumar@ti.com>
> > ---
> > .../bindings/mfd/ti,j721e-system-controller.yaml | 12 ++++++++++++
> > 1 file changed, 12 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
> > index fa86691ebf16..e774a7f0bb08 100644
> > --- a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
> > +++ b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
> > @@ -48,6 +48,12 @@ patternProperties:
> > description:
> > This is the SERDES lane control mux.
> >
> > + "^clock@[0-9a-f]+$":
> > + type: object
> > + $ref: ../clock/ti,am654-ehrpwm-tbclk.yaml#
Thanks Krzysztof,
Will address the review comments and send a v2
of this
Regards
Rahul T R
>
> Full path please, so /schemas/clock/.......
>
> > + description:
> > + This is TI syscon gate clk.
>
> Don't use "This is". Just describe it without need of full sentence.
> "syscon gate clock" is a bit unspecific and actually looks like you
> describe "clocks" property...
>
> > +
> > required:
> > - compatible
> > - reg
> > @@ -79,5 +85,11 @@ examples:
> > <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
> > /* SERDES4 lane0/1/2/3 select */
> > };
> > +
> > + ehrpwm_tbclk: clock@4140 {
>
> No need for label.
>
> > + compatible = "ti,am654-ehrpwm-tbclk", "syscon";
>
> Messed up indentation.
>
> > + reg = <0x4140 0x18>;
> > + #clock-cells = <1>;
> > + };
> > };
> > ...
>
>
> Best regards,
> Krzysztof
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/3] arm64: dts: ti: k3-j721e-*: Add dts nodes for EHRPWMs
2022-05-27 8:35 [PATCH 0/3] Enable RPi header on j721e sk Rahul T R
2022-05-27 8:35 ` [PATCH 1/3] dt-bindings: mfd: ti,j721e-system-controller: Add clock property Rahul T R
@ 2022-05-27 8:35 ` Rahul T R
2022-05-27 8:35 ` [PATCH 3/3] arm64: dts: ti: k3-j721e-sk: Add pinmux for RPi Header Rahul T R
2 siblings, 0 replies; 6+ messages in thread
From: Rahul T R @ 2022-05-27 8:35 UTC (permalink / raw)
To: robh+dt, nm, vigneshr, kishon, krzysztof.kozlowski+dt
Cc: lee.jones, rogerq, devicetree, kristo, linux-arm-kernel,
linux-kernel, s-anna, Vijay Pothukuchi, Rahul T R
From: Vijay Pothukuchi <vijayp@ti.com>
Add dts nodes for 6 EHRPWM instances on SoC
Signed-off-by: Vijay Pothukuchi <vijayp@ti.com>
Signed-off-by: Rahul T R <r-ravikumar@ti.com>
---
.../dts/ti/k3-j721e-common-proc-board.dts | 24 +++++++
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 62 ++++++++++++++++++-
arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 24 +++++++
3 files changed, 109 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index 2bc26a296496..f7d02fa4d6fc 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -995,3 +995,27 @@
&main_mcan13 {
status = "disabled";
};
+
+&main_ehrpwm0 {
+ status = "disabled";
+};
+
+&main_ehrpwm1 {
+ status = "disabled";
+};
+
+&main_ehrpwm2 {
+ status = "disabled";
+};
+
+&main_ehrpwm3 {
+ status = "disabled";
+};
+
+&main_ehrpwm4 {
+ status = "disabled";
+};
+
+&main_ehrpwm5 {
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 43b6cf5791ee..3ae3d1cc6570 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -66,7 +66,67 @@
#mux-control-cells = <1>;
mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */
<0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */
- };
+ };
+
+ ehrpwm_tbclk: clock@4140 {
+ compatible = "ti,am654-ehrpwm-tbclk", "syscon";
+ reg = <0x4140 0x18>;
+ #clock-cells = <1>;
+ };
+ };
+
+ main_ehrpwm0: pwm@3000000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x3000000 0x0 0x100>;
+ power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 0>, <&k3_clks 83 0>;
+ clock-names = "tbclk", "fck";
+ };
+
+ main_ehrpwm1: pwm@3010000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x3010000 0x0 0x100>;
+ power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 1>, <&k3_clks 84 0>;
+ clock-names = "tbclk", "fck";
+ };
+
+ main_ehrpwm2: pwm@3020000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x3020000 0x0 0x100>;
+ power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 2>, <&k3_clks 85 0>;
+ clock-names = "tbclk", "fck";
+ };
+
+ main_ehrpwm3: pwm@3030000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x3030000 0x0 0x100>;
+ power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 3>, <&k3_clks 86 0>;
+ clock-names = "tbclk", "fck";
+ };
+
+ main_ehrpwm4: pwm@3040000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x3040000 0x0 0x100>;
+ power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 4>, <&k3_clks 87 0>;
+ clock-names = "tbclk", "fck";
+ };
+
+ main_ehrpwm5: pwm@3050000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x3050000 0x0 0x100>;
+ power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 5>, <&k3_clks 88 0>;
+ clock-names = "tbclk", "fck";
};
gic500: interrupt-controller@1800000 {
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
index 80358cba6954..98a55778f3fe 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
@@ -1129,3 +1129,27 @@
memory-region = <&c71_0_dma_memory_region>,
<&c71_0_memory_region>;
};
+
+&main_ehrpwm0 {
+ status = "disabled";
+};
+
+&main_ehrpwm1 {
+ status = "disabled";
+};
+
+&main_ehrpwm2 {
+ status = "disabled";
+};
+
+&main_ehrpwm3 {
+ status = "disabled";
+};
+
+&main_ehrpwm4 {
+ status = "disabled";
+};
+
+&main_ehrpwm5 {
+ status = "disabled";
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 3/3] arm64: dts: ti: k3-j721e-sk: Add pinmux for RPi Header
2022-05-27 8:35 [PATCH 0/3] Enable RPi header on j721e sk Rahul T R
2022-05-27 8:35 ` [PATCH 1/3] dt-bindings: mfd: ti,j721e-system-controller: Add clock property Rahul T R
2022-05-27 8:35 ` [PATCH 2/3] arm64: dts: ti: k3-j721e-*: Add dts nodes for EHRPWMs Rahul T R
@ 2022-05-27 8:35 ` Rahul T R
2 siblings, 0 replies; 6+ messages in thread
From: Rahul T R @ 2022-05-27 8:35 UTC (permalink / raw)
To: robh+dt, nm, vigneshr, kishon, krzysztof.kozlowski+dt
Cc: lee.jones, rogerq, devicetree, kristo, linux-arm-kernel,
linux-kernel, s-anna, Sinthu Raja, Rahul T R
From: Sinthu Raja <sinthu.raja@ti.com>
Add pinmux required to bring out
i2c5, ehrpwm 2 and 3 and gpios on
40 pin RPi header on sk board
Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
Signed-off-by: Rahul T R <r-ravikumar@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 89 ++++++++++++++++++++++----
1 file changed, 78 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
index 98a55778f3fe..b913b18ae133 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
@@ -400,6 +400,57 @@
J721E_IOPAD(0x124, PIN_INPUT, 7) /* (Y24) PRG0_PRU1_GPO9.GPIO0_72 */
>;
};
+
+ main_i2c5_pins_default: main-i2c5-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */
+ J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */
+ >;
+ };
+
+ rpi_header_gpio0_pins_default: rpi-header-gpio0-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x01c, PIN_INPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */
+ J721E_IOPAD(0x120, PIN_INPUT, 7) /* (AA28) PRG0_PRU1_GPO8.GPIO0_71 */
+ J721E_IOPAD(0x14c, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */
+ J721E_IOPAD(0x02c, PIN_INPUT, 7) /* (AD21) PRG1_PRU0_GPO10.GPIO0_11 */
+ J721E_IOPAD(0x198, PIN_INPUT, 7) /* (V25) RGMII6_TD1.GPIO0_101 */
+ J721E_IOPAD(0x1b0, PIN_INPUT, 7) /* (W24) RGMII6_RD1.GPIO0_107 */
+ J721E_IOPAD(0x1a0, PIN_INPUT, 7) /* (W29) RGMII6_TXC.GPIO0_103 */
+ J721E_IOPAD(0x008, PIN_INPUT, 7) /* (AG22) PRG1_PRU0_GPO1.GPIO0_2 */
+ J721E_IOPAD(0x1d0, PIN_INPUT, 7) /* (AA3) SPI0_D1.GPIO0_115 */
+ J721E_IOPAD(0x11c, PIN_INPUT, 7) /* (AA24) PRG0_PRU1_GPO7.GPIO0_70 */
+ J721E_IOPAD(0x148, PIN_INPUT, 7) /* (AA26) PRG0_PRU1_GPO18.GPIO0_81 */
+ J721E_IOPAD(0x004, PIN_INPUT, 7) /* (AC23) PRG1_PRU0_GPO0.GPIO0_1 */
+ J721E_IOPAD(0x014, PIN_INPUT, 7) /* (AH23) PRG1_PRU0_GPO4.GPIO0_5 */
+ J721E_IOPAD(0x020, PIN_INPUT, 7) /* (AE20) PRG1_PRU0_GPO7.GPIO0_8 */
+ J721E_IOPAD(0x19c, PIN_INPUT, 7) /* (W27) RGMII6_TD0.GPIO0_102 */
+ J721E_IOPAD(0x1b4, PIN_INPUT, 7) /* (W25) RGMII6_RD0.GPIO0_108 */
+ J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */
+ J721E_IOPAD(0x00c, PIN_INPUT, 7) /* (AF22) PRG1_PRU0_GPO2.GPIO0_3 */
+ J721E_IOPAD(0x010, PIN_INPUT, 7) /* (AJ23) PRG1_PRU0_GPO3.GPIO0_4 */
+ >;
+ };
+
+ rpi_header_gpio1_pins_default: rpi-header-gpio1-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x234, PIN_INPUT, 7) /* (U3) EXT_REFCLK1.GPIO1_12 */
+ >;
+ };
+
+ rpi_header_ehrpwm2_pins_default: rpi-header-ehrpwm2-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x178, PIN_INPUT, 6) /* (U27) RGMII5_RD3.EHRPWM2_A */
+ J721E_IOPAD(0x17c, PIN_INPUT, 6) /* (U24) RGMII5_RD2.EHRPWM2_B */
+ >;
+ };
+
+ rpi_header_ehrpwm3_pins_default: rpi-header-ehrpwm3-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x18c, PIN_INPUT, 6) /* (V23) RGMII6_RX_CTL.EHRPWM3_A */
+ J721E_IOPAD(0x190, PIN_INPUT, 6) /* (W23) RGMII6_TD3.EHRPWM3_B */
+ >;
+ };
};
&wkup_pmx0 {
@@ -631,11 +682,6 @@
status = "disabled";
};
-&main_i2c5 {
- /* Brought out on RPi Header */
- status = "disabled";
-};
-
&main_i2c6 {
/* Unused */
status = "disabled";
@@ -1138,18 +1184,39 @@
status = "disabled";
};
-&main_ehrpwm2 {
+&main_ehrpwm4 {
status = "disabled";
};
-&main_ehrpwm3 {
+&main_ehrpwm5 {
status = "disabled";
};
-&main_ehrpwm4 {
- status = "disabled";
+&main_gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rpi_header_gpio0_pins_default>;
};
-&main_ehrpwm5 {
- status = "disabled";
+&main_gpio1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rpi_header_gpio1_pins_default>;
+};
+
+&main_i2c5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c5_pins_default>;
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&main_ehrpwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rpi_header_ehrpwm2_pins_default>;
+ status = "okay";
+};
+
+&main_ehrpwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rpi_header_ehrpwm3_pins_default>;
+ status = "okay";
};
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread