* [PATCH 1/5] ARM: tegra: define DT bindings for and instantiate timer
@ 2012-09-19 21:31 Stephen Warren
[not found] ` <1348090279-22631-1-git-send-email-swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
0 siblings, 1 reply; 6+ messages in thread
From: Stephen Warren @ 2012-09-19 21:31 UTC (permalink / raw)
To: Stephen Warren
Cc: Rob Herring, Grant Likely, linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, Stephen Warren
From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
The Tegra timer provides a number of 29-bit timer channels, a single
32-bit free running counter, and in the Tegra30 variant, 5 watchdog modules.
The first two channels may also trigger a legacy watchdog reset.
Define a DT binding for this HW module, and add the module into the Tegra
device tree files.
Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
.../bindings/timer/nvidia,tegra20-timer.txt | 21 ++++++++++++++++++
.../bindings/timer/nvidia,tegra30-timer.txt | 23 ++++++++++++++++++++
arch/arm/boot/dts/tegra20.dtsi | 9 +++++++
arch/arm/boot/dts/tegra30.dtsi | 11 +++++++++
4 files changed, 64 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt
create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt
diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt b/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt
new file mode 100644
index 0000000..e019fdc
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt
@@ -0,0 +1,21 @@
+NVIDIA Tegra20 timer
+
+The Tegra20 timer provides four 29-bit timer channels and a single 32-bit free
+running counter. The first two channels may also trigger a watchdog reset.
+
+Required properties:
+
+- compatible : should be "nvidia,tegra20-timer".
+- reg : Specifies base physical address and size of the registers.
+- interrupts : A list of 4 interrupts; one per timer channel.
+
+Example:
+
+timer {
+ compatible = "nvidia,tegra20-timer";
+ reg = <0x60005000 0x60>;
+ interrupts = <0 0 0x04
+ 0 1 0x04
+ 0 41 0x04
+ 0 42 0x04>;
+};
diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt b/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt
new file mode 100644
index 0000000..906109d
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt
@@ -0,0 +1,23 @@
+NVIDIA Tegra30 timer
+
+The Tegra30 timer provides ten 29-bit timer channels, a single 32-bit free
+running counter, and 5 watchdog modules. The first two channels may also
+trigger a legacy watchdog reset.
+
+Required properties:
+
+- compatible : should be "nvidia,tegra30-timer", "nvidia,tegra20-timer".
+- reg : Specifies base physical address and size of the registers.
+- interrupts : A list of 6 interrupts; one per each of timer channels 1
+ through 5, and one for the shared interrupt for the remaining channels.
+
+timer {
+ compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
+ reg = <0x60005000 0x400>;
+ interrupts = <0 0 0x04
+ 0 1 0x04
+ 0 41 0x04
+ 0 42 0x04
+ 0 121 0x04
+ 0 122 0x04>;
+};
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 405d167..0fadf4d 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -12,6 +12,15 @@
#interrupt-cells = <3>;
};
+ timer@60005000 {
+ compatible = "nvidia,tegra20-timer";
+ reg = <0x60005000 0x60>;
+ interrupts = <0 0 0x04
+ 0 1 0x04
+ 0 41 0x04
+ 0 42 0x04>;
+ };
+
apbdma: dma {
compatible = "nvidia,tegra20-apbdma";
reg = <0x6000a000 0x1200>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 3e4334d..d6f8e4c 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -12,6 +12,17 @@
#interrupt-cells = <3>;
};
+ timer@60005000 {
+ compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
+ reg = <0x60005000 0x400>;
+ interrupts = <0 0 0x04
+ 0 1 0x04
+ 0 41 0x04
+ 0 42 0x04
+ 0 121 0x04
+ 0 122 0x04>;
+ };
+
apbdma: dma {
compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
reg = <0x6000a000 0x1400>;
--
1.7.0.4
^ permalink raw reply related [flat|nested] 6+ messages in thread[parent not found: <1348090279-22631-1-git-send-email-swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>]
* [PATCH 2/5] ARM: tegra: define DT bindings for and instantiate RTC [not found] ` <1348090279-22631-1-git-send-email-swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> @ 2012-09-19 21:31 ` Stephen Warren 2012-09-19 21:31 ` [PATCH 3/5] ARM: tegra: add TWD to device tree Stephen Warren ` (2 subsequent siblings) 3 siblings, 0 replies; 6+ messages in thread From: Stephen Warren @ 2012-09-19 21:31 UTC (permalink / raw) To: Stephen Warren Cc: Rob Herring, Grant Likely, linux-tegra-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, Stephen Warren From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> The Tegra RTC maintains seconds and milliseconds counters, and five alarm registers. The alarms and other interrupts may wake the system from low-power state. Define a DT binding for this HW module, and add the module into the Tegra device tree files. Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> --- .../devicetree/bindings/rtc/nvidia,tegra20-rtc.txt | 19 +++++++++++++++++++ arch/arm/boot/dts/tegra20.dtsi | 6 ++++++ arch/arm/boot/dts/tegra30.dtsi | 6 ++++++ 3 files changed, 31 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt diff --git a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt new file mode 100644 index 0000000..93f45e9 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt @@ -0,0 +1,19 @@ +NVIDIA Tegra20 real-time clock + +The Tegra RTC maintains seconds and milliseconds counters, and five alarm +registers. The alarms and other interrupts may wake the system from low-power +state. + +Required properties: + +- compatible : should be "nvidia,tegra20-rtc". +- reg : Specifies base physical address and size of the registers. +- interrupts : A single interrupt specifier. + +Example: + +timer { + compatible = "nvidia,tegra20-rtc"; + reg = <0x7000e000 0x100>; + interrupts = <0 2 0x04>; +}; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 0fadf4d..9d22238 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -138,6 +138,12 @@ #pwm-cells = <2>; }; + rtc { + compatible = "nvidia,tegra20-rtc"; + reg = <0x7000e000 0x100>; + interrupts = <0 2 0x04>; + }; + i2c@7000c000 { compatible = "nvidia,tegra20-i2c"; reg = <0x7000c000 0x100>; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index d6f8e4c..ffb035a 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -134,6 +134,12 @@ #pwm-cells = <2>; }; + rtc { + compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; + reg = <0x7000e000 0x100>; + interrupts = <0 2 0x04>; + }; + i2c@7000c000 { compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; reg = <0x7000c000 0x100>; -- 1.7.0.4 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 3/5] ARM: tegra: add TWD to device tree [not found] ` <1348090279-22631-1-git-send-email-swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> 2012-09-19 21:31 ` [PATCH 2/5] ARM: tegra: define DT bindings for and instantiate RTC Stephen Warren @ 2012-09-19 21:31 ` Stephen Warren 2012-09-19 21:31 ` [PATCH 4/5] ARM: tegra: enhance timer.c to get information from " Stephen Warren 2012-09-19 21:31 ` [PATCH 5/5] ARM: tegra: select SPARSE_IRQ Stephen Warren 3 siblings, 0 replies; 6+ messages in thread From: Stephen Warren @ 2012-09-19 21:31 UTC (permalink / raw) To: Stephen Warren Cc: Rob Herring, Grant Likely, linux-tegra-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, Stephen Warren From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> This will allow timer.c to use twd_local_timer_of_register(), and hence not need to hard-code the TWD address or IRQ. Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> --- arch/arm/boot/dts/tegra20.dtsi | 6 ++++++ arch/arm/boot/dts/tegra30.dtsi | 6 ++++++ 2 files changed, 12 insertions(+), 0 deletions(-) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 9d22238..723fd43 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -4,6 +4,12 @@ compatible = "nvidia,tegra20"; interrupt-parent = <&intc>; + timer@50004600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x50040600 0x20>; + interrupts = <1 13 0x304>; + }; + intc: interrupt-controller { compatible = "arm,cortex-a9-gic"; reg = <0x50041000 0x1000 diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index ffb035a..15e61b6 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -4,6 +4,12 @@ compatible = "nvidia,tegra30"; interrupt-parent = <&intc>; + timer@50004600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x50040600 0x20>; + interrupts = <1 13 0xf04>; + }; + intc: interrupt-controller { compatible = "arm,cortex-a9-gic"; reg = <0x50041000 0x1000 -- 1.7.0.4 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 4/5] ARM: tegra: enhance timer.c to get information from device tree [not found] ` <1348090279-22631-1-git-send-email-swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> 2012-09-19 21:31 ` [PATCH 2/5] ARM: tegra: define DT bindings for and instantiate RTC Stephen Warren 2012-09-19 21:31 ` [PATCH 3/5] ARM: tegra: add TWD to device tree Stephen Warren @ 2012-09-19 21:31 ` Stephen Warren 2012-09-19 21:31 ` [PATCH 5/5] ARM: tegra: select SPARSE_IRQ Stephen Warren 3 siblings, 0 replies; 6+ messages in thread From: Stephen Warren @ 2012-09-19 21:31 UTC (permalink / raw) To: Stephen Warren Cc: Rob Herring, Grant Likely, linux-tegra-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, Stephen Warren From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> Modify Tegra's timer code to parse the Tegra timer IRQ from device tree, and to instantiate the TWD from device tree, rather than relying on hard- coded values from <mach/irqs.h>. Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> --- arch/arm/mach-tegra/timer.c | 40 +++++++++++++++++++++++----------------- 1 files changed, 23 insertions(+), 17 deletions(-) diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c index eccdce9..ef38c3c 100644 --- a/arch/arm/mach-tegra/timer.c +++ b/arch/arm/mach-tegra/timer.c @@ -26,13 +26,13 @@ #include <linux/clocksource.h> #include <linux/clk.h> #include <linux/io.h> +#include <linux/of_irq.h> #include <asm/mach/time.h> #include <asm/smp_twd.h> #include <asm/sched_clock.h> #include <mach/iomap.h> -#include <mach/irqs.h> #include "board.h" #include "clock.h" @@ -158,30 +158,32 @@ static struct irqaction tegra_timer_irq = { .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_HIGH, .handler = tegra_timer_interrupt, .dev_id = &tegra_clockevent, - .irq = INT_TMR3, }; -#ifdef CONFIG_HAVE_ARM_TWD -static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, - TEGRA_ARM_PERIF_BASE + 0x600, - IRQ_LOCALTIMER); - -static void __init tegra_twd_init(void) -{ - int err = twd_local_timer_register(&twd_local_timer); - if (err) - pr_err("twd_local_timer_register failed %d\n", err); -} -#else -#define tegra_twd_init() do {} while(0) -#endif +static const struct of_device_id timer_match[] __initconst = { + { .compatible = "nvidia,tegra20-timer" }, + {} +}; static void __init tegra_init_timer(void) { + struct device_node *np; struct clk *clk; unsigned long rate; int ret; + np = of_find_matching_node(NULL, timer_match); + if (!np) { + pr_err("Failed to find timer DT node\n"); + BUG(); + } + + tegra_timer_irq.irq = irq_of_parse_and_map(np, 2); + if (tegra_timer_irq.irq <= 0) { + pr_err("Failed to map timer IRQ\n"); + BUG(); + } + clk = clk_get_sys("timer", NULL); if (IS_ERR(clk)) { pr_warn("Unable to get timer clock." @@ -202,6 +204,8 @@ static void __init tegra_init_timer(void) else clk_prepare_enable(clk); + of_node_put(np); + switch (rate) { case 12000000: timer_writel(0x000b, TIMERUS_USEC_CFG); @@ -241,7 +245,9 @@ static void __init tegra_init_timer(void) tegra_clockevent.cpumask = cpu_all_mask; tegra_clockevent.irq = tegra_timer_irq.irq; clockevents_register_device(&tegra_clockevent); - tegra_twd_init(); +#ifdef CONFIG_HAVE_ARM_TWD + twd_local_timer_of_register(); +#endif register_persistent_clock(NULL, tegra_read_persistent_clock); } -- 1.7.0.4 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 5/5] ARM: tegra: select SPARSE_IRQ [not found] ` <1348090279-22631-1-git-send-email-swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> ` (2 preceding siblings ...) 2012-09-19 21:31 ` [PATCH 4/5] ARM: tegra: enhance timer.c to get information from " Stephen Warren @ 2012-09-19 21:31 ` Stephen Warren [not found] ` <1348090279-22631-5-git-send-email-swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> 3 siblings, 1 reply; 6+ messages in thread From: Stephen Warren @ 2012-09-19 21:31 UTC (permalink / raw) To: Stephen Warren Cc: Rob Herring, Grant Likely, linux-tegra-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, Stephen Warren From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> SPARSE_IRQ is required for single zImage support. With this enabled, we can delete <mach/irqs.h>. This requires removing one unnecessary include of that file, and hard-coding the PCIe IRQ into the PCIe driver. This is a hack that will be dealt with as part of converting the PCIe driver into a true DT-supporting driver. Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> --- arch/arm/Kconfig | 1 + arch/arm/mach-tegra/board-dt-tegra20.c | 1 - arch/arm/mach-tegra/include/mach/irqs.h | 182 ------------------------------- arch/arm/mach-tegra/pcie.c | 3 + 4 files changed, 4 insertions(+), 183 deletions(-) delete mode 100644 arch/arm/mach-tegra/include/mach/irqs.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9a87faf..f12088d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -679,6 +679,7 @@ config ARCH_TEGRA select ARCH_HAS_CPUFREQ select USE_OF select COMMON_CLK + select SPARSE_IRQ help This enables support for NVIDIA Tegra based systems (Tegra APX, Tegra 6xx and Tegra 2 series). diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c index c339444..e1cb597 100644 --- a/arch/arm/mach-tegra/board-dt-tegra20.c +++ b/arch/arm/mach-tegra/board-dt-tegra20.c @@ -41,7 +41,6 @@ #include <asm/setup.h> #include <mach/iomap.h> -#include <mach/irqs.h> #include "board.h" #include "clock.h" diff --git a/arch/arm/mach-tegra/include/mach/irqs.h b/arch/arm/mach-tegra/include/mach/irqs.h deleted file mode 100644 index aad1a2c..0000000 --- a/arch/arm/mach-tegra/include/mach/irqs.h +++ /dev/null @@ -1,182 +0,0 @@ -/* - * arch/arm/mach-tegra/include/mach/irqs.h - * - * Copyright (C) 2010 Google, Inc. - * - * Author: - * Colin Cross <ccross-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org> - * Erik Gilling <konkers-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __MACH_TEGRA_IRQS_H -#define __MACH_TEGRA_IRQS_H - -#define INT_GIC_BASE 0 - -#define IRQ_LOCALTIMER 29 - -/* Primary Interrupt Controller */ -#define INT_PRI_BASE (INT_GIC_BASE + 32) -#define INT_TMR1 (INT_PRI_BASE + 0) -#define INT_TMR2 (INT_PRI_BASE + 1) -#define INT_RTC (INT_PRI_BASE + 2) -#define INT_I2S2 (INT_PRI_BASE + 3) -#define INT_SHR_SEM_INBOX_IBF (INT_PRI_BASE + 4) -#define INT_SHR_SEM_INBOX_IBE (INT_PRI_BASE + 5) -#define INT_SHR_SEM_OUTBOX_IBF (INT_PRI_BASE + 6) -#define INT_SHR_SEM_OUTBOX_IBE (INT_PRI_BASE + 7) -#define INT_VDE_UCQ_ERROR (INT_PRI_BASE + 8) -#define INT_VDE_SYNC_TOKEN (INT_PRI_BASE + 9) -#define INT_VDE_BSE_V (INT_PRI_BASE + 10) -#define INT_VDE_BSE_A (INT_PRI_BASE + 11) -#define INT_VDE_SXE (INT_PRI_BASE + 12) -#define INT_I2S1 (INT_PRI_BASE + 13) -#define INT_SDMMC1 (INT_PRI_BASE + 14) -#define INT_SDMMC2 (INT_PRI_BASE + 15) -#define INT_XIO (INT_PRI_BASE + 16) -#define INT_VDE (INT_PRI_BASE + 17) -#define INT_AVP_UCQ (INT_PRI_BASE + 18) -#define INT_SDMMC3 (INT_PRI_BASE + 19) -#define INT_USB (INT_PRI_BASE + 20) -#define INT_USB2 (INT_PRI_BASE + 21) -#define INT_PRI_RES_22 (INT_PRI_BASE + 22) -#define INT_EIDE (INT_PRI_BASE + 23) -#define INT_NANDFLASH (INT_PRI_BASE + 24) -#define INT_VCP (INT_PRI_BASE + 25) -#define INT_APB_DMA (INT_PRI_BASE + 26) -#define INT_AHB_DMA (INT_PRI_BASE + 27) -#define INT_GNT_0 (INT_PRI_BASE + 28) -#define INT_GNT_1 (INT_PRI_BASE + 29) -#define INT_OWR (INT_PRI_BASE + 30) -#define INT_SDMMC4 (INT_PRI_BASE + 31) - -/* Secondary Interrupt Controller */ -#define INT_SEC_BASE (INT_PRI_BASE + 32) -#define INT_GPIO1 (INT_SEC_BASE + 0) -#define INT_GPIO2 (INT_SEC_BASE + 1) -#define INT_GPIO3 (INT_SEC_BASE + 2) -#define INT_GPIO4 (INT_SEC_BASE + 3) -#define INT_UARTA (INT_SEC_BASE + 4) -#define INT_UARTB (INT_SEC_BASE + 5) -#define INT_I2C (INT_SEC_BASE + 6) -#define INT_SPI (INT_SEC_BASE + 7) -#define INT_TWC (INT_SEC_BASE + 8) -#define INT_TMR3 (INT_SEC_BASE + 9) -#define INT_TMR4 (INT_SEC_BASE + 10) -#define INT_FLOW_RSM0 (INT_SEC_BASE + 11) -#define INT_FLOW_RSM1 (INT_SEC_BASE + 12) -#define INT_SPDIF (INT_SEC_BASE + 13) -#define INT_UARTC (INT_SEC_BASE + 14) -#define INT_MIPI (INT_SEC_BASE + 15) -#define INT_EVENTA (INT_SEC_BASE + 16) -#define INT_EVENTB (INT_SEC_BASE + 17) -#define INT_EVENTC (INT_SEC_BASE + 18) -#define INT_EVENTD (INT_SEC_BASE + 19) -#define INT_VFIR (INT_SEC_BASE + 20) -#define INT_DVC (INT_SEC_BASE + 21) -#define INT_SYS_STATS_MON (INT_SEC_BASE + 22) -#define INT_GPIO5 (INT_SEC_BASE + 23) -#define INT_CPU0_PMU_INTR (INT_SEC_BASE + 24) -#define INT_CPU1_PMU_INTR (INT_SEC_BASE + 25) -#define INT_SEC_RES_26 (INT_SEC_BASE + 26) -#define INT_S_LINK1 (INT_SEC_BASE + 27) -#define INT_APB_DMA_COP (INT_SEC_BASE + 28) -#define INT_AHB_DMA_COP (INT_SEC_BASE + 29) -#define INT_DMA_TX (INT_SEC_BASE + 30) -#define INT_DMA_RX (INT_SEC_BASE + 31) - -/* Tertiary Interrupt Controller */ -#define INT_TRI_BASE (INT_SEC_BASE + 32) -#define INT_HOST1X_COP_SYNCPT (INT_TRI_BASE + 0) -#define INT_HOST1X_MPCORE_SYNCPT (INT_TRI_BASE + 1) -#define INT_HOST1X_COP_GENERAL (INT_TRI_BASE + 2) -#define INT_HOST1X_MPCORE_GENERAL (INT_TRI_BASE + 3) -#define INT_MPE_GENERAL (INT_TRI_BASE + 4) -#define INT_VI_GENERAL (INT_TRI_BASE + 5) -#define INT_EPP_GENERAL (INT_TRI_BASE + 6) -#define INT_ISP_GENERAL (INT_TRI_BASE + 7) -#define INT_2D_GENERAL (INT_TRI_BASE + 8) -#define INT_DISPLAY_GENERAL (INT_TRI_BASE + 9) -#define INT_DISPLAY_B_GENERAL (INT_TRI_BASE + 10) -#define INT_HDMI (INT_TRI_BASE + 11) -#define INT_TVO_GENERAL (INT_TRI_BASE + 12) -#define INT_MC_GENERAL (INT_TRI_BASE + 13) -#define INT_EMC_GENERAL (INT_TRI_BASE + 14) -#define INT_TRI_RES_15 (INT_TRI_BASE + 15) -#define INT_TRI_RES_16 (INT_TRI_BASE + 16) -#define INT_AC97 (INT_TRI_BASE + 17) -#define INT_SPI_2 (INT_TRI_BASE + 18) -#define INT_SPI_3 (INT_TRI_BASE + 19) -#define INT_I2C2 (INT_TRI_BASE + 20) -#define INT_KBC (INT_TRI_BASE + 21) -#define INT_EXTERNAL_PMU (INT_TRI_BASE + 22) -#define INT_GPIO6 (INT_TRI_BASE + 23) -#define INT_TVDAC (INT_TRI_BASE + 24) -#define INT_GPIO7 (INT_TRI_BASE + 25) -#define INT_UARTD (INT_TRI_BASE + 26) -#define INT_UARTE (INT_TRI_BASE + 27) -#define INT_I2C3 (INT_TRI_BASE + 28) -#define INT_SPI_4 (INT_TRI_BASE + 29) -#define INT_TRI_RES_30 (INT_TRI_BASE + 30) -#define INT_SW_RESERVED (INT_TRI_BASE + 31) - -/* Quaternary Interrupt Controller */ -#define INT_QUAD_BASE (INT_TRI_BASE + 32) -#define INT_SNOR (INT_QUAD_BASE + 0) -#define INT_USB3 (INT_QUAD_BASE + 1) -#define INT_PCIE_INTR (INT_QUAD_BASE + 2) -#define INT_PCIE_MSI (INT_QUAD_BASE + 3) -#define INT_QUAD_RES_4 (INT_QUAD_BASE + 4) -#define INT_QUAD_RES_5 (INT_QUAD_BASE + 5) -#define INT_QUAD_RES_6 (INT_QUAD_BASE + 6) -#define INT_QUAD_RES_7 (INT_QUAD_BASE + 7) -#define INT_APB_DMA_CH0 (INT_QUAD_BASE + 8) -#define INT_APB_DMA_CH1 (INT_QUAD_BASE + 9) -#define INT_APB_DMA_CH2 (INT_QUAD_BASE + 10) -#define INT_APB_DMA_CH3 (INT_QUAD_BASE + 11) -#define INT_APB_DMA_CH4 (INT_QUAD_BASE + 12) -#define INT_APB_DMA_CH5 (INT_QUAD_BASE + 13) -#define INT_APB_DMA_CH6 (INT_QUAD_BASE + 14) -#define INT_APB_DMA_CH7 (INT_QUAD_BASE + 15) -#define INT_APB_DMA_CH8 (INT_QUAD_BASE + 16) -#define INT_APB_DMA_CH9 (INT_QUAD_BASE + 17) -#define INT_APB_DMA_CH10 (INT_QUAD_BASE + 18) -#define INT_APB_DMA_CH11 (INT_QUAD_BASE + 19) -#define INT_APB_DMA_CH12 (INT_QUAD_BASE + 20) -#define INT_APB_DMA_CH13 (INT_QUAD_BASE + 21) -#define INT_APB_DMA_CH14 (INT_QUAD_BASE + 22) -#define INT_APB_DMA_CH15 (INT_QUAD_BASE + 23) -#define INT_QUAD_RES_24 (INT_QUAD_BASE + 24) -#define INT_QUAD_RES_25 (INT_QUAD_BASE + 25) -#define INT_QUAD_RES_26 (INT_QUAD_BASE + 26) -#define INT_QUAD_RES_27 (INT_QUAD_BASE + 27) -#define INT_QUAD_RES_28 (INT_QUAD_BASE + 28) -#define INT_QUAD_RES_29 (INT_QUAD_BASE + 29) -#define INT_QUAD_RES_30 (INT_QUAD_BASE + 30) -#define INT_QUAD_RES_31 (INT_QUAD_BASE + 31) - -/* Tegra30 has 5 banks of 32 IRQs */ -#define INT_MAIN_NR (32 * 5) -#define INT_GPIO_BASE (INT_PRI_BASE + INT_MAIN_NR) - -/* Tegra30 has 8 banks of 32 GPIOs */ -#define INT_GPIO_NR (32 * 8) - -#define TEGRA_NR_IRQS (INT_GPIO_BASE + INT_GPIO_NR) - -#define INT_BOARD_BASE TEGRA_NR_IRQS -#define NR_BOARD_IRQS 32 - -#define NR_IRQS (INT_BOARD_BASE + NR_BOARD_IRQS) - -#endif diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c index a8dba64..e82e8b8 100644 --- a/arch/arm/mach-tegra/pcie.c +++ b/arch/arm/mach-tegra/pcie.c @@ -43,6 +43,9 @@ #include "board.h" +/* Hack - need to parse this from DT */ +#define INT_PCIE_INTR 130 + /* register definitions */ #define AFI_OFFSET 0x3800 #define PADS_OFFSET 0x3000 -- 1.7.0.4 ^ permalink raw reply related [flat|nested] 6+ messages in thread
[parent not found: <1348090279-22631-5-git-send-email-swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>]
* Re: [PATCH 5/5] ARM: tegra: select SPARSE_IRQ [not found] ` <1348090279-22631-5-git-send-email-swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> @ 2012-10-15 18:30 ` Stephen Warren 0 siblings, 0 replies; 6+ messages in thread From: Stephen Warren @ 2012-10-15 18:30 UTC (permalink / raw) To: Stephen Warren Cc: Rob Herring, Grant Likely, linux-tegra-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, Stephen Warren On 09/19/2012 03:31 PM, Stephen Warren wrote: > SPARSE_IRQ is required for single zImage support. > > With this enabled, we can delete <mach/irqs.h>. This requires removing > one unnecessary include of that file, and hard-coding the PCIe IRQ into > the PCIe driver. This is a hack that will be dealt with as part of > converting the PCIe driver into a true DT-supporting driver. I have applied this series to Tegra's for-3.8/single-zimage branch. I'm not sure yet if Tegra will actually be able to be part of single zImage in 3.8, but this branch will certainly host a fair few changes to get it very close at least. ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2012-10-15 18:30 UTC | newest]
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2012-09-19 21:31 [PATCH 1/5] ARM: tegra: define DT bindings for and instantiate timer Stephen Warren
[not found] ` <1348090279-22631-1-git-send-email-swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2012-09-19 21:31 ` [PATCH 2/5] ARM: tegra: define DT bindings for and instantiate RTC Stephen Warren
2012-09-19 21:31 ` [PATCH 3/5] ARM: tegra: add TWD to device tree Stephen Warren
2012-09-19 21:31 ` [PATCH 4/5] ARM: tegra: enhance timer.c to get information from " Stephen Warren
2012-09-19 21:31 ` [PATCH 5/5] ARM: tegra: select SPARSE_IRQ Stephen Warren
[not found] ` <1348090279-22631-5-git-send-email-swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2012-10-15 18:30 ` Stephen Warren
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