* [PATCH v11 0/3] ARM: hisi: Add initial support for Hi3519 SOC @ 2016-06-15 2:19 Jiancheng Xue [not found] ` <1465957147-32314-1-git-send-email-xuejiancheng-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org> ` (2 more replies) 0 siblings, 3 replies; 5+ messages in thread From: Jiancheng Xue @ 2016-06-15 2:19 UTC (permalink / raw) To: xuwei5, arnd Cc: robh+dt, linux-kernel, devicetree, linux-arm-kernel, yanhaifeng, yanghongwei, Jiancheng Xue These three patches are abstracted from the patchset titled "[RESEND PATCH v10 0/6] ARM: hisi: Add initial support including clock driver for Hi3519 soc."(https://lkml.org/lkml/2016/3/31/175). The clock driver part was merged in v4.7-rc1. This patch set is mainly used to enable Hi3519 basic soc and add dts files. Jiancheng Xue (3): ARM: hisi: add compatible string for Hi3519 soc ARM: dt-bindings: add device tree bindings for Hi3519 sysctrl ARM: dts: add dts files for Hi3519 .../bindings/arm/hisilicon/hi3519-sysctrl.txt | 14 ++ arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/hi3519-demb.dts | 42 +++++ arch/arm/boot/dts/hi3519.dtsi | 187 +++++++++++++++++++++ arch/arm/mach-hisi/hisilicon.c | 23 +-- 5 files changed, 249 insertions(+), 19 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt create mode 100644 arch/arm/boot/dts/hi3519-demb.dts create mode 100644 arch/arm/boot/dts/hi3519.dtsi -- 1.9.1 ^ permalink raw reply [flat|nested] 5+ messages in thread
[parent not found: <1465957147-32314-1-git-send-email-xuejiancheng-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>]
* [PATCH v11 1/3] ARM: hisi: add compatible string for Hi3519 soc [not found] ` <1465957147-32314-1-git-send-email-xuejiancheng-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org> @ 2016-06-15 2:19 ` Jiancheng Xue 2016-06-28 17:36 ` [PATCH v11 0/3] ARM: hisi: Add initial support for Hi3519 SOC Wei Xu 1 sibling, 0 replies; 5+ messages in thread From: Jiancheng Xue @ 2016-06-15 2:19 UTC (permalink / raw) To: xuwei5-C8/M+/jPZTeaMJb+Lgu22Q, arnd-r2nGTMty4D4 Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, linux-kernel-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, yanhaifeng-C8/M+/jPZTeaMJb+Lgu22Q, yanghongwei-C8/M+/jPZTeaMJb+Lgu22Q, Jiancheng Xue From: Jiancheng Xue <xuejiancheng-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> add compatible string for Hi3519 soc. Signed-off-by: Jiancheng Xue <xuejiancheng-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> --- arch/arm/mach-hisi/hisilicon.c | 23 ++++------------------- 1 file changed, 4 insertions(+), 19 deletions(-) diff --git a/arch/arm/mach-hisi/hisilicon.c b/arch/arm/mach-hisi/hisilicon.c index 8cc6215..00dae89 100644 --- a/arch/arm/mach-hisi/hisilicon.c +++ b/arch/arm/mach-hisi/hisilicon.c @@ -54,30 +54,15 @@ DT_MACHINE_START(HI3620, "Hisilicon Hi3620 (Flattened Device Tree)") .dt_compat = hi3xxx_compat, MACHINE_END -static const char *const hix5hd2_compat[] __initconst = { +static const char *const hisilicon_compat[] __initconst = { "hisilicon,hix5hd2", - NULL, -}; - -DT_MACHINE_START(HIX5HD2_DT, "Hisilicon HIX5HD2 (Flattened Device Tree)") - .dt_compat = hix5hd2_compat, -MACHINE_END - -static const char *const hip04_compat[] __initconst = { "hisilicon,hip04-d01", - NULL, -}; - -DT_MACHINE_START(HIP04, "Hisilicon HiP04 (Flattened Device Tree)") - .dt_compat = hip04_compat, -MACHINE_END - -static const char *const hip01_compat[] __initconst = { "hisilicon,hip01", "hisilicon,hip01-ca9x2", + "hisilicon,hi3519", NULL, }; -DT_MACHINE_START(HIP01, "Hisilicon HIP01 (Flattened Device Tree)") - .dt_compat = hip01_compat, +DT_MACHINE_START(HISILICON_DT, "HiSilicon Soc") + .dt_compat = hisilicon_compat, MACHINE_END -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v11 0/3] ARM: hisi: Add initial support for Hi3519 SOC [not found] ` <1465957147-32314-1-git-send-email-xuejiancheng-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org> 2016-06-15 2:19 ` [PATCH v11 1/3] ARM: hisi: add compatible string for Hi3519 soc Jiancheng Xue @ 2016-06-28 17:36 ` Wei Xu 1 sibling, 0 replies; 5+ messages in thread From: Wei Xu @ 2016-06-28 17:36 UTC (permalink / raw) To: Jiancheng Xue, arnd-r2nGTMty4D4 Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, linux-kernel-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, yanhaifeng-C8/M+/jPZTeaMJb+Lgu22Q, yanghongwei-C8/M+/jPZTeaMJb+Lgu22Q Hi Jiancheng, On 15/06/2016 03:19, Jiancheng Xue wrote: > These three patches are abstracted from the patchset titled > "[RESEND PATCH v10 0/6] ARM: hisi: Add initial support including > clock driver for Hi3519 soc."(https://lkml.org/lkml/2016/3/31/175). > The clock driver part was merged in v4.7-rc1. This patch set > is mainly used to enable Hi3519 basic soc and add dts files. > > Jiancheng Xue (3): > ARM: hisi: add compatible string for Hi3519 soc > ARM: dt-bindings: add device tree bindings for Hi3519 sysctrl > ARM: dts: add dts files for Hi3519 > Thanks! Applied all the 3 patches to the hisilicon soc tree. I have modified the dts Makefile in the patch 3 and shuffled the ARCH_HIGHBANK, ARCH_HISI and ARCH_HIX5HD2 around to keep the list sorted. Best Regards, Wei -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v11 2/3] ARM: dt-bindings: add device tree bindings for Hi3519 sysctrl 2016-06-15 2:19 [PATCH v11 0/3] ARM: hisi: Add initial support for Hi3519 SOC Jiancheng Xue [not found] ` <1465957147-32314-1-git-send-email-xuejiancheng-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org> @ 2016-06-15 2:19 ` Jiancheng Xue 2016-06-15 2:19 ` [PATCH v11 3/3] ARM: dts: add dts files for Hi3519 Jiancheng Xue 2 siblings, 0 replies; 5+ messages in thread From: Jiancheng Xue @ 2016-06-15 2:19 UTC (permalink / raw) To: xuwei5, arnd Cc: robh+dt, linux-kernel, devicetree, linux-arm-kernel, yanhaifeng, yanghongwei, Jiancheng Xue From: Jiancheng Xue <xuejiancheng@huawei.com> Add device tree bindings for Hi3519 system controller. Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com> Acked-by: Rob Herring <robh@kernel.org> --- .../devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt new file mode 100644 index 0000000..115c5be --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt @@ -0,0 +1,14 @@ +* Hisilicon Hi3519 System Controller Block + +This bindings use the following binding: +Documentation/devicetree/bindings/mfd/syscon.txt + +Required properties: +- compatible: "hisilicon,hi3519-sysctrl". +- reg: the register region of this block + +Examples: +sysctrl: system-controller@12010000 { + compatible = "hisilicon,hi3519-sysctrl", "syscon"; + reg = <0x12010000 0x1000>; +}; -- 1.9.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v11 3/3] ARM: dts: add dts files for Hi3519 2016-06-15 2:19 [PATCH v11 0/3] ARM: hisi: Add initial support for Hi3519 SOC Jiancheng Xue [not found] ` <1465957147-32314-1-git-send-email-xuejiancheng-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org> 2016-06-15 2:19 ` [PATCH v11 2/3] ARM: dt-bindings: add device tree bindings for Hi3519 sysctrl Jiancheng Xue @ 2016-06-15 2:19 ` Jiancheng Xue 2 siblings, 0 replies; 5+ messages in thread From: Jiancheng Xue @ 2016-06-15 2:19 UTC (permalink / raw) To: xuwei5, arnd Cc: robh+dt, linux-kernel, devicetree, linux-arm-kernel, yanhaifeng, yanghongwei, Jiancheng Xue From: Jiancheng Xue <xuejiancheng@huawei.com> add dts files for Hi3519 Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com> --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/hi3519-demb.dts | 42 +++++++++ arch/arm/boot/dts/hi3519.dtsi | 187 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 231 insertions(+) create mode 100644 arch/arm/boot/dts/hi3519-demb.dts create mode 100644 arch/arm/boot/dts/hi3519.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 06b6c2d..b47b975 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -146,6 +146,8 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \ exynos5800-peach-pi.dtb dtb-$(CONFIG_ARCH_HI3xxx) += \ hi3620-hi4511.dtb +dtb-$(CONFIG_ARCH_HISI) += \ + hi3519-demb.dtb dtb-$(CONFIG_ARCH_HIX5HD2) += \ hisi-x5hd2-dkb.dtb dtb-$(CONFIG_ARCH_HIGHBANK) += \ diff --git a/arch/arm/boot/dts/hi3519-demb.dts b/arch/arm/boot/dts/hi3519-demb.dts new file mode 100644 index 0000000..6991ab6 --- /dev/null +++ b/arch/arm/boot/dts/hi3519-demb.dts @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2015 HiSilicon Technologies Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + * + */ + +/dts-v1/; +#include "hi3519.dtsi" + +/ { + model = "HiSilicon HI3519 DEMO Board"; + compatible = "hisilicon,hi3519"; + + aliases { + serial0 = &uart0; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&dual_timer0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/hi3519.dtsi b/arch/arm/boot/dts/hi3519.dtsi new file mode 100644 index 0000000..5729ecf --- /dev/null +++ b/arch/arm/boot/dts/hi3519.dtsi @@ -0,0 +1,187 @@ +/* + * Copyright (c) 2015 HiSilicon Technologies Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + * + */ + +#include <dt-bindings/clock/hi3519-clock.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +/ { + #address-cells = <1>; + #size-cells = <1>; + chosen { }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0>; + }; + }; + + gic: interrupt-controller@10300000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x10301000 0x1000>, <0x10302000 0x1000>; + }; + + clk_3m: clk_3m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <3000000>; + }; + + crg: clock-reset-controller@12010000 { + compatible = "hisilicon,hi3519-crg"; + #clock-cells = <1>; + #reset-cells = <2>; + reg = <0x12010000 0x10000>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges; + + uart0: serial@12100000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12100000 0x1000>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg HI3519_UART0_CLK>; + clock-names = "apb_pclk"; + status = "disable"; + }; + + uart1: serial@12101000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12101000 0x1000>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg HI3519_UART1_CLK>; + clock-names = "apb_pclk"; + status = "disable"; + }; + + uart2: serial@12102000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12102000 0x1000>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg HI3519_UART2_CLK>; + clock-names = "apb_pclk"; + status = "disable"; + }; + + uart3: serial@12103000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12103000 0x1000>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg HI3519_UART3_CLK>; + clock-names = "apb_pclk"; + status = "disable"; + }; + + uart4: serial@12104000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12104000 0x1000>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg HI3519_UART4_CLK>; + clock-names = "apb_pclk"; + status = "disable"; + }; + + dual_timer0: timer@12000000 { + compatible = "arm,sp804", "arm,primecell"; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x12000000 0x1000>; + clocks = <&clk_3m>; + clock-names = "apb_pclk"; + status = "disable"; + }; + + dual_timer1: timer@12001000 { + compatible = "arm,sp804", "arm,primecell"; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x12001000 0x1000>; + clocks = <&clk_3m>; + clock-names = "apb_pclk"; + status = "disable"; + }; + + dual_timer2: timer@12002000 { + compatible = "arm,sp804", "arm,primecell"; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x12002000 0x1000>; + clocks = <&clk_3m>; + clock-names = "apb_pclk"; + status = "disable"; + }; + + spi_bus0: spi@12120000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x12120000 0x1000>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg HI3519_SPI0_CLK>; + clock-names = "apb_pclk"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disable"; + }; + + spi_bus1: spi@12121000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x12121000 0x1000>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg HI3519_SPI1_CLK>; + clock-names = "apb_pclk"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disable"; + }; + + spi_bus2: spi@12122000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x12122000 0x1000>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg HI3519_SPI2_CLK>; + clock-names = "apb_pclk"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disable"; + }; + + sysctrl: system-controller@12020000 { + compatible = "hisilicon,hi3519-sysctrl", "syscon"; + reg = <0x12020000 0x1000>; + }; + + reboot { + compatible = "syscon-reboot"; + regmap = <&sysctrl>; + offset = <0x4>; + mask = <0xdeadbeef>; + }; + }; +}; -- 1.9.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
end of thread, other threads:[~2016-06-28 17:36 UTC | newest] Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2016-06-15 2:19 [PATCH v11 0/3] ARM: hisi: Add initial support for Hi3519 SOC Jiancheng Xue [not found] ` <1465957147-32314-1-git-send-email-xuejiancheng-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org> 2016-06-15 2:19 ` [PATCH v11 1/3] ARM: hisi: add compatible string for Hi3519 soc Jiancheng Xue 2016-06-28 17:36 ` [PATCH v11 0/3] ARM: hisi: Add initial support for Hi3519 SOC Wei Xu 2016-06-15 2:19 ` [PATCH v11 2/3] ARM: dt-bindings: add device tree bindings for Hi3519 sysctrl Jiancheng Xue 2016-06-15 2:19 ` [PATCH v11 3/3] ARM: dts: add dts files for Hi3519 Jiancheng Xue
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