* [PATCH] arm64: dts: berlin4ct: Add L2 cache topology
@ 2016-06-16 8:40 Jisheng Zhang
[not found] ` <1466066418-1141-1-git-send-email-jszhang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>
0 siblings, 1 reply; 5+ messages in thread
From: Jisheng Zhang @ 2016-06-16 8:40 UTC (permalink / raw)
To: sebastian.hesselbarth, robh+dt, mark.rutland, catalin.marinas,
will.deacon
Cc: linux-arm-kernel, devicetree, linux-kernel, Jisheng Zhang
This patch adds the L2 cache topology for berlin4ct which has 1MB L2
cache.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
---
arch/arm64/boot/dts/marvell/berlin4ct.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi
index 099ad93..c9e3a98 100644
--- a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi
+++ b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi
@@ -68,6 +68,7 @@
device_type = "cpu";
reg = <0x0>;
enable-method = "psci";
+ next-level-cache = <&L2_0>;
cpu-idle-states = <&CPU_SLEEP_0>;
};
@@ -76,6 +77,7 @@
device_type = "cpu";
reg = <0x1>;
enable-method = "psci";
+ next-level-cache = <&L2_0>;
cpu-idle-states = <&CPU_SLEEP_0>;
};
@@ -84,6 +86,7 @@
device_type = "cpu";
reg = <0x2>;
enable-method = "psci";
+ next-level-cache = <&L2_0>;
cpu-idle-states = <&CPU_SLEEP_0>;
};
@@ -92,9 +95,14 @@
device_type = "cpu";
reg = <0x3>;
enable-method = "psci";
+ next-level-cache = <&L2_0>;
cpu-idle-states = <&CPU_SLEEP_0>;
};
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ };
+
idle-states {
entry-method = "psci";
CPU_SLEEP_0: cpu-sleep-0 {
--
2.8.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] arm64: dts: berlin4ct: Add L2 cache topology
[not found] ` <1466066418-1141-1-git-send-email-jszhang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>
@ 2016-07-06 17:49 ` Sebastian Hesselbarth
[not found] ` <577D448D.8030701-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
0 siblings, 1 reply; 5+ messages in thread
From: Sebastian Hesselbarth @ 2016-07-06 17:49 UTC (permalink / raw)
To: Jisheng Zhang, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, catalin.marinas-5wv7dgnIgG8,
will.deacon-5wv7dgnIgG8
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
On 16.06.2016 10:40, Jisheng Zhang wrote:
> This patch adds the L2 cache topology for berlin4ct which has 1MB L2
> cache.
>
> Signed-off-by: Jisheng Zhang <jszhang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>
> ---
> arch/arm64/boot/dts/marvell/berlin4ct.dtsi | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi
> index 099ad93..c9e3a98 100644
> --- a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi
> +++ b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi
[...]
> @@ -92,9 +95,14 @@
> device_type = "cpu";
> reg = <0x3>;
> enable-method = "psci";
> + next-level-cache = <&L2_0>;
> cpu-idle-states = <&CPU_SLEEP_0>;
> };
>
> + L2_0: l2-cache0 {
Jisheng,
The node name should just have a generic name that reflects
the purpose of the unit it represents, i.e.
s/l2-cache0/cache/
nits:
- What is that "0" for? Please remove if there is no good reason.
- Does the node label need to be upper-case? Please make it lower case.
Sebastian
> + compatible = "cache";
> + };
> +
> idle-states {
> entry-method = "psci";
> CPU_SLEEP_0: cpu-sleep-0 {
>
--
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] arm64: dts: berlin4ct: Add L2 cache topology
[not found] ` <577D448D.8030701-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2016-07-07 5:48 ` Jisheng Zhang
2016-07-07 17:10 ` Sebastian Hesselbarth
0 siblings, 1 reply; 5+ messages in thread
From: Jisheng Zhang @ 2016-07-07 5:48 UTC (permalink / raw)
To: Sebastian Hesselbarth
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
catalin.marinas-5wv7dgnIgG8, will.deacon-5wv7dgnIgG8,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Dear Sebastian,
On Wed, 6 Jul 2016 19:49:01 +0200 Sebastian Hesselbarth wrote:
> On 16.06.2016 10:40, Jisheng Zhang wrote:
> > This patch adds the L2 cache topology for berlin4ct which has 1MB L2
> > cache.
> >
> > Signed-off-by: Jisheng Zhang <jszhang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>
> > ---
> > arch/arm64/boot/dts/marvell/berlin4ct.dtsi | 8 ++++++++
> > 1 file changed, 8 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi
> > index 099ad93..c9e3a98 100644
> > --- a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi
> > +++ b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi
> [...]
> > @@ -92,9 +95,14 @@
> > device_type = "cpu";
> > reg = <0x3>;
> > enable-method = "psci";
> > + next-level-cache = <&L2_0>;
> > cpu-idle-states = <&CPU_SLEEP_0>;
> > };
> >
> > + L2_0: l2-cache0 {
>
> Jisheng,
>
> The node name should just have a generic name that reflects
> the purpose of the unit it represents, i.e.
> s/l2-cache0/cache/
IMHO, "cache" is too generic, this is L2 cache topology, so in v2, I use
"l2-cache" instead. what do you think?
PS: I found other arm64 SoCs also use "l2-cache" as the node name.
>
> nits:
> - What is that "0" for? Please remove if there is no good reason.
> - Does the node label need to be upper-case? Please make it lower case.
>
oh yeah, thanks for the hints! will do in v2.
Thanks for reviewing,
Jisheng
> Sebastian
>
> > + compatible = "cache";
> > + };
> > +
> > idle-states {
> > entry-method = "psci";
> > CPU_SLEEP_0: cpu-sleep-0 {
> >
>
--
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] arm64: dts: berlin4ct: Add L2 cache topology
2016-07-07 5:48 ` Jisheng Zhang
@ 2016-07-07 17:10 ` Sebastian Hesselbarth
2016-07-08 6:05 ` Jisheng Zhang
0 siblings, 1 reply; 5+ messages in thread
From: Sebastian Hesselbarth @ 2016-07-07 17:10 UTC (permalink / raw)
To: Jisheng Zhang
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
catalin.marinas-5wv7dgnIgG8, will.deacon-5wv7dgnIgG8,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
On 07.07.2016 07:48, Jisheng Zhang wrote:
> On Wed, 6 Jul 2016 19:49:01 +0200 Sebastian Hesselbarth wrote:
>> On 16.06.2016 10:40, Jisheng Zhang wrote:
>>> This patch adds the L2 cache topology for berlin4ct which has 1MB L2
>>> cache.
>>>
>>> Signed-off-by: Jisheng Zhang <jszhang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>
>>> ---
>>> arch/arm64/boot/dts/marvell/berlin4ct.dtsi | 8 ++++++++
>>> 1 file changed, 8 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi
>>> index 099ad93..c9e3a98 100644
>>> --- a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi
>>> +++ b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi
>> [...]
>>> @@ -92,9 +95,14 @@
>>> device_type = "cpu";
>>> reg = <0x3>;
>>> enable-method = "psci";
>>> + next-level-cache = <&L2_0>;
>>> cpu-idle-states = <&CPU_SLEEP_0>;
>>> };
>>>
>>> + L2_0: l2-cache0 {
>>
>> The node name should just have a generic name that reflects
>> the purpose of the unit it represents, i.e.
>> s/l2-cache0/cache/
>
> IMHO, "cache" is too generic, this is L2 cache topology, so in v2, I use
> "l2-cache" instead. what do you think?
>
> PS: I found other arm64 SoCs also use "l2-cache" as the node name.
Yeah, I realized that too. Anyway, the node name should be as generic
as possible. Moreover, the more specific compatible string below also
is "cache", too. So I see no reason why the node name should be more
specific than the compatible.
>>> + compatible = "cache";
>>> + };
If you want to have the cache-level represented in the node, I guess
you can use cache-level property. However, I cannot find any cache
related binding documentation other than for arm(32) and powerpc that
mentions cache-level property.
If you are fine with it, I can pick up the v2 you sent earlier, rename
the node to "cache" only, and add a cache-level = <2>; property while
applying.
Sebastian
>>> idle-states {
>>> entry-method = "psci";
>>> CPU_SLEEP_0: cpu-sleep-0 {
>>>
>>
>
--
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] arm64: dts: berlin4ct: Add L2 cache topology
2016-07-07 17:10 ` Sebastian Hesselbarth
@ 2016-07-08 6:05 ` Jisheng Zhang
0 siblings, 0 replies; 5+ messages in thread
From: Jisheng Zhang @ 2016-07-08 6:05 UTC (permalink / raw)
To: Sebastian Hesselbarth
Cc: robh+dt, mark.rutland, catalin.marinas, will.deacon,
linux-arm-kernel, devicetree, linux-kernel
Dear Sebastian,
On Thu, 7 Jul 2016 19:10:26 +0200 Sebastian Hesselbarth wrote:
> On 07.07.2016 07:48, Jisheng Zhang wrote:
> > On Wed, 6 Jul 2016 19:49:01 +0200 Sebastian Hesselbarth wrote:
> >> On 16.06.2016 10:40, Jisheng Zhang wrote:
> >>> This patch adds the L2 cache topology for berlin4ct which has 1MB L2
> >>> cache.
> >>>
> >>> Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
> >>> ---
> >>> arch/arm64/boot/dts/marvell/berlin4ct.dtsi | 8 ++++++++
> >>> 1 file changed, 8 insertions(+)
> >>>
> >>> diff --git a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi
> >>> index 099ad93..c9e3a98 100644
> >>> --- a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi
> >>> +++ b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi
> >> [...]
> >>> @@ -92,9 +95,14 @@
> >>> device_type = "cpu";
> >>> reg = <0x3>;
> >>> enable-method = "psci";
> >>> + next-level-cache = <&L2_0>;
> >>> cpu-idle-states = <&CPU_SLEEP_0>;
> >>> };
> >>>
> >>> + L2_0: l2-cache0 {
> >>
> >> The node name should just have a generic name that reflects
> >> the purpose of the unit it represents, i.e.
> >> s/l2-cache0/cache/
> >
> > IMHO, "cache" is too generic, this is L2 cache topology, so in v2, I use
> > "l2-cache" instead. what do you think?
> >
> > PS: I found other arm64 SoCs also use "l2-cache" as the node name.
>
> Yeah, I realized that too. Anyway, the node name should be as generic
> as possible. Moreover, the more specific compatible string below also
> is "cache", too. So I see no reason why the node name should be more
> specific than the compatible.
make sense, I agree with you now.
>
> >>> + compatible = "cache";
> >>> + };
>
> If you want to have the cache-level represented in the node, I guess
> you can use cache-level property. However, I cannot find any cache
> related binding documentation other than for arm(32) and powerpc that
> mentions cache-level property.
>
> If you are fine with it, I can pick up the v2 you sent earlier, rename
> the node to "cache" only, and add a cache-level = <2>; property while
> applying.
Per my understanding of the code, drivers/base/cacheinfo.c and related
source code, the "cache-level" property isn't used at all, so could you
please only rename the node to "cache"?
Thanks in advance,
Jisheng
^ permalink raw reply [flat|nested] 5+ messages in thread
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2016-06-16 8:40 [PATCH] arm64: dts: berlin4ct: Add L2 cache topology Jisheng Zhang
[not found] ` <1466066418-1141-1-git-send-email-jszhang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>
2016-07-06 17:49 ` Sebastian Hesselbarth
[not found] ` <577D448D.8030701-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2016-07-07 5:48 ` Jisheng Zhang
2016-07-07 17:10 ` Sebastian Hesselbarth
2016-07-08 6:05 ` Jisheng Zhang
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