From: Sricharan R <sricharan@codeaurora.org>
To: mturquette@baylibre.com, sboyd@codeaurora.org,
devicetree@vger.kernel.org, linux-pm@vger.kernel.org,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
viresh.kumar@linaro.org, linux-arm-kernel@lists.infradead.org
Cc: sricharan@codeaurora.org
Subject: [PATCH v4 06/12] clk: qcom: Add IPQ806X's HFPLLs
Date: Fri, 8 Dec 2017 15:12:24 +0530 [thread overview]
Message-ID: <1512726150-7204-7-git-send-email-sricharan@codeaurora.org> (raw)
In-Reply-To: <1512726150-7204-1-git-send-email-sricharan@codeaurora.org>
From: Stephen Boyd <sboyd@codeaurora.org>
Describe the HFPLLs present on IPQ806X devices.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
drivers/clk/qcom/gcc-ipq806x.c | 82 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 82 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index 28eb200..d571cf8 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -30,6 +30,7 @@
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-branch.h"
+#include "clk-hfpll.h"
#include "reset.h"
static struct clk_pll pll0 = {
@@ -113,6 +114,84 @@
},
};
+static struct hfpll_data hfpll0_data = {
+ .mode_reg = 0x3200,
+ .l_reg = 0x3208,
+ .m_reg = 0x320c,
+ .n_reg = 0x3210,
+ .config_reg = 0x3204,
+ .status_reg = 0x321c,
+ .config_val = 0x7845c665,
+ .droop_reg = 0x3214,
+ .droop_val = 0x0108c000,
+ .min_rate = 600000000UL,
+ .max_rate = 1800000000UL,
+};
+
+static struct clk_hfpll hfpll0 = {
+ .d = &hfpll0_data,
+ .clkr.hw.init = &(struct clk_init_data){
+ .parent_names = (const char *[]){ "pxo" },
+ .num_parents = 1,
+ .name = "hfpll0",
+ .ops = &clk_ops_hfpll,
+ .flags = CLK_IGNORE_UNUSED,
+ },
+ .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
+};
+
+static struct hfpll_data hfpll1_data = {
+ .mode_reg = 0x3240,
+ .l_reg = 0x3248,
+ .m_reg = 0x324c,
+ .n_reg = 0x3250,
+ .config_reg = 0x3244,
+ .status_reg = 0x325c,
+ .config_val = 0x7845c665,
+ .droop_reg = 0x3314,
+ .droop_val = 0x0108c000,
+ .min_rate = 600000000UL,
+ .max_rate = 1800000000UL,
+};
+
+static struct clk_hfpll hfpll1 = {
+ .d = &hfpll1_data,
+ .clkr.hw.init = &(struct clk_init_data){
+ .parent_names = (const char *[]){ "pxo" },
+ .num_parents = 1,
+ .name = "hfpll1",
+ .ops = &clk_ops_hfpll,
+ .flags = CLK_IGNORE_UNUSED,
+ },
+ .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
+};
+
+static struct hfpll_data hfpll_l2_data = {
+ .mode_reg = 0x3300,
+ .l_reg = 0x3308,
+ .m_reg = 0x330c,
+ .n_reg = 0x3310,
+ .config_reg = 0x3304,
+ .status_reg = 0x331c,
+ .config_val = 0x7845c665,
+ .droop_reg = 0x3314,
+ .droop_val = 0x0108c000,
+ .min_rate = 600000000UL,
+ .max_rate = 1800000000UL,
+};
+
+static struct clk_hfpll hfpll_l2 = {
+ .d = &hfpll_l2_data,
+ .clkr.hw.init = &(struct clk_init_data){
+ .parent_names = (const char *[]){ "pxo" },
+ .num_parents = 1,
+ .name = "hfpll_l2",
+ .ops = &clk_ops_hfpll,
+ .flags = CLK_IGNORE_UNUSED,
+ },
+ .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
+};
+
static struct clk_pll pll14 = {
.l_reg = 0x31c4,
.m_reg = 0x31c8,
@@ -2800,6 +2879,9 @@ enum {
[UBI32_CORE2_CLK_SRC] = &ubi32_core2_src_clk.clkr,
[NSSTCM_CLK_SRC] = &nss_tcm_src.clkr,
[NSSTCM_CLK] = &nss_tcm_clk.clkr,
+ [PLL9] = &hfpll0.clkr,
+ [PLL10] = &hfpll1.clkr,
+ [PLL12] = &hfpll_l2.clkr,
};
static const struct qcom_reset_map gcc_ipq806x_resets[] = {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
next prev parent reply other threads:[~2017-12-08 9:42 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-08 9:42 [RESEND PATCH v4 00/12] Krait clocks + Krait CPUfreq Sricharan R
2017-12-08 9:42 ` [PATCH v4 01/12] ARM: Add Krait L2 register accessor functions Sricharan R
2017-12-08 9:42 ` [PATCH v4 02/12] clk: mux: Split out register accessors for reuse Sricharan R
2017-12-08 9:42 ` [PATCH v4 03/12] clk: qcom: Add support for High-Frequency PLLs (HFPLLs) Sricharan R
2017-12-08 9:42 ` [PATCH v4 04/12] clk: qcom: Add HFPLL driver Sricharan R
2017-12-12 20:35 ` Rob Herring
2017-12-13 11:10 ` Sricharan R
2017-12-08 9:42 ` [PATCH v4 05/12] clk: qcom: Add MSM8960/APQ8064's HFPLLs Sricharan R
2017-12-12 20:36 ` Rob Herring
2017-12-13 11:10 ` Sricharan R
2017-12-08 9:42 ` Sricharan R [this message]
2017-12-08 9:42 ` [PATCH v4 07/12] clk: qcom: Add support for Krait clocks Sricharan R
2017-12-08 9:42 ` [PATCH v4 08/12] clk: qcom: Add KPSS ACC/GCC driver Sricharan R
2017-12-12 20:38 ` Rob Herring
2017-12-13 11:42 ` Sricharan R
2017-12-08 9:42 ` [PATCH v4 09/12] clk: qcom: Add Krait clock controller driver Sricharan R
2017-12-12 20:51 ` Rob Herring
2017-12-13 11:11 ` Sricharan R
[not found] ` <1512726150-7204-1-git-send-email-sricharan-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-12-08 9:42 ` [PATCH v4 10/12] clk: qcom: Add safe switch hook for krait mux clocks Sricharan R
2017-12-08 9:42 ` [PATCH v4 11/12] cpufreq: Add module to register cpufreq on Krait CPUs Sricharan R
2017-12-11 8:39 ` Viresh Kumar
2017-12-11 13:22 ` Sricharan R
2017-12-08 9:42 ` [PATCH v4 12/12] cpufreq: dt: Reintroduce independent_clocks platform data Sricharan R
2017-12-11 8:33 ` Viresh Kumar
2017-12-11 13:24 ` Sricharan R
-- strict thread matches above, loose matches on Subject: below --
2017-12-08 9:29 [PATCH v4 00/12] Krait clocks + Krait CPUfreq Sricharan R
2017-12-08 9:29 ` [PATCH v4 06/12] clk: qcom: Add IPQ806X's HFPLLs Sricharan R
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