devicetree.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
* [PATCH 1/1] arm: sunxi: Add alternative pins for spi0
@ 2017-12-13  7:44 Stefan Mavrodiev
       [not found] ` <1513151074-6888-1-git-send-email-stefan-kyXcfZUBQGPQT0dZR+AlfA@public.gmane.org>
  0 siblings, 1 reply; 7+ messages in thread
From: Stefan Mavrodiev @ 2017-12-13  7:44 UTC (permalink / raw)
  Cc: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Stefan Mavrodiev,
	Rob Herring, Mark Rutland, Russell King, Maxime Ripard,
	Chen-Yu Tsai,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM PORT, open list

Allwinner A10/A13/A20 SoCs have pinmux for spi0
on port C. The patch adds these pins in the respective
dts includes.

Signed-off-by: Stefan Mavrodiev <stefan-kyXcfZUBQGPQT0dZR+AlfA@public.gmane.org>
---
 arch/arm/boot/dts/sun4i-a10.dtsi | 10 ++++++++++
 arch/arm/boot/dts/sun5i.dtsi     | 10 ++++++++++
 arch/arm/boot/dts/sun7i-a20.dtsi | 10 ++++++++++
 3 files changed, 30 insertions(+)

diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 5840f5c..d835741 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -705,11 +705,21 @@
 				bias-pull-up;
 			};
 
+			spi0_pc_pins: spi0-pc-pins {
+				pins = "PC0", "PC1", "PC2";
+				function = "spi0";
+			};
+
 			spi0_pi_pins: spi0-pi-pins {
 				pins = "PI11", "PI12", "PI13";
 				function = "spi0";
 			};
 
+			spi0_cs0_pc_pin: spi0-cs0-pc-pin {
+				pins = "PC23";
+				function = "spi0";
+			};
+
 			spi0_cs0_pi_pin: spi0-cs0-pi-pin {
 				pins = "PI10";
 				function = "spi0";
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index 07f2248..9290e26 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -492,6 +492,16 @@
 				function = "nand0";
 			};
 
+			spi0_pins_a: spi0@0 {
+				pins = "PC0", "PC1", "PC2";
+				function = "spi0";
+			};
+
+			spi0_cs0_pins_a: spi0-cs0@0 {
+				pins = "PC3";
+				function = "spi0";
+			};
+
 			spi2_pins_a: spi2@0 {
 				pins = "PE1", "PE2", "PE3";
 				function = "spi2";
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 59655e4..6930527 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -838,11 +838,21 @@
 				function = "spi0";
 			};
 
+			spi0_pins_b: spi0@1 {
+				pins = "PC0", "PC1", "PC2";
+				function = "spi0";
+			};
+
 			spi0_cs0_pins_a: spi0_cs0@0 {
 				pins = "PI10";
 				function = "spi0";
 			};
 
+			spi0_cs0_pins_b: spi0_cs0@1 {
+				pins = "PC23";
+				function = "spi0";
+			};
+
 			spi0_cs1_pins_a: spi0_cs1@0 {
 				pins = "PI14";
 				function = "spi0";
-- 
2.7.4

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

^ permalink raw reply related	[flat|nested] 7+ messages in thread

* Re: [PATCH 1/1] arm: sunxi: Add alternative pins for spi0
       [not found] ` <1513151074-6888-1-git-send-email-stefan-kyXcfZUBQGPQT0dZR+AlfA@public.gmane.org>
@ 2017-12-13 15:40   ` Maxime Ripard
       [not found]     ` <20171213154035.qc655iahjoeflftq-ZC1Zs529Oq4@public.gmane.org>
  0 siblings, 1 reply; 7+ messages in thread
From: Maxime Ripard @ 2017-12-13 15:40 UTC (permalink / raw)
  To: Stefan Mavrodiev
  Cc: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Rob Herring, Mark Rutland,
	Russell King, Chen-Yu Tsai,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM PORT, open list

[-- Attachment #1: Type: text/plain, Size: 487 bytes --]

Hi,

On Wed, Dec 13, 2017 at 09:44:34AM +0200, Stefan Mavrodiev wrote:
> Allwinner A10/A13/A20 SoCs have pinmux for spi0
> on port C. The patch adds these pins in the respective
> dts includes.
> 
> Signed-off-by: Stefan Mavrodiev <stefan-kyXcfZUBQGPQT0dZR+AlfA@public.gmane.org>

Do you have any boards that are using these?

We won't merge that patch if there's no users for it.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH 1/1] arm: sunxi: Add alternative pins for spi0
       [not found]     ` <20171213154035.qc655iahjoeflftq-ZC1Zs529Oq4@public.gmane.org>
@ 2017-12-14  6:24       ` Stefan Mavrodiev
       [not found]         ` <5f518e4b-e624-17c2-7e72-24ba930a1c15-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
  0 siblings, 1 reply; 7+ messages in thread
From: Stefan Mavrodiev @ 2017-12-14  6:24 UTC (permalink / raw)
  To: Maxime Ripard, Stefan Mavrodiev
  Cc: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Rob Herring, Mark Rutland,
	Russell King, Chen-Yu Tsai,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM PORT, open list

On 12/13/2017 05:40 PM, Maxime Ripard wrote:
> Hi,
>
> On Wed, Dec 13, 2017 at 09:44:34AM +0200, Stefan Mavrodiev wrote:
>> Allwinner A10/A13/A20 SoCs have pinmux for spi0
>> on port C. The patch adds these pins in the respective
>> dts includes.
>>
>> Signed-off-by: Stefan Mavrodiev <stefan-kyXcfZUBQGPQT0dZR+AlfA@public.gmane.org>
> Do you have any boards that are using these?
>
> We won't merge that patch if there's no users for it.
>
> Maxime
>
A20-OLinuXino-Lime/Lime2 and A10-OLinuXino-Lime with spi flash.
For A13 we still doesn't have that option.

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH 1/1] arm: sunxi: Add alternative pins for spi0
       [not found]         ` <5f518e4b-e624-17c2-7e72-24ba930a1c15-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2017-12-15 15:08           ` Maxime Ripard
       [not found]             ` <20171215150823.jplgknururmkvp2t-ZC1Zs529Oq4@public.gmane.org>
  0 siblings, 1 reply; 7+ messages in thread
From: Maxime Ripard @ 2017-12-15 15:08 UTC (permalink / raw)
  To: Stefan Mavrodiev
  Cc: Stefan Mavrodiev, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw,
	Rob Herring, Mark Rutland, Russell King, Chen-Yu Tsai,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM PORT, open list

[-- Attachment #1: Type: text/plain, Size: 947 bytes --]

Hi,

On Thu, Dec 14, 2017 at 08:24:54AM +0200, Stefan Mavrodiev wrote:
> On 12/13/2017 05:40 PM, Maxime Ripard wrote:
> > Hi,
> > 
> > On Wed, Dec 13, 2017 at 09:44:34AM +0200, Stefan Mavrodiev wrote:
> > > Allwinner A10/A13/A20 SoCs have pinmux for spi0
> > > on port C. The patch adds these pins in the respective
> > > dts includes.
> > > 
> > > Signed-off-by: Stefan Mavrodiev <stefan-kyXcfZUBQGPQT0dZR+AlfA@public.gmane.org>
> > Do you have any boards that are using these?
> > 
> > We won't merge that patch if there's no users for it.
>
> A20-OLinuXino-Lime/Lime2 and A10-OLinuXino-Lime with spi flash.
> For A13 we still doesn't have that option.

If this bus is exposed on the headers, you can add those to the DT but
leave them disabled if you want. Buf if there's no users of those
nodes, our policy is not to merge them.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH 1/1] arm: sunxi: Add alternative pins for spi0
       [not found]             ` <20171215150823.jplgknururmkvp2t-ZC1Zs529Oq4@public.gmane.org>
@ 2017-12-18  6:24               ` Stefan Mavrodiev
       [not found]                 ` <ca648552-cefb-e19d-72cf-8b56e97b013d-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
  0 siblings, 1 reply; 7+ messages in thread
From: Stefan Mavrodiev @ 2017-12-18  6:24 UTC (permalink / raw)
  To: Maxime Ripard
  Cc: Stefan Mavrodiev, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw,
	Rob Herring, Mark Rutland, Russell King, Chen-Yu Tsai,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM PORT, open list

On 12/15/2017 05:08 PM, Maxime Ripard wrote:
> Hi,
>
> On Thu, Dec 14, 2017 at 08:24:54AM +0200, Stefan Mavrodiev wrote:
>> On 12/13/2017 05:40 PM, Maxime Ripard wrote:
>>> Hi,
>>>
>>> On Wed, Dec 13, 2017 at 09:44:34AM +0200, Stefan Mavrodiev wrote:
>>>> Allwinner A10/A13/A20 SoCs have pinmux for spi0
>>>> on port C. The patch adds these pins in the respective
>>>> dts includes.
>>>>
>>>> Signed-off-by: Stefan Mavrodiev <stefan-kyXcfZUBQGPQT0dZR+AlfA@public.gmane.org>
>>> Do you have any boards that are using these?
>>>
>>> We won't merge that patch if there's no users for it.
>> A20-OLinuXino-Lime/Lime2 and A10-OLinuXino-Lime with spi flash.
>> For A13 we still doesn't have that option.
> If this bus is exposed on the headers, you can add those to the DT but
> leave them disabled if you want. Buf if there's no users of those
> nodes, our policy is not to merge them.
So basically I should resend the patch, enabling the those pins only for
sun4i and sun7i platform?
>
> Thanks!
> Maxime
>
Regards,
Stefan Mavrodiev

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH 1/1] arm: sunxi: Add alternative pins for spi0
       [not found]                 ` <ca648552-cefb-e19d-72cf-8b56e97b013d-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2017-12-18  9:28                   ` Maxime Ripard
       [not found]                     ` <20171218092814.n5ptd5mhvo4nkjgq-ZC1Zs529Oq4@public.gmane.org>
  0 siblings, 1 reply; 7+ messages in thread
From: Maxime Ripard @ 2017-12-18  9:28 UTC (permalink / raw)
  To: Stefan Mavrodiev
  Cc: Stefan Mavrodiev, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw,
	Rob Herring, Mark Rutland, Russell King, Chen-Yu Tsai,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM PORT, open list

[-- Attachment #1: Type: text/plain, Size: 1379 bytes --]

On Mon, Dec 18, 2017 at 08:24:21AM +0200, Stefan Mavrodiev wrote:
> On 12/15/2017 05:08 PM, Maxime Ripard wrote:
> > Hi,
> > 
> > On Thu, Dec 14, 2017 at 08:24:54AM +0200, Stefan Mavrodiev wrote:
> > > On 12/13/2017 05:40 PM, Maxime Ripard wrote:
> > > > Hi,
> > > > 
> > > > On Wed, Dec 13, 2017 at 09:44:34AM +0200, Stefan Mavrodiev wrote:
> > > > > Allwinner A10/A13/A20 SoCs have pinmux for spi0
> > > > > on port C. The patch adds these pins in the respective
> > > > > dts includes.
> > > > > 
> > > > > Signed-off-by: Stefan Mavrodiev <stefan-kyXcfZUBQGPQT0dZR+AlfA@public.gmane.org>
> > > > Do you have any boards that are using these?
> > > > 
> > > > We won't merge that patch if there's no users for it.
> > > A20-OLinuXino-Lime/Lime2 and A10-OLinuXino-Lime with spi flash.
> > > For A13 we still doesn't have that option.
> > If this bus is exposed on the headers, you can add those to the DT but
> > leave them disabled if you want. Buf if there's no users of those
> > nodes, our policy is not to merge them.
>
> So basically I should resend the patch, enabling the those pins only for
> sun4i and sun7i platform?

I'm not quite sure what you mean, but you should do something like
77df9d66b0b1ad01c685fd6341ce501493899658

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH 1/1] arm: sunxi: Add alternative pins for spi0
       [not found]                     ` <20171218092814.n5ptd5mhvo4nkjgq-ZC1Zs529Oq4@public.gmane.org>
@ 2017-12-18 11:00                       ` Stefan Mavrodiev
  0 siblings, 0 replies; 7+ messages in thread
From: Stefan Mavrodiev @ 2017-12-18 11:00 UTC (permalink / raw)
  To: Maxime Ripard
  Cc: Stefan Mavrodiev, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw,
	Rob Herring, Mark Rutland, Russell King, Chen-Yu Tsai,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM PORT, open list

On 12/18/2017 11:28 AM, Maxime Ripard wrote:
> On Mon, Dec 18, 2017 at 08:24:21AM +0200, Stefan Mavrodiev wrote:
>> On 12/15/2017 05:08 PM, Maxime Ripard wrote:
>>> Hi,
>>>
>>> On Thu, Dec 14, 2017 at 08:24:54AM +0200, Stefan Mavrodiev wrote:
>>>> On 12/13/2017 05:40 PM, Maxime Ripard wrote:
>>>>> Hi,
>>>>>
>>>>> On Wed, Dec 13, 2017 at 09:44:34AM +0200, Stefan Mavrodiev wrote:
>>>>>> Allwinner A10/A13/A20 SoCs have pinmux for spi0
>>>>>> on port C. The patch adds these pins in the respective
>>>>>> dts includes.
>>>>>>
>>>>>> Signed-off-by: Stefan Mavrodiev <stefan-kyXcfZUBQGPQT0dZR+AlfA@public.gmane.org>
>>>>> Do you have any boards that are using these?
>>>>>
>>>>> We won't merge that patch if there's no users for it.
>>>> A20-OLinuXino-Lime/Lime2 and A10-OLinuXino-Lime with spi flash.
>>>> For A13 we still doesn't have that option.
>>> If this bus is exposed on the headers, you can add those to the DT but
>>> leave them disabled if you want. Buf if there's no users of those
>>> nodes, our policy is not to merge them.
>> So basically I should resend the patch, enabling the those pins only for
>> sun4i and sun7i platform?
> I'm not quite sure what you mean, but you should do something like
> 77df9d66b0b1ad01c685fd6341ce501493899658
>
> Maxime
>
I guess, since this patch actually supports optional component, it 
shouldn't be applied.
(This is already commented here: 
https://patchwork.kernel.org/patch/10076721/ )

Thanks,
Stefan Mavrodiev

^ permalink raw reply	[flat|nested] 7+ messages in thread

end of thread, other threads:[~2017-12-18 11:00 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-12-13  7:44 [PATCH 1/1] arm: sunxi: Add alternative pins for spi0 Stefan Mavrodiev
     [not found] ` <1513151074-6888-1-git-send-email-stefan-kyXcfZUBQGPQT0dZR+AlfA@public.gmane.org>
2017-12-13 15:40   ` Maxime Ripard
     [not found]     ` <20171213154035.qc655iahjoeflftq-ZC1Zs529Oq4@public.gmane.org>
2017-12-14  6:24       ` Stefan Mavrodiev
     [not found]         ` <5f518e4b-e624-17c2-7e72-24ba930a1c15-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-12-15 15:08           ` Maxime Ripard
     [not found]             ` <20171215150823.jplgknururmkvp2t-ZC1Zs529Oq4@public.gmane.org>
2017-12-18  6:24               ` Stefan Mavrodiev
     [not found]                 ` <ca648552-cefb-e19d-72cf-8b56e97b013d-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-12-18  9:28                   ` Maxime Ripard
     [not found]                     ` <20171218092814.n5ptd5mhvo4nkjgq-ZC1Zs529Oq4@public.gmane.org>
2017-12-18 11:00                       ` Stefan Mavrodiev

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).