* [PATCH 1/3] dt-bindings: pwm-stm32-lp: add #pwm-cells
[not found] ` <1517492678-767-1-git-send-email-fabrice.gasnier-qxv4g6HH51o@public.gmane.org>
@ 2018-02-01 13:44 ` Fabrice Gasnier
2018-02-05 6:09 ` Rob Herring
2018-02-01 13:44 ` [PATCH 2/3] pwm: stm32: LPTimer: use 3 cells xlate Fabrice Gasnier
2018-02-01 13:44 ` [PATCH 3/3] ARM: dts: stm32: update pwm-cells for LPTimer on stm32h743 Fabrice Gasnier
2 siblings, 1 reply; 5+ messages in thread
From: Fabrice Gasnier @ 2018-02-01 13:44 UTC (permalink / raw)
To: thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, alexandre.torgue-qxv4g6HH51o
Cc: mark.rutland-5wv7dgnIgG8, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
mcoquelin.stm32-Re5JQEeQqe8AvxtiuMwx3w,
fabrice.gasnier-qxv4g6HH51o, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-pwm-u79uwXL29TY76Z2rM5mHXA
From: Gerald Baeza <gerald.baeza-qxv4g6HH51o@public.gmane.org>
STM32 Low-Power Timer supports generic 3 cells pwm to encode
PWM number, period and polarity.
Signed-off-by: Gerald Baeza <gerald.baeza-qxv4g6HH51o@public.gmane.org>
Signed-off-by: Fabrice Gasnier <fabrice.gasnier-qxv4g6HH51o@public.gmane.org>
---
Documentation/devicetree/bindings/pwm/pwm-stm32-lp.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/pwm/pwm-stm32-lp.txt b/Documentation/devicetree/bindings/pwm/pwm-stm32-lp.txt
index f8338d1..bd23302 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-stm32-lp.txt
+++ b/Documentation/devicetree/bindings/pwm/pwm-stm32-lp.txt
@@ -7,6 +7,8 @@ See ../mfd/stm32-lptimer.txt for details about the parent node.
Required parameters:
- compatible: Must be "st,stm32-pwm-lp".
+- #pwm-cells: Should be set to 3. This PWM chip uses the default 3 cells
+ bindings defined in pwm.txt.
Optional properties:
- pinctrl-names: Set to "default".
@@ -18,6 +20,7 @@ Example:
...
pwm {
compatible = "st,stm32-pwm-lp";
+ #pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&lppwm1_pins>;
};
--
1.9.1
--
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^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH 1/3] dt-bindings: pwm-stm32-lp: add #pwm-cells
2018-02-01 13:44 ` [PATCH 1/3] dt-bindings: pwm-stm32-lp: add #pwm-cells Fabrice Gasnier
@ 2018-02-05 6:09 ` Rob Herring
0 siblings, 0 replies; 5+ messages in thread
From: Rob Herring @ 2018-02-05 6:09 UTC (permalink / raw)
To: Fabrice Gasnier
Cc: thierry.reding, alexandre.torgue, mark.rutland, linux,
mcoquelin.stm32, devicetree, linux-arm-kernel, linux-kernel,
linux-pwm
On Thu, Feb 01, 2018 at 02:44:36PM +0100, Fabrice Gasnier wrote:
> From: Gerald Baeza <gerald.baeza@st.com>
>
> STM32 Low-Power Timer supports generic 3 cells pwm to encode
> PWM number, period and polarity.
>
> Signed-off-by: Gerald Baeza <gerald.baeza@st.com>
> Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
> ---
> Documentation/devicetree/bindings/pwm/pwm-stm32-lp.txt | 3 +++
> 1 file changed, 3 insertions(+)
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 2/3] pwm: stm32: LPTimer: use 3 cells xlate
[not found] ` <1517492678-767-1-git-send-email-fabrice.gasnier-qxv4g6HH51o@public.gmane.org>
2018-02-01 13:44 ` [PATCH 1/3] dt-bindings: pwm-stm32-lp: add #pwm-cells Fabrice Gasnier
@ 2018-02-01 13:44 ` Fabrice Gasnier
2018-02-01 13:44 ` [PATCH 3/3] ARM: dts: stm32: update pwm-cells for LPTimer on stm32h743 Fabrice Gasnier
2 siblings, 0 replies; 5+ messages in thread
From: Fabrice Gasnier @ 2018-02-01 13:44 UTC (permalink / raw)
To: thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, alexandre.torgue-qxv4g6HH51o
Cc: mark.rutland-5wv7dgnIgG8, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
mcoquelin.stm32-Re5JQEeQqe8AvxtiuMwx3w,
fabrice.gasnier-qxv4g6HH51o, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-pwm-u79uwXL29TY76Z2rM5mHXA
From: Gerald Baeza <gerald.baeza-qxv4g6HH51o@public.gmane.org>
STM32 Low-Power Timer supports generic 3 cells pwm to encode
PWM number, period and polarity.
Signed-off-by: Gerald Baeza <gerald.baeza-qxv4g6HH51o@public.gmane.org>
Signed-off-by: Fabrice Gasnier <fabrice.gasnier-qxv4g6HH51o@public.gmane.org>
---
drivers/pwm/pwm-stm32-lp.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/pwm/pwm-stm32-lp.c b/drivers/pwm/pwm-stm32-lp.c
index 1ac9e43..346b7bd 100644
--- a/drivers/pwm/pwm-stm32-lp.c
+++ b/drivers/pwm/pwm-stm32-lp.c
@@ -203,6 +203,8 @@ static int stm32_pwm_lp_probe(struct platform_device *pdev)
priv->chip.dev = &pdev->dev;
priv->chip.ops = &stm32_pwm_lp_ops;
priv->chip.npwm = 1;
+ priv->chip.of_xlate = of_pwm_xlate_with_flags;
+ priv->chip.of_pwm_n_cells = 3;
ret = pwmchip_add(&priv->chip);
if (ret < 0)
--
1.9.1
--
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^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 3/3] ARM: dts: stm32: update pwm-cells for LPTimer on stm32h743
[not found] ` <1517492678-767-1-git-send-email-fabrice.gasnier-qxv4g6HH51o@public.gmane.org>
2018-02-01 13:44 ` [PATCH 1/3] dt-bindings: pwm-stm32-lp: add #pwm-cells Fabrice Gasnier
2018-02-01 13:44 ` [PATCH 2/3] pwm: stm32: LPTimer: use 3 cells xlate Fabrice Gasnier
@ 2018-02-01 13:44 ` Fabrice Gasnier
2 siblings, 0 replies; 5+ messages in thread
From: Fabrice Gasnier @ 2018-02-01 13:44 UTC (permalink / raw)
To: thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, alexandre.torgue-qxv4g6HH51o
Cc: mark.rutland-5wv7dgnIgG8, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
mcoquelin.stm32-Re5JQEeQqe8AvxtiuMwx3w,
fabrice.gasnier-qxv4g6HH51o, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-pwm-u79uwXL29TY76Z2rM5mHXA
LPTimer pwm cells should be updated to 3, to allow initialization of
channel, period and polarity.
Signed-off-by: Fabrice Gasnier <fabrice.gasnier-qxv4g6HH51o@public.gmane.org>
---
arch/arm/boot/dts/stm32h743.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi
index bbfcbac..40d7d76 100644
--- a/arch/arm/boot/dts/stm32h743.dtsi
+++ b/arch/arm/boot/dts/stm32h743.dtsi
@@ -85,6 +85,7 @@
pwm {
compatible = "st,stm32-pwm-lp";
+ #pwm-cells = <3>;
status = "disabled";
};
@@ -238,6 +239,7 @@
pwm {
compatible = "st,stm32-pwm-lp";
+ #pwm-cells = <3>;
status = "disabled";
};
@@ -264,6 +266,7 @@
pwm {
compatible = "st,stm32-pwm-lp";
+ #pwm-cells = <3>;
status = "disabled";
};
@@ -285,6 +288,7 @@
pwm {
compatible = "st,stm32-pwm-lp";
+ #pwm-cells = <3>;
status = "disabled";
};
};
@@ -300,6 +304,7 @@
pwm {
compatible = "st,stm32-pwm-lp";
+ #pwm-cells = <3>;
status = "disabled";
};
};
--
1.9.1
--
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^ permalink raw reply related [flat|nested] 5+ messages in thread