[PATCH 1/2] doc: fpga: Add reset bridge support

[PATCH 1/2] doc: fpga: Add reset bridge support

[Shubhrajyoti Datta]

Add reset bridge support. Once this bridge is enabled.
The reset line(s) will be toggled. Generally it will be
called after the bitstream load to reset the PL.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
---
 .../devicetree/bindings/fpga/xlnx,rst-bridge.txt   | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,rst-bridge.txt

diff --git a/Documentation/devicetree/bindings/fpga/xlnx,rst-bridge.txt b/Documentation/devicetree/bindings/fpga/xlnx,rst-bridge.txt
new file mode 100644
index 0000000..6f1bfc2
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/xlnx,rst-bridge.txt
@@ -0,0 +1,22 @@
+Xilinx fpga reset bridge
+
+The Xilinx reset bridge toggles the reset line to the PL
+in Zynqmp Ultrascale plus.
+
+
+Required properties:
+- compatible   : Should contain "xlnx,rst-bridge"
+- reset                : reset phandles
+
+Optional properties:
+- bridge-enable                : 0 if driver should disable bridge at startup
+                         1 if driver should enable bridge at startup
+                         Default is to leave bridge in current state.
+
+See Documentation/devicetree/bindings/fpga/fpga-region.txt for generic bindings.
+
+Example:
+fpga_rst_bridge: fpga_rst_bridge {
+       compatible = "xlnx,rst-bridge";
+       resets = <&rst 115>;
+};
--
2.1.1

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Re: [PATCH 1/2] doc: fpga: Add reset bridge support

[Shubhrajyoti Datta]

Hi ,


On Tue, Feb 20, 2018 at 2:10 PM, Shubhrajyoti Datta
<shubhrajyoti.datta@xilinx.com> wrote:
> Add reset bridge support. Once this bridge is enabled.
> The reset line(s) will be toggled. Generally it will be
> called after the bitstream load to reset the PL.
>
> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
> ---
>  .../devicetree/bindings/fpga/xlnx,rst-bridge.txt   | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,rst-bridge.txt
>
> diff --git a/Documentation/devicetree/bindings/fpga/xlnx,rst-bridge.txt b/Documentation/devicetree/bindings/fpga/xlnx,rst-bridge.txt
> new file mode 100644
> index 0000000..6f1bfc2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/fpga/xlnx,rst-bridge.txt
> @@ -0,0 +1,22 @@
> +Xilinx fpga reset bridge
> +
> +The Xilinx reset bridge toggles the reset line to the PL
> +in Zynqmp Ultrascale plus.
> +
> +
> +Required properties:
> +- compatible   : Should contain "xlnx,rst-bridge"
> +- reset                : reset phandles
> +
> +Optional properties:
> +- bridge-enable                : 0 if driver should disable bridge at startup
> +                         1 if driver should enable bridge at startup
> +                         Default is to leave bridge in current state.
> +
> +See Documentation/devicetree/bindings/fpga/fpga-region.txt for generic bindings.
> +
> +Example:
> +fpga_rst_bridge: fpga_rst_bridge {
> +       compatible = "xlnx,rst-bridge";
> +       resets = <&rst 115>;
> +};
> --
> 2.1.1
>
> This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.
Please ignore will resend.

[PATCH 2/2] fpga: reset bridge: Add the reset bridge

[Shubhrajyoti Datta]

Adds the reset bridge. After the bitstream load the reset
bridge helps in reseting the programable logic. The
reset lines depends on the design.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
---
 drivers/fpga/Kconfig             |   8 ++++
 drivers/fpga/Makefile            |   1 +
 drivers/fpga/xilinx-rst-bridge.c | 100 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 109 insertions(+)
 create mode 100644 drivers/fpga/xilinx-rst-bridge.c

diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index ad5448f..752a907 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -117,4 +117,12 @@ config XILINX_PR_DECOUPLER
          region of the FPGA from the busses while that region is
          being reprogrammed during partial reconfig.

+config XILINX_RST_BRIDGE
+       tristate "Xilinx Reset bridge"
+       depends on FPGA_BRIDGE
+       help
+         Say Y to enable drivers for Xilinx Reset bridge.
+         After writing the bitstream there has to be a reset.
+         The reset lines are design specific.
+
 endif # FPGA
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index f98dcf1..c1b0d13 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_FPGA_BRIDGE)             += fpga-bridge.o
 obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE)      += altera-hps2fpga.o altera-fpga2sdram.o
 obj-$(CONFIG_ALTERA_FREEZE_BRIDGE)     += altera-freeze-bridge.o
 obj-$(CONFIG_XILINX_PR_DECOUPLER)      += xilinx-pr-decoupler.o
+obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA)     += xilinx-rst-bridge.o

 # High Level Interfaces
 obj-$(CONFIG_FPGA_REGION)              += fpga-region.o
diff --git a/drivers/fpga/xilinx-rst-bridge.c b/drivers/fpga/xilinx-rst-bridge.c
new file mode 100644
index 0000000..8062283
--- /dev/null
+++ b/drivers/fpga/xilinx-rst-bridge.c
@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx FPGA reset bridge.
+ * Copyright (c) 2018 Xilinx Inc.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/fpga/fpga-bridge.h>
+#include <linux/reset.h>
+
+struct xlnx_rst_bridge_priv {
+       struct device *dev;
+       bool enable;
+};
+
+static int xlnx_rst_bridge_enable_set(struct fpga_bridge *bridge, bool enable)
+{
+       struct xlnx_rst_bridge_priv *priv = bridge->priv;
+       struct device *dev = priv->dev;
+       struct reset_control *rstc;
+       int ret = 0;
+
+       if (enable) {
+               rstc = of_reset_control_array_get(dev->of_node, false, false);
+               if (IS_ERR(rstc))
+                       return PTR_ERR(rstc);
+
+               ret = reset_control_reset(rstc);
+
+               reset_control_put(rstc);
+
+               if (ret)
+                       dev_err(dev, "Reset failed\n");
+       } else {
+               dev_dbg(dev, "Bridge disabled\n");
+       }
+
+       if (!ret)
+               priv->enable = enable;
+
+       return ret;
+}
+
+static int xlnx_rst_bridge_enable_show(struct fpga_bridge *bridge)
+{
+       struct xlnx_rst_bridge_priv *priv = bridge->priv;
+
+       return priv->enable;
+}
+
+static struct fpga_bridge_ops xlnx_rst_bridge_ops = {
+       .enable_set = xlnx_rst_bridge_enable_set,
+       .enable_show = xlnx_rst_bridge_enable_show,
+};
+
+static int xlnx_rst_bridge_probe(struct platform_device *pdev)
+{
+       struct xlnx_rst_bridge_priv *priv;
+       struct device *dev = &pdev->dev;
+
+       priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+       if (!priv)
+               return -ENOMEM;
+
+       priv->dev = dev;
+
+       return fpga_bridge_register(dev, "xlnx_rst_bridge",
+                                   &xlnx_rst_bridge_ops, priv);
+}
+
+static int xlnx_rst_bridge_remove(struct platform_device *pdev)
+{
+       fpga_bridge_unregister(&pdev->dev);
+
+       return 0;
+}
+
+static const struct of_device_id xlnx_rst_bridge_of_match[] = {
+       { .compatible = "xlnx,rst-bridge", },
+       {},
+};
+MODULE_DEVICE_TABLE(of, xlnx_rst_bridge_of_match);
+
+static struct platform_driver xlnx_rst_bridge_driver = {
+       .probe = xlnx_rst_bridge_probe,
+       .remove = xlnx_rst_bridge_remove,
+       .driver = {
+               .name   = "xlnx_rst_bridge",
+               .of_match_table = of_match_ptr(xlnx_rst_bridge_of_match),
+       },
+};
+
+module_platform_driver(xlnx_rst_bridge_driver);
+
+MODULE_DESCRIPTION("Xilinx reset Bridge");
+MODULE_AUTHOR("Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>");
+MODULE_LICENSE("GPL v2");
--
2.1.1

This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.

[PATCH 1/2] doc: fpga: Add reset bridge support

[Shubhrajyoti Datta]

Add reset bridge support. Once this bridge is enabled.
The reset line(s) will be toggled. Generally it will be
called after the bitstream load to reset the PL.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
---
 .../devicetree/bindings/fpga/xlnx,rst-bridge.txt   | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,rst-bridge.txt

diff --git a/Documentation/devicetree/bindings/fpga/xlnx,rst-bridge.txt b/Documentation/devicetree/bindings/fpga/xlnx,rst-bridge.txt
new file mode 100644
index 0000000..6f1bfc2
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/xlnx,rst-bridge.txt
@@ -0,0 +1,22 @@
+Xilinx fpga reset bridge
+
+The Xilinx reset bridge toggles the reset line to the PL
+in Zynqmp Ultrascale plus.
+
+
+Required properties:
+- compatible   : Should contain "xlnx,rst-bridge"
+- reset                : reset phandles
+
+Optional properties:
+- bridge-enable                : 0 if driver should disable bridge at startup
+                         1 if driver should enable bridge at startup
+                         Default is to leave bridge in current state.
+
+See Documentation/devicetree/bindings/fpga/fpga-region.txt for generic bindings.
+
+Example:
+fpga_rst_bridge: fpga_rst_bridge {
+       compatible = "xlnx,rst-bridge";
+       resets = <&rst 115>;
+};
--
2.1.1

This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.

[PATCH 1/2] doc: fpga: Add reset bridge support

[shubhrajyoti.datta]

From: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>

Add reset bridge support. Once this bridge is enabled.
The reset line(s) will be toggled. Generally it will be
called after the bitstream load to reset the PL.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
---
 .../devicetree/bindings/fpga/xlnx,rst-bridge.txt   | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,rst-bridge.txt

diff --git a/Documentation/devicetree/bindings/fpga/xlnx,rst-bridge.txt b/Documentation/devicetree/bindings/fpga/xlnx,rst-bridge.txt
new file mode 100644
index 0000000..6f1bfc2
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/xlnx,rst-bridge.txt
@@ -0,0 +1,22 @@
+Xilinx fpga reset bridge
+
+The Xilinx reset bridge toggles the reset line to the PL
+in Zynqmp Ultrascale plus.
+
+
+Required properties:
+- compatible	: Should contain "xlnx,rst-bridge"
+- reset		: reset phandles
+
+Optional properties:
+- bridge-enable		: 0 if driver should disable bridge at startup
+			  1 if driver should enable bridge at startup
+			  Default is to leave bridge in current state.
+
+See Documentation/devicetree/bindings/fpga/fpga-region.txt for generic bindings.
+
+Example:
+fpga_rst_bridge: fpga_rst_bridge {
+	compatible = "xlnx,rst-bridge";
+	resets = <&rst 115>;
+};
-- 
2.1.1

Re: [PATCH 1/2] doc: fpga: Add reset bridge support

[Moritz Fischer]

[-- Attachment #1: Type: text/plain, Size: 1854 bytes --]

On Wed, Feb 21, 2018 at 10:23:45AM +0530, shubhrajyoti.datta@gmail.com wrote:
> From: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
> 
> Add reset bridge support. Once this bridge is enabled.
> The reset line(s) will be toggled. Generally it will be
> called after the bitstream load to reset the PL.
> 
> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
> ---
>  .../devicetree/bindings/fpga/xlnx,rst-bridge.txt   | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,rst-bridge.txt
> 
> diff --git a/Documentation/devicetree/bindings/fpga/xlnx,rst-bridge.txt b/Documentation/devicetree/bindings/fpga/xlnx,rst-bridge.txt
> new file mode 100644
> index 0000000..6f1bfc2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/fpga/xlnx,rst-bridge.txt
> @@ -0,0 +1,22 @@
> +Xilinx fpga reset bridge
> +
> +The Xilinx reset bridge toggles the reset line to the PL
> +in Zynqmp Ultrascale plus.

Out of curiosity do you have a reference in the TRM where this is
explained?
> +
> +
> +Required properties:
> +- compatible	: Should contain "xlnx,rst-bridge"
> +- reset		: reset phandles
> +
> +Optional properties:
> +- bridge-enable		: 0 if driver should disable bridge at startup
> +			  1 if driver should enable bridge at startup
> +			  Default is to leave bridge in current state.
> +
> +See Documentation/devicetree/bindings/fpga/fpga-region.txt for generic bindings.

Since this would be the 5th? time of replicating this I sent out a patch
[1] to consolidate this paragraph into a single file.

Feel free to add this to your series and replace the above with

See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.

Thanks

Moritz

[1] https://lkml.org/lkml/2018/2/21/1099

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Re: [PATCH 1/2] doc: fpga: Add reset bridge support

[Shubhrajyoti Datta]

Hi Moritz,

On Wed, Feb 21, 2018 at 11:14 PM, Moritz Fischer <mdf@kernel.org> wrote:
> On Wed, Feb 21, 2018 at 10:23:45AM +0530, shubhrajyoti.datta@gmail.com wrote:
>> From: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
>>
>> Add reset bridge support. Once this bridge is enabled.
>> The reset line(s) will be toggled. Generally it will be
>> called after the bitstream load to reset the PL.
>>
>> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
>> ---
>>  .../devicetree/bindings/fpga/xlnx,rst-bridge.txt   | 22 ++++++++++++++++++++++
>>  1 file changed, 22 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,rst-bridge.txt
>>
>> diff --git a/Documentation/devicetree/bindings/fpga/xlnx,rst-bridge.txt b/Documentation/devicetree/bindings/fpga/xlnx,rst-bridge.txt
>> new file mode 100644
>> index 0000000..6f1bfc2
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/fpga/xlnx,rst-bridge.txt
>> @@ -0,0 +1,22 @@
>> +Xilinx fpga reset bridge
>> +
>> +The Xilinx reset bridge toggles the reset line to the PL
>> +in Zynqmp Ultrascale plus.
>
> Out of curiosity do you have a reference in the TRM where this is
> explained?

https://www.xilinx.com/support/documentation/ip_documentation/zynq_ultra_ps_e/v2_0/pg201-zynq-ultrascale-plus-processing-system.pdf

section :Fabric Reset Enable
>> +
>> +
>> +Required properties:
>> +- compatible : Should contain "xlnx,rst-bridge"
>> +- reset              : reset phandles
>> +
>> +Optional properties:
>> +- bridge-enable              : 0 if driver should disable bridge at startup
>> +                       1 if driver should enable bridge at startup
>> +                       Default is to leave bridge in current state.
>> +
>> +See Documentation/devicetree/bindings/fpga/fpga-region.txt for generic bindings.
>
> Since this would be the 5th? time of replicating this I sent out a patch
> [1] to consolidate this paragraph into a single file.
>
> Feel free to add this to your series and replace the above with
>
> See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
Will do

>
> Thanks
>
> Moritz
>
> [1] https://lkml.org/lkml/2018/2/21/1099