* [PATCH v2 0/2] Introduce STM32 USB PHY Controller driver
@ 2018-03-01 15:30 Amelie Delaunay
2018-03-01 15:30 ` [PATCH v2 1/2] dt-bindings: phy: add support for STM32 USB PHY Controller (USBPHYC) Amelie Delaunay
2018-03-01 15:30 ` [PATCH v2 2/2] phy: stm32: " Amelie Delaunay
0 siblings, 2 replies; 5+ messages in thread
From: Amelie Delaunay @ 2018-03-01 15:30 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Kishon Vijay Abraham I,
Alexandre Torgue, Maxime Coquelin
Cc: devicetree, Amelie Delaunay, linux-kernel, linux-arm-kernel
This patchset adds support for STMicroelectronics STM32 USB PHY Controller
(USBPHYC) which is embedded in STM32MP1 SoC.
The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
switch that selects either USB OTG controller or USB Host controller for the
second PHY port.
---
Changes in v2:
* Update diagram to better describe the context.
* Change boolean dt propery st,port2-switch-to-host into u32 st,utmi-switch.
* Silent phy creation failure in case of -EPROBE_DEFER.
Amelie Delaunay (2):
dt-bindings: phy: add support for STM32 USB PHY Controller (USBPHYC)
phy: stm32: add support for STM32 USB PHY Controller (USBPHYC)
.../devicetree/bindings/phy/phy-stm32-usbphyc.txt | 46 +++
drivers/phy/st/Kconfig | 14 +
drivers/phy/st/Makefile | 1 +
drivers/phy/st/phy-stm32-usbphyc.c | 382 +++++++++++++++++++++
4 files changed, 443 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt
create mode 100644 drivers/phy/st/phy-stm32-usbphyc.c
--
2.7.4
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2 1/2] dt-bindings: phy: add support for STM32 USB PHY Controller (USBPHYC)
2018-03-01 15:30 [PATCH v2 0/2] Introduce STM32 USB PHY Controller driver Amelie Delaunay
@ 2018-03-01 15:30 ` Amelie Delaunay
2018-03-02 6:02 ` Kishon Vijay Abraham I
2018-03-01 15:30 ` [PATCH v2 2/2] phy: stm32: " Amelie Delaunay
1 sibling, 1 reply; 5+ messages in thread
From: Amelie Delaunay @ 2018-03-01 15:30 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Kishon Vijay Abraham I,
Alexandre Torgue, Maxime Coquelin
Cc: devicetree, Amelie Delaunay, linux-kernel, linux-arm-kernel
This patch adds the device tree bindings description for STM32 USBPHYC
(USB PHY Controller).
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
---
.../devicetree/bindings/phy/phy-stm32-usbphyc.txt | 46 ++++++++++++++++++++++
1 file changed, 46 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt
diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt
new file mode 100644
index 0000000..1ad3893
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt
@@ -0,0 +1,46 @@
+STMicroelectronics STM32 USB HS PHY controller
+
+The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
+switch. It controls PHY configuration and status, and the UTMI+ switch that
+selects either OTG or HOST controller for the second PHY port. It also sets
+PLL configuration.
+
+USBPHYC
+ |_ PLL
+ |
+ |_ PHY port#1 _________________ HOST controller
+ | _ |
+ | / 1|________________|
+ |_ PHY port#2 ----| |________________
+ | \_0| |
+ |_ UTMI switch_______| OTG controller
+
+
+Required properties:
+- compatible: must be "st,stm32mp1-usbphyc"
+- reg: address and length of the usb phy control register set
+- clocks: phandle + clock specifier for the PLL phy clock
+- phy-supply: from the generic phy bindings, phandle to the regulator
+ providing 3V3 power to the PHY, see phy-bindings.txt
+- vdda1v1-supply: phandle to the regulator providing 1V1 power to the PHY
+- vdda1v8-supply: phandle to the regulator providing 1V8 power to the PHY
+
+Optional properties:
+- assigned-clocks: phandle + clock specifier for the PLL phy clock
+- assigned-clock-parents: the PLL phy clock parent
+- resets: phandle + reset specifier
+- st,utmi-switch: should be <0> or <1>, to select USB controller for PHY
+ port#2. If not specified, 0 is the default selection.
+
+
+Example:
+ usbphyc: usb-phy@5a006000 {
+ compatible = "st,stm32mp1-usbphyc";
+ reg = <0x5a006000 0x1000>;
+ clocks = <&rcc_clk USBPHY_K>;
+ resets = <&rcc_rst USBPHY_R>;
+ st,utmi-switch = <1>;
+ phy-supply = <&vdd_usb>;
+ vdda1v1-supply = <®11>;
+ vdda1v8-supply = <®18>
+ };
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v2 2/2] phy: stm32: add support for STM32 USB PHY Controller (USBPHYC)
2018-03-01 15:30 [PATCH v2 0/2] Introduce STM32 USB PHY Controller driver Amelie Delaunay
2018-03-01 15:30 ` [PATCH v2 1/2] dt-bindings: phy: add support for STM32 USB PHY Controller (USBPHYC) Amelie Delaunay
@ 2018-03-01 15:30 ` Amelie Delaunay
1 sibling, 0 replies; 5+ messages in thread
From: Amelie Delaunay @ 2018-03-01 15:30 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Kishon Vijay Abraham I,
Alexandre Torgue, Maxime Coquelin
Cc: devicetree, linux-arm-kernel, linux-kernel, Amelie Delaunay
This patch adds phy transceiver driver for STM32 USB PHY Controller
(USBPHYC) that provides dual port High-Speed phy for OTG (single port)
and EHCI/OHCI host controller (two ports).
One port of the phy is shared between the two USB controllers through
a UTMI+ switch.
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
---
drivers/phy/st/Kconfig | 14 ++
drivers/phy/st/Makefile | 1 +
drivers/phy/st/phy-stm32-usbphyc.c | 382 +++++++++++++++++++++++++++++++++++++
3 files changed, 397 insertions(+)
create mode 100644 drivers/phy/st/phy-stm32-usbphyc.c
diff --git a/drivers/phy/st/Kconfig b/drivers/phy/st/Kconfig
index 0814d3f..609719b 100644
--- a/drivers/phy/st/Kconfig
+++ b/drivers/phy/st/Kconfig
@@ -31,3 +31,17 @@ config PHY_STIH407_USB
help
Enable this support to enable the picoPHY device used by USB2
and USB3 controllers on STMicroelectronics STiH407 SoC families.
+
+config PHY_STM32_USBPHYC
+ tristate "STMicroelectronics STM32 USB HS PHY Controller driver"
+ depends on ARCH_STM32 || COMPILE_TEST
+ select GENERIC_PHY
+ help
+ Enable this to support the High-Speed USB transceivers that are part
+ of some STMicroelectronics STM32 SoCs.
+
+ This driver controls the entire USB PHY block: the USB PHY controller
+ (USBPHYC) and the two 8-bit wide UTMI+ interfaces. First interface is
+ used by an HS USB Host controller, and the second one is shared
+ between an HS USB OTG controller and an HS USB Host controller,
+ selected by a USB switch.
diff --git a/drivers/phy/st/Makefile b/drivers/phy/st/Makefile
index e2adfe2..c0091ad 100644
--- a/drivers/phy/st/Makefile
+++ b/drivers/phy/st/Makefile
@@ -2,3 +2,4 @@ obj-$(CONFIG_PHY_MIPHY28LP) += phy-miphy28lp.o
obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o
obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o
obj-$(CONFIG_PHY_STIH407_USB) += phy-stih407-usb.o
+obj-$(CONFIG_PHY_STM32_USBPHYC) += phy-stm32-usbphyc.o
diff --git a/drivers/phy/st/phy-stm32-usbphyc.c b/drivers/phy/st/phy-stm32-usbphyc.c
new file mode 100644
index 0000000..e1179ce
--- /dev/null
+++ b/drivers/phy/st/phy-stm32-usbphyc.c
@@ -0,0 +1,382 @@
+// SPDX-Licence-Identifier: GPL-2.0
+/*
+ * STMicroelectronics STM32 USB PHY Controller driver
+ *
+ * Copyright (C) 2018 STMicroelectronics
+ * Author(s): Amelie Delaunay <amelie.delaunay@st.com>.
+ */
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/phy/phy.h>
+#include <linux/reset.h>
+
+#define STM32_USBPHYC_PLL 0x0
+#define STM32_USBPHYC_MISC 0x8
+#define STM32_USBPHYC_VERSION 0x3F4
+
+/* STM32_USBPHYC_PLL bit fields */
+#define PLLNDIV GENMASK(6, 0)
+#define PLLFRACIN GENMASK(25, 10)
+#define PLLEN BIT(26)
+#define PLLSTRB BIT(27)
+#define PLLSTRBYP BIT(28)
+#define PLLFRACCTL BIT(29)
+#define PLLDITHEN0 BIT(30)
+#define PLLDITHEN1 BIT(31)
+
+/* STM32_USBPHYC_MISC bit fields */
+#define SWITHOST BIT(0)
+
+/* STM32_USBPHYC_VERSION bit fields */
+#define MINREV GENMASK(3, 0)
+#define MAJREV GENMASK(7, 4)
+
+#define MAX_PHYS 2
+
+static const char * const stm32_usbphyc_supply_names[] = {
+ "vdda1v1", /* 1V1 */
+ "vdda1v8", /* 1V8 */
+};
+
+#define NUM_SUPPLIES ARRAY_SIZE(stm32_usbphyc_supply_names)
+
+#define PLL_LOCK_TIME_US 100
+#define PLL_PWR_DOWN_TIME_US 5
+#define PLL_FVCO 2880 /* in MHz */
+#define PLL_INFF_MIN_RATE 19200000 /* in Hz */
+#define PLL_INFF_MAX_RATE 38400000 /* in Hz */
+
+struct pll_params {
+ u8 ndiv;
+ u16 frac;
+};
+
+struct stm32_usbphyc {
+ struct device *dev;
+ void __iomem *base;
+ struct clk *clk;
+ struct reset_control *rst;
+ struct regulator_bulk_data supplies[NUM_SUPPLIES];
+ struct stm32_usbphyc_phy {
+ struct phy *phy;
+ int index;
+ bool init;
+ } phys[MAX_PHYS];
+};
+
+static inline struct stm32_usbphyc *
+to_usbphyc(struct stm32_usbphyc_phy *usbphyc_phy)
+{
+ return container_of(usbphyc_phy, struct stm32_usbphyc,
+ phys[usbphyc_phy->index]);
+}
+
+static inline void stm32_usbphyc_set_bits(void __iomem *reg, u32 bits)
+{
+ writel_relaxed(readl_relaxed(reg) | bits, reg);
+}
+
+static inline void stm32_usbphyc_clr_bits(void __iomem *reg, u32 bits)
+{
+ writel_relaxed(readl_relaxed(reg) & ~bits, reg);
+}
+
+void stm32_usbphyc_get_pll_params(u32 clk_rate, struct pll_params *pll_params)
+{
+ unsigned long long fvco, ndiv, frac;
+
+ /* _
+ * | FVCO = INFF*2*(NDIV + FRACT/2^16) when DITHER_DISABLE[1] = 1
+ * | FVCO = 2880MHz
+ * <
+ * | NDIV = integer part of input bits to set the LDF
+ * |_FRACT = fractional part of input bits to set the LDF
+ * => PLLNDIV = integer part of (FVCO / (INFF*2))
+ * => PLLFRACIN = fractional part of(FVCO / INFF*2) * 2^16
+ * <=> PLLFRACIN = ((FVCO / (INFF*2)) - PLLNDIV) * 2^16
+ */
+ fvco = (unsigned long long)PLL_FVCO * 1000000; /* In Hz */
+
+ ndiv = fvco;
+ do_div(ndiv, (clk_rate * 2));
+ pll_params->ndiv = (u8)ndiv;
+
+ frac = fvco * (1 << 16);
+ do_div(frac, (clk_rate * 2));
+ frac = frac - (ndiv * (1 << 16));
+ pll_params->frac = (u16)frac;
+}
+
+static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
+{
+ struct pll_params pll_params;
+ u32 clk_rate = clk_get_rate(usbphyc->clk);
+ u32 ndiv, frac;
+ u32 usbphyc_pll;
+
+ if ((clk_rate < PLL_INFF_MIN_RATE) || (clk_rate > PLL_INFF_MAX_RATE)) {
+ dev_err(usbphyc->dev, "input clk freq (%dHz) out of range\n",
+ clk_rate);
+ return -EINVAL;
+ }
+
+ stm32_usbphyc_get_pll_params(clk_rate, &pll_params);
+ ndiv = FIELD_PREP(PLLNDIV, pll_params.ndiv);
+ frac = FIELD_PREP(PLLFRACIN, pll_params.frac);
+
+ usbphyc_pll = PLLDITHEN1 | PLLDITHEN0 | PLLSTRBYP | ndiv;
+
+ if (pll_params.frac)
+ usbphyc_pll |= PLLFRACCTL | frac;
+
+ writel_relaxed(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL);
+
+ dev_dbg(usbphyc->dev, "input clk freq=%dHz, ndiv=%lu, frac=%lu\n",
+ clk_rate, FIELD_GET(PLLNDIV, usbphyc_pll),
+ FIELD_GET(PLLFRACIN, usbphyc_pll));
+
+ return 0;
+}
+
+static bool stm32_usbphyc_is_init(struct stm32_usbphyc *usbphyc)
+{
+ int i;
+
+ for (i = 0; i < MAX_PHYS; i++) {
+ if (usbphyc->phys[i].init)
+ return true;
+ }
+
+ return false;
+}
+
+static int stm32_usbphyc_phy_init(struct phy *phy)
+{
+ struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
+ struct stm32_usbphyc *usbphyc = to_usbphyc(usbphyc_phy);
+ void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
+ bool pllen = !!(readl_relaxed(pll_reg) & PLLEN);
+ int ret;
+
+ /* Check if one phy port has already configured the pll */
+ if (pllen && stm32_usbphyc_is_init(usbphyc))
+ goto initialized;
+
+ if (pllen) {
+ stm32_usbphyc_clr_bits(pll_reg, PLLEN);
+ udelay(PLL_PWR_DOWN_TIME_US);
+ }
+
+ ret = stm32_usbphyc_pll_init(usbphyc);
+ if (ret)
+ return ret;
+
+ stm32_usbphyc_set_bits(pll_reg, PLLEN);
+
+ /* Wait for maximum lock time */
+ udelay(PLL_LOCK_TIME_US);
+
+ if (!(readl_relaxed(pll_reg) & PLLEN)) {
+ dev_err(usbphyc->dev, "PLLEN not set\n");
+ return -EIO;
+ }
+
+initialized:
+ usbphyc_phy->init = true;
+
+ return 0;
+}
+
+static int stm32_usbphyc_phy_exit(struct phy *phy)
+{
+ struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
+ struct stm32_usbphyc *usbphyc = to_usbphyc(usbphyc_phy);
+ void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
+
+ usbphyc_phy->init = false;
+
+ /* Check if other phy port requires pllen */
+ if (stm32_usbphyc_is_init(usbphyc))
+ return 0;
+
+ stm32_usbphyc_clr_bits(pll_reg, PLLEN);
+
+ /* Wait for minimum width of powerdown pulse (ENABLE = Low) */
+ udelay(PLL_PWR_DOWN_TIME_US);
+
+ if (readl_relaxed(pll_reg) & PLLEN) {
+ dev_err(usbphyc->dev, "PLL not reset\n");
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int stm32_usbphyc_phy_power_on(struct phy *phy)
+{
+ struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
+ struct stm32_usbphyc *usbphyc = to_usbphyc(usbphyc_phy);
+
+ return regulator_bulk_enable(NUM_SUPPLIES, usbphyc->supplies);
+}
+
+static int stm32_usbphyc_phy_power_off(struct phy *phy)
+{
+ struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
+ struct stm32_usbphyc *usbphyc = to_usbphyc(usbphyc_phy);
+
+ return regulator_bulk_disable(NUM_SUPPLIES, usbphyc->supplies);
+}
+
+static const struct phy_ops stm32_usbphyc_phy_ops = {
+ .init = stm32_usbphyc_phy_init,
+ .exit = stm32_usbphyc_phy_exit,
+ .power_on = stm32_usbphyc_phy_power_on,
+ .power_off = stm32_usbphyc_phy_power_off,
+ .owner = THIS_MODULE,
+};
+
+static struct phy *stm32_usbphyc_of_xlate(struct device *dev,
+ struct of_phandle_args *args)
+{
+ struct stm32_usbphyc *usbphyc = dev_get_drvdata(dev);
+
+ if (args->args[0] >= MAX_PHYS)
+ return ERR_PTR(-ENODEV);
+
+ return usbphyc->phys[args->args[0]].phy;
+}
+
+static int stm32_usbphyc_probe(struct platform_device *pdev)
+{
+ struct stm32_usbphyc *usbphyc;
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct resource *res;
+ struct phy_provider *phy_provider;
+ u32 utmi_switch, version;
+ int i, ret;
+
+ usbphyc = devm_kzalloc(dev, sizeof(*usbphyc), GFP_KERNEL);
+ if (!usbphyc)
+ return -ENOMEM;
+ usbphyc->dev = dev;
+ dev_set_drvdata(dev, usbphyc);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ usbphyc->base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(usbphyc->base))
+ return PTR_ERR(usbphyc->base);
+
+ usbphyc->clk = devm_clk_get(dev, 0);
+ if (IS_ERR(usbphyc->clk)) {
+ ret = PTR_ERR(usbphyc->clk);
+ dev_err(dev, "clk get failed: %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(usbphyc->clk);
+ if (ret) {
+ dev_err(dev, "clk enable failed: %d\n", ret);
+ return ret;
+ }
+
+ for (i = 0; i < NUM_SUPPLIES; i++)
+ usbphyc->supplies[i].supply = stm32_usbphyc_supply_names[i];
+
+ ret = devm_regulator_bulk_get(dev, NUM_SUPPLIES, usbphyc->supplies);
+ if (ret) {
+ if (ret != -EPROBE_DEFER)
+ dev_err(dev, "failed to get regulators: %d\n", ret);
+ goto clk_disable;
+ }
+
+ for (i = 0; i < MAX_PHYS; i++) {
+ struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + i;
+
+ usbphyc_phy->phy = devm_phy_create(dev, NULL,
+ &stm32_usbphyc_phy_ops);
+ if (IS_ERR(usbphyc_phy->phy)) {
+ ret = PTR_ERR(usbphyc_phy->phy);
+ if (ret != -EPROBE_DEFER)
+ dev_err(dev,
+ "failed to create phy%d: %d\n", i, ret);
+ goto clk_disable;
+ }
+
+ usbphyc_phy->index = i;
+ usbphyc_phy->init = false;
+ phy_set_bus_width(usbphyc_phy->phy, 8);
+ phy_set_drvdata(usbphyc_phy->phy, usbphyc_phy);
+ }
+
+ usbphyc->rst = devm_reset_control_get(dev, 0);
+ if (!IS_ERR(usbphyc->rst)) {
+ reset_control_assert(usbphyc->rst);
+ udelay(2);
+ reset_control_deassert(usbphyc->rst);
+ }
+
+ phy_provider = devm_of_phy_provider_register(dev,
+ stm32_usbphyc_of_xlate);
+ if (IS_ERR(phy_provider)) {
+ ret = PTR_ERR(phy_provider);
+ dev_err(dev, "failed to register phy provider: %d\n", ret);
+ goto clk_disable;
+ }
+
+ /* Check if need to configure utmi switch */
+ ret = of_property_read_u32(np, "st,utmi-switch", &utmi_switch);
+ if (ret && ret != -EINVAL) {
+ dev_err(dev, "invalid st,utmi-switch value: %d\n", ret);
+ goto clk_disable;
+ }
+ if (utmi_switch == 1)
+ stm32_usbphyc_set_bits(usbphyc->base + STM32_USBPHYC_MISC,
+ SWITHOST);
+
+ version = readl_relaxed(usbphyc->base + STM32_USBPHYC_VERSION);
+ dev_info(dev, "registered rev:%lu.%lu\n",
+ FIELD_GET(MAJREV, version), FIELD_GET(MINREV, version));
+
+ return 0;
+
+clk_disable:
+ clk_disable_unprepare(usbphyc->clk);
+
+ return ret;
+}
+
+static int stm32_usbphyc_remove(struct platform_device *pdev)
+{
+ struct stm32_usbphyc *usbphyc = dev_get_drvdata(&pdev->dev);
+
+ clk_disable_unprepare(usbphyc->clk);
+
+ return 0;
+}
+
+static const struct of_device_id stm32_usbphyc_of_match[] = {
+ { .compatible = "st,stm32mp1-usbphyc", },
+ { },
+};
+MODULE_DEVICE_TABLE(of, stm32_usbphyc_of_match);
+
+static struct platform_driver stm32_usbphyc_driver = {
+ .probe = stm32_usbphyc_probe,
+ .remove = stm32_usbphyc_remove,
+ .driver = {
+ .of_match_table = stm32_usbphyc_of_match,
+ .name = "stm32-usbphyc",
+ }
+};
+module_platform_driver(stm32_usbphyc_driver);
+
+MODULE_DESCRIPTION("STMicroelectronics STM32 USBPHYC driver");
+MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
+MODULE_LICENSE("GPL v2");
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v2 1/2] dt-bindings: phy: add support for STM32 USB PHY Controller (USBPHYC)
2018-03-01 15:30 ` [PATCH v2 1/2] dt-bindings: phy: add support for STM32 USB PHY Controller (USBPHYC) Amelie Delaunay
@ 2018-03-02 6:02 ` Kishon Vijay Abraham I
2018-03-02 14:42 ` Amelie DELAUNAY
0 siblings, 1 reply; 5+ messages in thread
From: Kishon Vijay Abraham I @ 2018-03-02 6:02 UTC (permalink / raw)
To: Amelie Delaunay, Rob Herring, Mark Rutland, Alexandre Torgue,
Maxime Coquelin
Cc: devicetree, linux-kernel, linux-arm-kernel
On Thursday 01 March 2018 09:00 PM, Amelie Delaunay wrote:
> This patch adds the device tree bindings description for STM32 USBPHYC
> (USB PHY Controller).
>
> Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
> ---
> .../devicetree/bindings/phy/phy-stm32-usbphyc.txt | 46 ++++++++++++++++++++++
> 1 file changed, 46 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt
>
> diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt
> new file mode 100644
> index 0000000..1ad3893
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt
> @@ -0,0 +1,46 @@
> +STMicroelectronics STM32 USB HS PHY controller
> +
> +The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
> +switch. It controls PHY configuration and status, and the UTMI+ switch that
> +selects either OTG or HOST controller for the second PHY port. It also sets
> +PLL configuration.
> +
> +USBPHYC
> + |_ PLL
> + |
> + |_ PHY port#1 _________________ HOST controller
> + | _ |
> + | / 1|________________|
> + |_ PHY port#2 ----| |________________
> + | \_0| |
> + |_ UTMI switch_______| OTG controller
> +
> +
This should be modeled as a phy provider node with two separate sub-nodes for
each of the PHYs.
Thanks
Kishon
> +Required properties:
> +- compatible: must be "st,stm32mp1-usbphyc"
> +- reg: address and length of the usb phy control register set
> +- clocks: phandle + clock specifier for the PLL phy clock
> +- phy-supply: from the generic phy bindings, phandle to the regulator
> + providing 3V3 power to the PHY, see phy-bindings.txt
> +- vdda1v1-supply: phandle to the regulator providing 1V1 power to the PHY
> +- vdda1v8-supply: phandle to the regulator providing 1V8 power to the PHY
> +
> +Optional properties:
> +- assigned-clocks: phandle + clock specifier for the PLL phy clock
> +- assigned-clock-parents: the PLL phy clock parent
> +- resets: phandle + reset specifier
> +- st,utmi-switch: should be <0> or <1>, to select USB controller for PHY
> + port#2. If not specified, 0 is the default selection.
> +
> +
> +Example:
> + usbphyc: usb-phy@5a006000 {
> + compatible = "st,stm32mp1-usbphyc";
> + reg = <0x5a006000 0x1000>;
> + clocks = <&rcc_clk USBPHY_K>;
> + resets = <&rcc_rst USBPHY_R>;
> + st,utmi-switch = <1>;
> + phy-supply = <&vdd_usb>;
> + vdda1v1-supply = <®11>;
> + vdda1v8-supply = <®18>
> + };
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2 1/2] dt-bindings: phy: add support for STM32 USB PHY Controller (USBPHYC)
2018-03-02 6:02 ` Kishon Vijay Abraham I
@ 2018-03-02 14:42 ` Amelie DELAUNAY
0 siblings, 0 replies; 5+ messages in thread
From: Amelie DELAUNAY @ 2018-03-02 14:42 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Rob Herring, Mark Rutland,
Alexandre TORGUE, Maxime Coquelin
Cc: devicetree, linux-kernel, linux-arm-kernel
On 03/02/2018 07:02 AM, Kishon Vijay Abraham I wrote:
>
>
> On Thursday 01 March 2018 09:00 PM, Amelie Delaunay wrote:
>> This patch adds the device tree bindings description for STM32 USBPHYC
>> (USB PHY Controller).
>>
>> Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
>> ---
>> .../devicetree/bindings/phy/phy-stm32-usbphyc.txt | 46 ++++++++++++++++++++++
>> 1 file changed, 46 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt
>>
>> diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt
>> new file mode 100644
>> index 0000000..1ad3893
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt
>> @@ -0,0 +1,46 @@
>> +STMicroelectronics STM32 USB HS PHY controller
>> +
>> +The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
>> +switch. It controls PHY configuration and status, and the UTMI+ switch that
>> +selects either OTG or HOST controller for the second PHY port. It also sets
>> +PLL configuration.
>> +
>> +USBPHYC
>> + |_ PLL
>> + |
>> + |_ PHY port#1 _________________ HOST controller
>> + | _ |
>> + | / 1|________________|
>> + |_ PHY port#2 ----| |________________
>> + | \_0| |
>> + |_ UTMI switch_______| OTG controller
>> +
>> +
>
> This should be modeled as a phy provider node with two separate sub-nodes for
> each of the PHYs.
>
> Thanks
> Kishon
>
Thank you for pointing me to the right solution. I send a V3.
Regards,
Amelie
>> +Required properties:
>> +- compatible: must be "st,stm32mp1-usbphyc"
>> +- reg: address and length of the usb phy control register set
>> +- clocks: phandle + clock specifier for the PLL phy clock
>> +- phy-supply: from the generic phy bindings, phandle to the regulator
>> + providing 3V3 power to the PHY, see phy-bindings.txt
>> +- vdda1v1-supply: phandle to the regulator providing 1V1 power to the PHY
>> +- vdda1v8-supply: phandle to the regulator providing 1V8 power to the PHY
>> +
>> +Optional properties:
>> +- assigned-clocks: phandle + clock specifier for the PLL phy clock
>> +- assigned-clock-parents: the PLL phy clock parent
>> +- resets: phandle + reset specifier
>> +- st,utmi-switch: should be <0> or <1>, to select USB controller for PHY
>> + port#2. If not specified, 0 is the default selection.
>> +
>> +
>> +Example:
>> + usbphyc: usb-phy@5a006000 {
>> + compatible = "st,stm32mp1-usbphyc";
>> + reg = <0x5a006000 0x1000>;
>> + clocks = <&rcc_clk USBPHY_K>;
>> + resets = <&rcc_rst USBPHY_R>;
>> + st,utmi-switch = <1>;
>> + phy-supply = <&vdd_usb>;
>> + vdda1v1-supply = <®11>;
>> + vdda1v8-supply = <®18>
>> + };
>>
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2018-03-02 14:42 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-03-01 15:30 [PATCH v2 0/2] Introduce STM32 USB PHY Controller driver Amelie Delaunay
2018-03-01 15:30 ` [PATCH v2 1/2] dt-bindings: phy: add support for STM32 USB PHY Controller (USBPHYC) Amelie Delaunay
2018-03-02 6:02 ` Kishon Vijay Abraham I
2018-03-02 14:42 ` Amelie DELAUNAY
2018-03-01 15:30 ` [PATCH v2 2/2] phy: stm32: " Amelie Delaunay
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).