[PATCH v4 1/6] clk: mediatek: update missing clock data for MT7622 audsys

[PATCH v4 1/6] clk: mediatek: update missing clock data for MT7622 audsys

[Ryder Lee]

Add missing clock data 'CLK_AUDIO_AFE_CONN' for MT7622 audsys.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
---
 drivers/clk/mediatek/clk-mt7622-aud.c  | 1 +
 include/dt-bindings/clock/mt7622-clk.h | 3 ++-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/mediatek/clk-mt7622-aud.c b/drivers/clk/mediatek/clk-mt7622-aud.c
index fad7d9f..13f752d 100644
--- a/drivers/clk/mediatek/clk-mt7622-aud.c
+++ b/drivers/clk/mediatek/clk-mt7622-aud.c
@@ -106,6 +106,7 @@
 	GATE_AUDIO1(CLK_AUDIO_INTDIR, "audio_intdir", "intdir_sel", 20),
 	GATE_AUDIO1(CLK_AUDIO_A1SYS, "audio_a1sys", "a1sys_hp_sel", 21),
 	GATE_AUDIO1(CLK_AUDIO_A2SYS, "audio_a2sys", "a2sys_hp_sel", 22),
+	GATE_AUDIO1(CLK_AUDIO_AFE_CONN, "audio_afe_conn", "a1sys_hp_sel", 23),
 	/* AUDIO2 */
 	GATE_AUDIO2(CLK_AUDIO_UL1, "audio_ul1", "a1sys_hp_sel", 0),
 	GATE_AUDIO2(CLK_AUDIO_UL2, "audio_ul2", "a1sys_hp_sel", 1),
diff --git a/include/dt-bindings/clock/mt7622-clk.h b/include/dt-bindings/clock/mt7622-clk.h
index 3e514ed..e9d77f0 100644
--- a/include/dt-bindings/clock/mt7622-clk.h
+++ b/include/dt-bindings/clock/mt7622-clk.h
@@ -235,7 +235,8 @@
 #define CLK_AUDIO_MEM_ASRC3		43
 #define CLK_AUDIO_MEM_ASRC4		44
 #define CLK_AUDIO_MEM_ASRC5		45
-#define CLK_AUDIO_NR_CLK		46
+#define CLK_AUDIO_AFE_CONN		46
+#define CLK_AUDIO_NR_CLK		47
 
 /* SSUSBSYS */
 
-- 
1.9.1

[PATCH v4 2/6] clk: mediatek: add devm_of_platform_populate() for MT7622 audsys

[Ryder Lee]

Add devm_of_platform_populate() to populate devices which are children
of the root node.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
---
 drivers/clk/mediatek/clk-mt7622-aud.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt7622-aud.c b/drivers/clk/mediatek/clk-mt7622-aud.c
index 13f752d..0a1109f 100644
--- a/drivers/clk/mediatek/clk-mt7622-aud.c
+++ b/drivers/clk/mediatek/clk-mt7622-aud.c
@@ -142,6 +142,7 @@ static int clk_mt7622_audiosys_init(struct platform_device *pdev)
 {
 	struct clk_onecell_data *clk_data;
 	struct device_node *node = pdev->dev.of_node;
+
 	int r;
 
 	clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);
@@ -150,12 +151,15 @@ static int clk_mt7622_audiosys_init(struct platform_device *pdev)
 			       clk_data);
 
 	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r)
+	if (r) {
 		dev_err(&pdev->dev,
 			"could not register clock provider: %s: %d\n",
 			pdev->name, r);
 
-	return r;
+		return r;
+	}
+
+	return devm_of_platform_populate(&pdev->dev);
 }
 
 static const struct of_device_id of_match_clk_mt7622_aud[] = {
-- 
1.9.1

[PATCH v4 3/6] clk: mediatek: add audsys support for MT2701

[Ryder Lee]

Add clock driver support for MT2701 audsys.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
---
 drivers/clk/mediatek/Kconfig          |   6 ++
 drivers/clk/mediatek/Makefile         |   1 +
 drivers/clk/mediatek/clk-mt2701-aud.c | 177 ++++++++++++++++++++++++++++++++++
 3 files changed, 184 insertions(+)
 create mode 100644 drivers/clk/mediatek/clk-mt2701-aud.c

diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 1f9ea0f..92afe59 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -54,6 +54,12 @@ config COMMON_CLK_MT2701_BDPSYS
 	---help---
 	  This driver supports MediaTek MT2701 bdpsys clocks.
 
+config COMMON_CLK_MT2701_AUDSYS
+	bool "Clock driver for Mediatek MT2701 audsys"
+	depends on COMMON_CLK_MT2701
+	---help---
+	  This driver supports Mediatek MT2701 audsys clocks.
+
 config COMMON_CLK_MT2712
 	bool "Clock driver for MediaTek MT2712"
 	depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 5160fdc..b80eff2 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_COMMON_CLK_MT6797_MMSYS) += clk-mt6797-mm.o
 obj-$(CONFIG_COMMON_CLK_MT6797_VDECSYS) += clk-mt6797-vdec.o
 obj-$(CONFIG_COMMON_CLK_MT6797_VENCSYS) += clk-mt6797-venc.o
 obj-$(CONFIG_COMMON_CLK_MT2701) += clk-mt2701.o
+obj-$(CONFIG_COMMON_CLK_MT2701_AUDSYS) += clk-mt2701-aud.o
 obj-$(CONFIG_COMMON_CLK_MT2701_BDPSYS) += clk-mt2701-bdp.o
 obj-$(CONFIG_COMMON_CLK_MT2701_ETHSYS) += clk-mt2701-eth.o
 obj-$(CONFIG_COMMON_CLK_MT2701_HIFSYS) += clk-mt2701-hif.o
diff --git a/drivers/clk/mediatek/clk-mt2701-aud.c b/drivers/clk/mediatek/clk-mt2701-aud.c
new file mode 100644
index 0000000..3ccd67d
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt2701-aud.c
@@ -0,0 +1,177 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Ryder Lee <ryder.lee@mediatek.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt2701-clk.h>
+
+#define GATE_AUDIO0(_id, _name, _parent, _shift) {	\
+		.id = _id,				\
+		.name = _name,				\
+		.parent_name = _parent,			\
+		.regs = &audio0_cg_regs,			\
+		.shift = _shift,			\
+		.ops = &mtk_clk_gate_ops_no_setclr,	\
+	}
+
+#define GATE_AUDIO1(_id, _name, _parent, _shift) {	\
+		.id = _id,				\
+		.name = _name,				\
+		.parent_name = _parent,			\
+		.regs = &audio1_cg_regs,			\
+		.shift = _shift,			\
+		.ops = &mtk_clk_gate_ops_no_setclr,	\
+	}
+
+#define GATE_AUDIO2(_id, _name, _parent, _shift) {	\
+		.id = _id,				\
+		.name = _name,				\
+		.parent_name = _parent,			\
+		.regs = &audio2_cg_regs,			\
+		.shift = _shift,			\
+		.ops = &mtk_clk_gate_ops_no_setclr,	\
+	}
+
+#define GATE_AUDIO3(_id, _name, _parent, _shift) {	\
+		.id = _id,				\
+		.name = _name,				\
+		.parent_name = _parent,			\
+		.regs = &audio3_cg_regs,			\
+		.shift = _shift,			\
+		.ops = &mtk_clk_gate_ops_no_setclr,	\
+	}
+
+static const struct mtk_gate_regs audio0_cg_regs = {
+	.set_ofs = 0x0,
+	.clr_ofs = 0x0,
+	.sta_ofs = 0x0,
+};
+
+static const struct mtk_gate_regs audio1_cg_regs = {
+	.set_ofs = 0x10,
+	.clr_ofs = 0x10,
+	.sta_ofs = 0x10,
+};
+
+static const struct mtk_gate_regs audio2_cg_regs = {
+	.set_ofs = 0x14,
+	.clr_ofs = 0x14,
+	.sta_ofs = 0x14,
+};
+
+static const struct mtk_gate_regs audio3_cg_regs = {
+	.set_ofs = 0x634,
+	.clr_ofs = 0x634,
+	.sta_ofs = 0x634,
+};
+
+static const struct mtk_gate audio_clks[] = {
+	/* AUDIO0 */
+	GATE_AUDIO0(CLK_AUD_AFE, "audio_afe", "aud_intbus_sel", 2),
+	GATE_AUDIO0(CLK_AUD_HDMI, "audio_hdmi", "audpll_sel", 20),
+	GATE_AUDIO0(CLK_AUD_SPDF, "audio_spdf", "audpll_sel", 21),
+	GATE_AUDIO0(CLK_AUD_SPDF2, "audio_spdf2", "audpll_sel", 22),
+	GATE_AUDIO0(CLK_AUD_APLL, "audio_apll", "audpll_sel", 23),
+	/* AUDIO1 */
+	GATE_AUDIO1(CLK_AUD_I2SIN1, "audio_i2sin1", "aud_mux1_sel", 0),
+	GATE_AUDIO1(CLK_AUD_I2SIN2, "audio_i2sin2", "aud_mux1_sel", 1),
+	GATE_AUDIO1(CLK_AUD_I2SIN3, "audio_i2sin3", "aud_mux1_sel", 2),
+	GATE_AUDIO1(CLK_AUD_I2SIN4, "audio_i2sin4", "aud_mux1_sel", 3),
+	GATE_AUDIO1(CLK_AUD_I2SIN5, "audio_i2sin5", "aud_mux1_sel", 4),
+	GATE_AUDIO1(CLK_AUD_I2SIN6, "audio_i2sin6", "aud_mux1_sel", 5),
+	GATE_AUDIO1(CLK_AUD_I2SO1, "audio_i2so1", "aud_mux1_sel", 6),
+	GATE_AUDIO1(CLK_AUD_I2SO2, "audio_i2so2", "aud_mux1_sel", 7),
+	GATE_AUDIO1(CLK_AUD_I2SO3, "audio_i2so3", "aud_mux1_sel", 8),
+	GATE_AUDIO1(CLK_AUD_I2SO4, "audio_i2so4", "aud_mux1_sel", 9),
+	GATE_AUDIO1(CLK_AUD_I2SO5, "audio_i2so5", "aud_mux1_sel", 10),
+	GATE_AUDIO1(CLK_AUD_I2SO6, "audio_i2so6", "aud_mux1_sel", 11),
+	GATE_AUDIO1(CLK_AUD_ASRCI1, "audio_asrci1", "asm_h_sel", 12),
+	GATE_AUDIO1(CLK_AUD_ASRCI2, "audio_asrci2", "asm_h_sel", 13),
+	GATE_AUDIO1(CLK_AUD_ASRCO1, "audio_asrco1", "asm_h_sel", 14),
+	GATE_AUDIO1(CLK_AUD_ASRCO2, "audio_asrco2", "asm_h_sel", 15),
+	GATE_AUDIO1(CLK_AUD_INTDIR, "audio_intdir", "intdir_sel", 20),
+	GATE_AUDIO1(CLK_AUD_A1SYS, "audio_a1sys", "aud_mux1_sel", 21),
+	GATE_AUDIO1(CLK_AUD_A2SYS, "audio_a2sys", "aud_mux2_sel", 22),
+	GATE_AUDIO1(CLK_AUD_AFE_CONN, "audio_afe_conn", "aud_mux1_sel", 23),
+	GATE_AUDIO1(CLK_AUD_AFE_MRGIF, "audio_afe_mrgif", "aud_mux1_sel", 25),
+	/* AUDIO2 */
+	GATE_AUDIO2(CLK_AUD_MMIF_UL1, "audio_ul1", "aud_mux1_sel", 0),
+	GATE_AUDIO2(CLK_AUD_MMIF_UL2, "audio_ul2", "aud_mux1_sel", 1),
+	GATE_AUDIO2(CLK_AUD_MMIF_UL3, "audio_ul3", "aud_mux1_sel", 2),
+	GATE_AUDIO2(CLK_AUD_MMIF_UL4, "audio_ul4", "aud_mux1_sel", 3),
+	GATE_AUDIO2(CLK_AUD_MMIF_UL5, "audio_ul5", "aud_mux1_sel", 4),
+	GATE_AUDIO2(CLK_AUD_MMIF_UL6, "audio_ul6", "aud_mux1_sel", 5),
+	GATE_AUDIO2(CLK_AUD_MMIF_DL1, "audio_dl1", "aud_mux1_sel", 6),
+	GATE_AUDIO2(CLK_AUD_MMIF_DL2, "audio_dl2", "aud_mux1_sel", 7),
+	GATE_AUDIO2(CLK_AUD_MMIF_DL3, "audio_dl3", "aud_mux1_sel", 8),
+	GATE_AUDIO2(CLK_AUD_MMIF_DL4, "audio_dl4", "aud_mux1_sel", 9),
+	GATE_AUDIO2(CLK_AUD_MMIF_DL5, "audio_dl5", "aud_mux1_sel", 10),
+	GATE_AUDIO2(CLK_AUD_MMIF_DL6, "audio_dl6", "aud_mux1_sel", 11),
+	GATE_AUDIO2(CLK_AUD_MMIF_DLMCH, "audio_dlmch", "aud_mux1_sel", 12),
+	GATE_AUDIO2(CLK_AUD_MMIF_ARB1, "audio_arb1", "aud_mux1_sel", 13),
+	GATE_AUDIO2(CLK_AUD_MMIF_AWB1, "audio_awb", "aud_mux1_sel", 14),
+	GATE_AUDIO2(CLK_AUD_MMIF_AWB2, "audio_awb2", "aud_mux1_sel", 15),
+	GATE_AUDIO2(CLK_AUD_MMIF_DAI, "audio_dai", "aud_mux1_sel", 16),
+	/* AUDIO3 */
+	GATE_AUDIO3(CLK_AUD_ASRCI3, "audio_asrci3", "asm_h_sel", 2),
+	GATE_AUDIO3(CLK_AUD_ASRCI4, "audio_asrci4", "asm_h_sel", 3),
+	GATE_AUDIO3(CLK_AUD_ASRCI5, "audio_asrci5", "asm_h_sel", 4),
+	GATE_AUDIO3(CLK_AUD_ASRCI6, "audio_asrci6", "asm_h_sel", 5),
+	GATE_AUDIO3(CLK_AUD_ASRCO3, "audio_asrco3", "asm_h_sel", 6),
+	GATE_AUDIO3(CLK_AUD_ASRCO4, "audio_asrco4", "asm_h_sel", 7),
+	GATE_AUDIO3(CLK_AUD_ASRCO5, "audio_asrco5", "asm_h_sel", 8),
+	GATE_AUDIO3(CLK_AUD_ASRCO6, "audio_asrco6", "asm_h_sel", 9),
+	GATE_AUDIO3(CLK_AUD_MEM_ASRC1, "audio_mem_asrc1", "asm_h_sel", 10),
+	GATE_AUDIO3(CLK_AUD_MEM_ASRC2, "audio_mem_asrc2", "asm_h_sel", 11),
+	GATE_AUDIO3(CLK_AUD_MEM_ASRC3, "audio_mem_asrc3", "asm_h_sel", 12),
+	GATE_AUDIO3(CLK_AUD_MEM_ASRC4, "audio_mem_asrc4", "asm_h_sel", 13),
+	GATE_AUDIO3(CLK_AUD_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14),
+};
+
+static const struct of_device_id of_match_clk_mt2701_aud[] = {
+	{ .compatible = "mediatek,mt2701-audsys", },
+	{}
+};
+
+static int clk_mt2701_aud_probe(struct platform_device *pdev)
+{
+	struct clk_onecell_data *clk_data;
+	struct device_node *node = pdev->dev.of_node;
+	int r;
+
+	clk_data = mtk_alloc_clk_data(CLK_AUD_NR);
+
+	mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
+			       clk_data);
+
+	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+	if (r) {
+		dev_err(&pdev->dev,
+			"could not register clock provider: %s: %d\n",
+			pdev->name, r);
+
+		return r;
+	}
+
+	return devm_of_platform_populate(&pdev->dev);
+}
+
+static struct platform_driver clk_mt2701_aud_drv = {
+	.probe = clk_mt2701_aud_probe,
+	.driver = {
+		.name = "clk-mt2701-aud",
+		.of_match_table = of_match_clk_mt2701_aud,
+	},
+};
+
+builtin_platform_driver(clk_mt2701_aud_drv);
-- 
1.9.1

[PATCH v4 4/6] dt-bindings: clock: mediatek: update audsys documentation to adapt MFD device

[Ryder Lee]

The MediaTek audio hardware block that exposes functionalities that are
handled by separate subsystems in the kernel.  These functions are all
mapped somewhere at 0x112xxxxx, and there are some control bits are mixed
up with other functions within the same registers.

This patch modifies example to illustrate child nodes.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
---
 .../bindings/arm/mediatek/mediatek,audsys.txt         | 19 ++++++++++++++-----
 1 file changed, 14 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
index 9b8f578..97b304e 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
@@ -13,10 +13,19 @@ The AUDSYS controller uses the common clk binding from
 Documentation/devicetree/bindings/clock/clock-bindings.txt
 The available clocks are defined in dt-bindings/clock/mt*-clk.h.
 
+Required sub-nodes:
+-------
+For common binding part and usage, refer to
+../sonud/mt2701-afe-pcm.txt.
+
 Example:
 
-audsys: audsys@11220000 {
-	compatible = "mediatek,mt7622-audsys", "syscon";
-	reg = <0 0x11220000 0 0x1000>;
-	#clock-cells = <1>;
-};
+	audsys: clock-controller@11220000 {
+		compatible = "mediatek,mt7622-audsys", "syscon";
+		reg = <0 0x11220000 0 0x2000>;
+		#clock-cells = <1>;
+
+		afe: audio-controller {
+			...
+		};
+	};
-- 
1.9.1

[PATCH v4 5/6] dt-bindings: clock: mediatek: add audsys support for MT2701

[Ryder Lee]

This patch adds a compatible string for MT2701.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
---
 Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
index 97b304e..34a69ba 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
@@ -6,6 +6,7 @@ The MediaTek AUDSYS controller provides various clocks to the system.
 Required Properties:
 
 - compatible: Should be one of:
+	- "mediatek,mt2701-audsys", "syscon"
 	- "mediatek,mt7622-audsys", "syscon"
 - #clock-cells: Must be 1
 
-- 
1.9.1

[PATCH v4 6/6] arm: dts: mediatek: modify audio related nodes for both MT2701 and MT7623

[Ryder Lee]

Modify audio related nodes to reflect the actual usage in binding documents.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
---
 arch/arm/boot/dts/mt2701.dtsi | 188 ++++++++++++++++++++---------------------
 arch/arm/boot/dts/mt7623.dtsi | 190 ++++++++++++++++++++----------------------
 2 files changed, 182 insertions(+), 196 deletions(-)

diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 05557fc..05cf65c 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -426,104 +426,96 @@
 		status = "disabled";
 	};
 
-	afe: audio-controller@11220000 {
-		compatible = "mediatek,mt2701-audio";
-		reg = <0 0x11220000 0 0x2000>,
-		      <0 0x112a0000 0 0x20000>;
-		interrupts =  <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
-			      <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
-		interrupt-names	= "afe", "asys";
-		power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
-
-		clocks = <&infracfg CLK_INFRA_AUDIO>,
-			 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
-			 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
-			 <&topckgen CLK_TOP_AUD_MUX1_DIV>,
-			 <&topckgen CLK_TOP_AUD_MUX2_DIV>,
-			 <&topckgen CLK_TOP_AUD_48K_TIMING>,
-			 <&topckgen CLK_TOP_AUD_44K_TIMING>,
-			 <&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
-			 <&topckgen CLK_TOP_APLL_SEL>,
-			 <&topckgen CLK_TOP_AUD1PLL_98M>,
-			 <&topckgen CLK_TOP_AUD2PLL_90M>,
-			 <&topckgen CLK_TOP_HADDS2PLL_98M>,
-			 <&topckgen CLK_TOP_HADDS2PLL_294M>,
-			 <&topckgen CLK_TOP_AUDPLL>,
-			 <&topckgen CLK_TOP_AUDPLL_D4>,
-			 <&topckgen CLK_TOP_AUDPLL_D8>,
-			 <&topckgen CLK_TOP_AUDPLL_D16>,
-			 <&topckgen CLK_TOP_AUDPLL_D24>,
-			 <&topckgen CLK_TOP_AUDINTBUS_SEL>,
-			 <&clk26m>,
-			 <&topckgen CLK_TOP_SYSPLL1_D4>,
-			 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
-			 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
-			 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
-			 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
-			 <&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
-			 <&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
-			 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
-			 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
-			 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
-			 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
-			 <&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
-			 <&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
-			 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
-			 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
-			 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
-			 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
-			 <&topckgen CLK_TOP_AUD_I2S5_MCLK>,
-			 <&topckgen CLK_TOP_AUD_I2S6_MCLK>,
-			 <&topckgen CLK_TOP_ASM_M_SEL>,
-			 <&topckgen CLK_TOP_ASM_H_SEL>,
-			 <&topckgen CLK_TOP_UNIVPLL2_D4>,
-			 <&topckgen CLK_TOP_UNIVPLL2_D2>,
-			 <&topckgen CLK_TOP_SYSPLL_D5>;
-
-		clock-names = "infra_sys_audio_clk",
-			 "top_audio_mux1_sel",
-			 "top_audio_mux2_sel",
-			 "top_audio_mux1_div",
-			 "top_audio_mux2_div",
-			 "top_audio_48k_timing",
-			 "top_audio_44k_timing",
-			 "top_audpll_mux_sel",
-			 "top_apll_sel",
-			 "top_aud1_pll_98M",
-			 "top_aud2_pll_90M",
-			 "top_hadds2_pll_98M",
-			 "top_hadds2_pll_294M",
-			 "top_audpll",
-			 "top_audpll_d4",
-			 "top_audpll_d8",
-			 "top_audpll_d16",
-			 "top_audpll_d24",
-			 "top_audintbus_sel",
-			 "clk_26m",
-			 "top_syspll1_d4",
-			 "top_aud_k1_src_sel",
-			 "top_aud_k2_src_sel",
-			 "top_aud_k3_src_sel",
-			 "top_aud_k4_src_sel",
-			 "top_aud_k5_src_sel",
-			 "top_aud_k6_src_sel",
-			 "top_aud_k1_src_div",
-			 "top_aud_k2_src_div",
-			 "top_aud_k3_src_div",
-			 "top_aud_k4_src_div",
-			 "top_aud_k5_src_div",
-			 "top_aud_k6_src_div",
-			 "top_aud_i2s1_mclk",
-			 "top_aud_i2s2_mclk",
-			 "top_aud_i2s3_mclk",
-			 "top_aud_i2s4_mclk",
-			 "top_aud_i2s5_mclk",
-			 "top_aud_i2s6_mclk",
-			 "top_asm_m_sel",
-			 "top_asm_h_sel",
-			 "top_univpll2_d4",
-			 "top_univpll2_d2",
-			 "top_syspll_d5";
+	audsys: clock-controller@11220000 {
+		compatible = "mediatek,mt2701-audsys", "syscon";
+		reg = <0 0x11220000 0 0x2000>;
+		#clock-cells = <1>;
+
+		afe: audio-controller {
+			compatible = "mediatek,mt2701-audio";
+			interrupts =  <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
+				      <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
+			interrupt-names	= "afe", "asys";
+			power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
+
+			clocks = <&infracfg CLK_INFRA_AUDIO>,
+				 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
+				 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
+				 <&topckgen CLK_TOP_AUD_48K_TIMING>,
+				 <&topckgen CLK_TOP_AUD_44K_TIMING>,
+				 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
+				 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
+				 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
+				 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
+				 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
+				 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
+				 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
+				 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
+				 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
+				 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
+				 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
+				 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
+				 <&audsys CLK_AUD_I2SO1>,
+				 <&audsys CLK_AUD_I2SO2>,
+				 <&audsys CLK_AUD_I2SO3>,
+				 <&audsys CLK_AUD_I2SO4>,
+				 <&audsys CLK_AUD_I2SIN1>,
+				 <&audsys CLK_AUD_I2SIN2>,
+				 <&audsys CLK_AUD_I2SIN3>,
+				 <&audsys CLK_AUD_I2SIN4>,
+				 <&audsys CLK_AUD_ASRCO1>,
+				 <&audsys CLK_AUD_ASRCO2>,
+				 <&audsys CLK_AUD_ASRCO3>,
+				 <&audsys CLK_AUD_ASRCO4>,
+				 <&audsys CLK_AUD_AFE>,
+				 <&audsys CLK_AUD_AFE_CONN>,
+				 <&audsys CLK_AUD_A1SYS>,
+				 <&audsys CLK_AUD_A2SYS>,
+				 <&audsys CLK_AUD_AFE_MRGIF>;
+
+			clock-names = "infra_sys_audio_clk",
+				      "top_audio_mux1_sel",
+				      "top_audio_mux2_sel",
+				      "top_audio_a1sys_hp",
+				      "top_audio_a2sys_hp",
+				      "i2s0_src_sel",
+				      "i2s1_src_sel",
+				      "i2s2_src_sel",
+				      "i2s3_src_sel",
+				      "i2s0_src_div",
+				      "i2s1_src_div",
+				      "i2s2_src_div",
+				      "i2s3_src_div",
+				      "i2s0_mclk_en",
+				      "i2s1_mclk_en",
+				      "i2s2_mclk_en",
+				      "i2s3_mclk_en",
+				      "i2so0_hop_ck",
+				      "i2so1_hop_ck",
+				      "i2so2_hop_ck",
+				      "i2so3_hop_ck",
+				      "i2si0_hop_ck",
+				      "i2si1_hop_ck",
+				      "i2si2_hop_ck",
+				      "i2si3_hop_ck",
+				      "asrc0_out_ck",
+				      "asrc1_out_ck",
+				      "asrc2_out_ck",
+				      "asrc3_out_ck",
+				      "audio_afe_pd",
+				      "audio_afe_conn_pd",
+				      "audio_a1sys_pd",
+				      "audio_a2sys_pd",
+				      "audio_mrgif_pd";
+
+			assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
+					  <&topckgen CLK_TOP_AUD_MUX2_SEL>,
+					  <&topckgen CLK_TOP_AUD_MUX1_DIV>,
+					  <&topckgen CLK_TOP_AUD_MUX2_DIV>;
+			assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
+						 <&topckgen CLK_TOP_AUD2PLL_90M>;
+			assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
+		};
 	};
 
 	mmsys: syscon@14000000 {
diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
index b750da5..e4dd31d 100644
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -538,105 +538,99 @@
 		status = "disabled";
 	};
 
-	afe: audio-controller@11220000 {
-		compatible = "mediatek,mt7623-audio",
-			     "mediatek,mt2701-audio";
-		reg = <0 0x11220000 0 0x2000>,
-		      <0 0x112a0000 0 0x20000>;
-		interrupts =  <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
-			      <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
-		interrupt-names	= "afe", "asys";
-		power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
+	audsys: clock-controller@11220000 {
+		compatible = "mediatek,mt7623-audsys",
+			     "mediatek,mt2701-audsys",
+			     "syscon";
+		reg = <0 0x11220000 0 0x2000>;
+		#clock-cells = <1>;
 
-		clocks = <&infracfg CLK_INFRA_AUDIO>,
-			 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
-			 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
-			 <&topckgen CLK_TOP_AUD_MUX1_DIV>,
-			 <&topckgen CLK_TOP_AUD_MUX2_DIV>,
-			 <&topckgen CLK_TOP_AUD_48K_TIMING>,
-			 <&topckgen CLK_TOP_AUD_44K_TIMING>,
-			 <&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
-			 <&topckgen CLK_TOP_APLL_SEL>,
-			 <&topckgen CLK_TOP_AUD1PLL_98M>,
-			 <&topckgen CLK_TOP_AUD2PLL_90M>,
-			 <&topckgen CLK_TOP_HADDS2PLL_98M>,
-			 <&topckgen CLK_TOP_HADDS2PLL_294M>,
-			 <&topckgen CLK_TOP_AUDPLL>,
-			 <&topckgen CLK_TOP_AUDPLL_D4>,
-			 <&topckgen CLK_TOP_AUDPLL_D8>,
-			 <&topckgen CLK_TOP_AUDPLL_D16>,
-			 <&topckgen CLK_TOP_AUDPLL_D24>,
-			 <&topckgen CLK_TOP_AUDINTBUS_SEL>,
-			 <&clk26m>,
-			 <&topckgen CLK_TOP_SYSPLL1_D4>,
-			 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
-			 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
-			 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
-			 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
-			 <&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
-			 <&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
-			 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
-			 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
-			 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
-			 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
-			 <&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
-			 <&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
-			 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
-			 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
-			 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
-			 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
-			 <&topckgen CLK_TOP_AUD_I2S5_MCLK>,
-			 <&topckgen CLK_TOP_AUD_I2S6_MCLK>,
-			 <&topckgen CLK_TOP_ASM_M_SEL>,
-			 <&topckgen CLK_TOP_ASM_H_SEL>,
-			 <&topckgen CLK_TOP_UNIVPLL2_D4>,
-			 <&topckgen CLK_TOP_UNIVPLL2_D2>,
-			 <&topckgen CLK_TOP_SYSPLL_D5>;
-
-		clock-names = "infra_sys_audio_clk",
-			 "top_audio_mux1_sel",
-			 "top_audio_mux2_sel",
-			 "top_audio_mux1_div",
-			 "top_audio_mux2_div",
-			 "top_audio_48k_timing",
-			 "top_audio_44k_timing",
-			 "top_audpll_mux_sel",
-			 "top_apll_sel",
-			 "top_aud1_pll_98M",
-			 "top_aud2_pll_90M",
-			 "top_hadds2_pll_98M",
-			 "top_hadds2_pll_294M",
-			 "top_audpll",
-			 "top_audpll_d4",
-			 "top_audpll_d8",
-			 "top_audpll_d16",
-			 "top_audpll_d24",
-			 "top_audintbus_sel",
-			 "clk_26m",
-			 "top_syspll1_d4",
-			 "top_aud_k1_src_sel",
-			 "top_aud_k2_src_sel",
-			 "top_aud_k3_src_sel",
-			 "top_aud_k4_src_sel",
-			 "top_aud_k5_src_sel",
-			 "top_aud_k6_src_sel",
-			 "top_aud_k1_src_div",
-			 "top_aud_k2_src_div",
-			 "top_aud_k3_src_div",
-			 "top_aud_k4_src_div",
-			 "top_aud_k5_src_div",
-			 "top_aud_k6_src_div",
-			 "top_aud_i2s1_mclk",
-			 "top_aud_i2s2_mclk",
-			 "top_aud_i2s3_mclk",
-			 "top_aud_i2s4_mclk",
-			 "top_aud_i2s5_mclk",
-			 "top_aud_i2s6_mclk",
-			 "top_asm_m_sel",
-			 "top_asm_h_sel",
-			 "top_univpll2_d4",
-			 "top_univpll2_d2",
-			 "top_syspll_d5";
+		afe: audio-controller {
+			compatible = "mediatek,mt7623-audio",
+				     "mediatek,mt2701-audio";
+			interrupts =  <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
+				      <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
+			interrupt-names	= "afe", "asys";
+			power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
+
+			clocks = <&infracfg CLK_INFRA_AUDIO>,
+				 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
+				 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
+				 <&topckgen CLK_TOP_AUD_48K_TIMING>,
+				 <&topckgen CLK_TOP_AUD_44K_TIMING>,
+				 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
+				 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
+				 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
+				 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
+				 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
+				 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
+				 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
+				 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
+				 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
+				 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
+				 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
+				 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
+				 <&audsys CLK_AUD_I2SO1>,
+				 <&audsys CLK_AUD_I2SO2>,
+				 <&audsys CLK_AUD_I2SO3>,
+				 <&audsys CLK_AUD_I2SO4>,
+				 <&audsys CLK_AUD_I2SIN1>,
+				 <&audsys CLK_AUD_I2SIN2>,
+				 <&audsys CLK_AUD_I2SIN3>,
+				 <&audsys CLK_AUD_I2SIN4>,
+				 <&audsys CLK_AUD_ASRCO1>,
+				 <&audsys CLK_AUD_ASRCO2>,
+				 <&audsys CLK_AUD_ASRCO3>,
+				 <&audsys CLK_AUD_ASRCO4>,
+				 <&audsys CLK_AUD_AFE>,
+				 <&audsys CLK_AUD_AFE_CONN>,
+				 <&audsys CLK_AUD_A1SYS>,
+				 <&audsys CLK_AUD_A2SYS>,
+				 <&audsys CLK_AUD_AFE_MRGIF>;
+
+			clock-names = "infra_sys_audio_clk",
+				      "top_audio_mux1_sel",
+				      "top_audio_mux2_sel",
+				      "top_audio_a1sys_hp",
+				      "top_audio_a2sys_hp",
+				      "i2s0_src_sel",
+				      "i2s1_src_sel",
+				      "i2s2_src_sel",
+				      "i2s3_src_sel",
+				      "i2s0_src_div",
+				      "i2s1_src_div",
+				      "i2s2_src_div",
+				      "i2s3_src_div",
+				      "i2s0_mclk_en",
+				      "i2s1_mclk_en",
+				      "i2s2_mclk_en",
+				      "i2s3_mclk_en",
+				      "i2so0_hop_ck",
+				      "i2so1_hop_ck",
+				      "i2so2_hop_ck",
+				      "i2so3_hop_ck",
+				      "i2si0_hop_ck",
+				      "i2si1_hop_ck",
+				      "i2si2_hop_ck",
+				      "i2si3_hop_ck",
+				      "asrc0_out_ck",
+				      "asrc1_out_ck",
+				      "asrc2_out_ck",
+				      "asrc3_out_ck",
+				      "audio_afe_pd",
+				      "audio_afe_conn_pd",
+				      "audio_a1sys_pd",
+				      "audio_a2sys_pd",
+				      "audio_mrgif_pd";
+
+			assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
+					  <&topckgen CLK_TOP_AUD_MUX2_SEL>,
+					  <&topckgen CLK_TOP_AUD_MUX1_DIV>,
+					  <&topckgen CLK_TOP_AUD_MUX2_DIV>;
+			assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
+						 <&topckgen CLK_TOP_AUD2PLL_90M>;
+			assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
+		};
 	};
 
 	mmc0: mmc@11230000 {
-- 
1.9.1

Re: [PATCH v4 3/6] clk: mediatek: add audsys support for MT2701

[Stephen Boyd]

Quoting Ryder Lee (2018-03-06 01:09:28)
> +
> +static const struct of_device_id of_match_clk_mt2701_aud[] = {
> +       { .compatible = "mediatek,mt2701-audsys", },
> +       {}
> +};
> +
> +static int clk_mt2701_aud_probe(struct platform_device *pdev)
> +{
> +       struct clk_onecell_data *clk_data;
> +       struct device_node *node = pdev->dev.of_node;
> +       int r;
> +
> +       clk_data = mtk_alloc_clk_data(CLK_AUD_NR);
> +
> +       mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
> +                              clk_data);
> +
> +       r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> +       if (r) {
> +               dev_err(&pdev->dev,
> +                       "could not register clock provider: %s: %d\n",
> +                       pdev->name, r);
> +
> +               return r;
> +       }

This fails to remove the clk provider when devm_of_platform_populate()
returns an error.

> +
> +       return devm_of_platform_populate(&pdev->dev);
> +}
> +
> +static struct platform_driver clk_mt2701_aud_drv = {
> +       .probe = clk_mt2701_aud_probe,
> +       .driver = {
> +               .name = "clk-mt2701-aud",
> +               .of_match_table = of_match_clk_mt2701_aud,
> +       },
> +};
> +
> +builtin_platform_driver(clk_mt2701_aud_drv);

Re: [PATCH v4 2/6] clk: mediatek: add devm_of_platform_populate() for MT7622 audsys

[Stephen Boyd]

Quoting Ryder Lee (2018-03-06 01:09:27)
> @@ -150,12 +151,15 @@ static int clk_mt7622_audiosys_init(struct platform_device *pdev)
>                                clk_data);
>  
>         r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> -       if (r)
> +       if (r) {
>                 dev_err(&pdev->dev,
>                         "could not register clock provider: %s: %d\n",
>                         pdev->name, r);
>  
> -       return r;
> +               return r;
> +       }
> +
> +       return devm_of_platform_populate(&pdev->dev);

And now we fail to remove the clk provider when this fails.

>  }
>  
>  static const struct of_device_id of_match_clk_mt7622_aud[] = {
> -- 
> 1.9.1
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v4 1/6] clk: mediatek: update missing clock data for MT7622 audsys

[Stephen Boyd]

Quoting Ryder Lee (2018-03-06 01:09:26)
> Add missing clock data 'CLK_AUDIO_AFE_CONN' for MT7622 audsys.
> 
> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
> ---

Applied to clk-next

Re: [PATCH v4 4/6] dt-bindings: clock: mediatek: update audsys documentation to adapt MFD device

[Stephen Boyd]

Quoting Ryder Lee (2018-03-06 01:09:29)
> The MediaTek audio hardware block that exposes functionalities that are
> handled by separate subsystems in the kernel.  These functions are all
> mapped somewhere at 0x112xxxxx, and there are some control bits are mixed
> up with other functions within the same registers.
> 
> This patch modifies example to illustrate child nodes.
> 
> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
> ---

Applied to clk-next

Re: [PATCH v4 5/6] dt-bindings: clock: mediatek: add audsys support for MT2701

[Stephen Boyd]

Quoting Ryder Lee (2018-03-06 01:09:30)
> This patch adds a compatible string for MT2701.
> 
> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
> ---

Applied to clk-next

Re: [PATCH v4 3/6] clk: mediatek: add audsys support for MT2701

[Ryder Lee]

On Mon, 2018-03-19 at 13:31 -0700, Stephen Boyd wrote:
> Quoting Ryder Lee (2018-03-06 01:09:28)
> > +
> > +static const struct of_device_id of_match_clk_mt2701_aud[] = {
> > +       { .compatible = "mediatek,mt2701-audsys", },
> > +       {}
> > +};
> > +
> > +static int clk_mt2701_aud_probe(struct platform_device *pdev)
> > +{
> > +       struct clk_onecell_data *clk_data;
> > +       struct device_node *node = pdev->dev.of_node;
> > +       int r;
> > +
> > +       clk_data = mtk_alloc_clk_data(CLK_AUD_NR);
> > +
> > +       mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
> > +                              clk_data);
> > +
> > +       r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> > +       if (r) {
> > +               dev_err(&pdev->dev,
> > +                       "could not register clock provider: %s: %d\n",
> > +                       pdev->name, r);
> > +
> > +               return r;
> > +       }
> 
> This fails to remove the clk provider when devm_of_platform_populate()
> returns an error.
> 
> > +
> > +       return devm_of_platform_populate(&pdev->dev);
> > +}

I've sent a new one to fix it.

Thanks

Re: [PATCH v4 6/6] arm: dts: mediatek: modify audio related nodes for both MT2701 and MT7623

[Matthias Brugger]

On 03/06/2018 10:09 AM, Ryder Lee wrote:
> Modify audio related nodes to reflect the actual usage in binding documents.
> 
> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
> ---

applied to v4.17-next/dts32

Thanks!

>  arch/arm/boot/dts/mt2701.dtsi | 188 ++++++++++++++++++++---------------------
>  arch/arm/boot/dts/mt7623.dtsi | 190 ++++++++++++++++++++----------------------
>  2 files changed, 182 insertions(+), 196 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> index 05557fc..05cf65c 100644
> --- a/arch/arm/boot/dts/mt2701.dtsi
> +++ b/arch/arm/boot/dts/mt2701.dtsi
> @@ -426,104 +426,96 @@
>  		status = "disabled";
>  	};
>  
> -	afe: audio-controller@11220000 {
> -		compatible = "mediatek,mt2701-audio";
> -		reg = <0 0x11220000 0 0x2000>,
> -		      <0 0x112a0000 0 0x20000>;
> -		interrupts =  <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
> -			      <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
> -		interrupt-names	= "afe", "asys";
> -		power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
> -
> -		clocks = <&infracfg CLK_INFRA_AUDIO>,
> -			 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
> -			 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
> -			 <&topckgen CLK_TOP_AUD_MUX1_DIV>,
> -			 <&topckgen CLK_TOP_AUD_MUX2_DIV>,
> -			 <&topckgen CLK_TOP_AUD_48K_TIMING>,
> -			 <&topckgen CLK_TOP_AUD_44K_TIMING>,
> -			 <&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
> -			 <&topckgen CLK_TOP_APLL_SEL>,
> -			 <&topckgen CLK_TOP_AUD1PLL_98M>,
> -			 <&topckgen CLK_TOP_AUD2PLL_90M>,
> -			 <&topckgen CLK_TOP_HADDS2PLL_98M>,
> -			 <&topckgen CLK_TOP_HADDS2PLL_294M>,
> -			 <&topckgen CLK_TOP_AUDPLL>,
> -			 <&topckgen CLK_TOP_AUDPLL_D4>,
> -			 <&topckgen CLK_TOP_AUDPLL_D8>,
> -			 <&topckgen CLK_TOP_AUDPLL_D16>,
> -			 <&topckgen CLK_TOP_AUDPLL_D24>,
> -			 <&topckgen CLK_TOP_AUDINTBUS_SEL>,
> -			 <&clk26m>,
> -			 <&topckgen CLK_TOP_SYSPLL1_D4>,
> -			 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
> -			 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
> -			 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
> -			 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
> -			 <&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
> -			 <&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
> -			 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
> -			 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
> -			 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
> -			 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
> -			 <&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
> -			 <&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
> -			 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
> -			 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
> -			 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
> -			 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
> -			 <&topckgen CLK_TOP_AUD_I2S5_MCLK>,
> -			 <&topckgen CLK_TOP_AUD_I2S6_MCLK>,
> -			 <&topckgen CLK_TOP_ASM_M_SEL>,
> -			 <&topckgen CLK_TOP_ASM_H_SEL>,
> -			 <&topckgen CLK_TOP_UNIVPLL2_D4>,
> -			 <&topckgen CLK_TOP_UNIVPLL2_D2>,
> -			 <&topckgen CLK_TOP_SYSPLL_D5>;
> -
> -		clock-names = "infra_sys_audio_clk",
> -			 "top_audio_mux1_sel",
> -			 "top_audio_mux2_sel",
> -			 "top_audio_mux1_div",
> -			 "top_audio_mux2_div",
> -			 "top_audio_48k_timing",
> -			 "top_audio_44k_timing",
> -			 "top_audpll_mux_sel",
> -			 "top_apll_sel",
> -			 "top_aud1_pll_98M",
> -			 "top_aud2_pll_90M",
> -			 "top_hadds2_pll_98M",
> -			 "top_hadds2_pll_294M",
> -			 "top_audpll",
> -			 "top_audpll_d4",
> -			 "top_audpll_d8",
> -			 "top_audpll_d16",
> -			 "top_audpll_d24",
> -			 "top_audintbus_sel",
> -			 "clk_26m",
> -			 "top_syspll1_d4",
> -			 "top_aud_k1_src_sel",
> -			 "top_aud_k2_src_sel",
> -			 "top_aud_k3_src_sel",
> -			 "top_aud_k4_src_sel",
> -			 "top_aud_k5_src_sel",
> -			 "top_aud_k6_src_sel",
> -			 "top_aud_k1_src_div",
> -			 "top_aud_k2_src_div",
> -			 "top_aud_k3_src_div",
> -			 "top_aud_k4_src_div",
> -			 "top_aud_k5_src_div",
> -			 "top_aud_k6_src_div",
> -			 "top_aud_i2s1_mclk",
> -			 "top_aud_i2s2_mclk",
> -			 "top_aud_i2s3_mclk",
> -			 "top_aud_i2s4_mclk",
> -			 "top_aud_i2s5_mclk",
> -			 "top_aud_i2s6_mclk",
> -			 "top_asm_m_sel",
> -			 "top_asm_h_sel",
> -			 "top_univpll2_d4",
> -			 "top_univpll2_d2",
> -			 "top_syspll_d5";
> +	audsys: clock-controller@11220000 {
> +		compatible = "mediatek,mt2701-audsys", "syscon";
> +		reg = <0 0x11220000 0 0x2000>;
> +		#clock-cells = <1>;
> +
> +		afe: audio-controller {
> +			compatible = "mediatek,mt2701-audio";
> +			interrupts =  <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
> +				      <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
> +			interrupt-names	= "afe", "asys";
> +			power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
> +
> +			clocks = <&infracfg CLK_INFRA_AUDIO>,
> +				 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
> +				 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
> +				 <&topckgen CLK_TOP_AUD_48K_TIMING>,
> +				 <&topckgen CLK_TOP_AUD_44K_TIMING>,
> +				 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
> +				 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
> +				 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
> +				 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
> +				 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
> +				 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
> +				 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
> +				 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
> +				 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
> +				 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
> +				 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
> +				 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
> +				 <&audsys CLK_AUD_I2SO1>,
> +				 <&audsys CLK_AUD_I2SO2>,
> +				 <&audsys CLK_AUD_I2SO3>,
> +				 <&audsys CLK_AUD_I2SO4>,
> +				 <&audsys CLK_AUD_I2SIN1>,
> +				 <&audsys CLK_AUD_I2SIN2>,
> +				 <&audsys CLK_AUD_I2SIN3>,
> +				 <&audsys CLK_AUD_I2SIN4>,
> +				 <&audsys CLK_AUD_ASRCO1>,
> +				 <&audsys CLK_AUD_ASRCO2>,
> +				 <&audsys CLK_AUD_ASRCO3>,
> +				 <&audsys CLK_AUD_ASRCO4>,
> +				 <&audsys CLK_AUD_AFE>,
> +				 <&audsys CLK_AUD_AFE_CONN>,
> +				 <&audsys CLK_AUD_A1SYS>,
> +				 <&audsys CLK_AUD_A2SYS>,
> +				 <&audsys CLK_AUD_AFE_MRGIF>;
> +
> +			clock-names = "infra_sys_audio_clk",
> +				      "top_audio_mux1_sel",
> +				      "top_audio_mux2_sel",
> +				      "top_audio_a1sys_hp",
> +				      "top_audio_a2sys_hp",
> +				      "i2s0_src_sel",
> +				      "i2s1_src_sel",
> +				      "i2s2_src_sel",
> +				      "i2s3_src_sel",
> +				      "i2s0_src_div",
> +				      "i2s1_src_div",
> +				      "i2s2_src_div",
> +				      "i2s3_src_div",
> +				      "i2s0_mclk_en",
> +				      "i2s1_mclk_en",
> +				      "i2s2_mclk_en",
> +				      "i2s3_mclk_en",
> +				      "i2so0_hop_ck",
> +				      "i2so1_hop_ck",
> +				      "i2so2_hop_ck",
> +				      "i2so3_hop_ck",
> +				      "i2si0_hop_ck",
> +				      "i2si1_hop_ck",
> +				      "i2si2_hop_ck",
> +				      "i2si3_hop_ck",
> +				      "asrc0_out_ck",
> +				      "asrc1_out_ck",
> +				      "asrc2_out_ck",
> +				      "asrc3_out_ck",
> +				      "audio_afe_pd",
> +				      "audio_afe_conn_pd",
> +				      "audio_a1sys_pd",
> +				      "audio_a2sys_pd",
> +				      "audio_mrgif_pd";
> +
> +			assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
> +					  <&topckgen CLK_TOP_AUD_MUX2_SEL>,
> +					  <&topckgen CLK_TOP_AUD_MUX1_DIV>,
> +					  <&topckgen CLK_TOP_AUD_MUX2_DIV>;
> +			assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
> +						 <&topckgen CLK_TOP_AUD2PLL_90M>;
> +			assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
> +		};
>  	};
>  
>  	mmsys: syscon@14000000 {
> diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
> index b750da5..e4dd31d 100644
> --- a/arch/arm/boot/dts/mt7623.dtsi
> +++ b/arch/arm/boot/dts/mt7623.dtsi
> @@ -538,105 +538,99 @@
>  		status = "disabled";
>  	};
>  
> -	afe: audio-controller@11220000 {
> -		compatible = "mediatek,mt7623-audio",
> -			     "mediatek,mt2701-audio";
> -		reg = <0 0x11220000 0 0x2000>,
> -		      <0 0x112a0000 0 0x20000>;
> -		interrupts =  <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
> -			      <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
> -		interrupt-names	= "afe", "asys";
> -		power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
> +	audsys: clock-controller@11220000 {
> +		compatible = "mediatek,mt7623-audsys",
> +			     "mediatek,mt2701-audsys",
> +			     "syscon";
> +		reg = <0 0x11220000 0 0x2000>;
> +		#clock-cells = <1>;
>  
> -		clocks = <&infracfg CLK_INFRA_AUDIO>,
> -			 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
> -			 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
> -			 <&topckgen CLK_TOP_AUD_MUX1_DIV>,
> -			 <&topckgen CLK_TOP_AUD_MUX2_DIV>,
> -			 <&topckgen CLK_TOP_AUD_48K_TIMING>,
> -			 <&topckgen CLK_TOP_AUD_44K_TIMING>,
> -			 <&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
> -			 <&topckgen CLK_TOP_APLL_SEL>,
> -			 <&topckgen CLK_TOP_AUD1PLL_98M>,
> -			 <&topckgen CLK_TOP_AUD2PLL_90M>,
> -			 <&topckgen CLK_TOP_HADDS2PLL_98M>,
> -			 <&topckgen CLK_TOP_HADDS2PLL_294M>,
> -			 <&topckgen CLK_TOP_AUDPLL>,
> -			 <&topckgen CLK_TOP_AUDPLL_D4>,
> -			 <&topckgen CLK_TOP_AUDPLL_D8>,
> -			 <&topckgen CLK_TOP_AUDPLL_D16>,
> -			 <&topckgen CLK_TOP_AUDPLL_D24>,
> -			 <&topckgen CLK_TOP_AUDINTBUS_SEL>,
> -			 <&clk26m>,
> -			 <&topckgen CLK_TOP_SYSPLL1_D4>,
> -			 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
> -			 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
> -			 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
> -			 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
> -			 <&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
> -			 <&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
> -			 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
> -			 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
> -			 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
> -			 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
> -			 <&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
> -			 <&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
> -			 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
> -			 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
> -			 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
> -			 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
> -			 <&topckgen CLK_TOP_AUD_I2S5_MCLK>,
> -			 <&topckgen CLK_TOP_AUD_I2S6_MCLK>,
> -			 <&topckgen CLK_TOP_ASM_M_SEL>,
> -			 <&topckgen CLK_TOP_ASM_H_SEL>,
> -			 <&topckgen CLK_TOP_UNIVPLL2_D4>,
> -			 <&topckgen CLK_TOP_UNIVPLL2_D2>,
> -			 <&topckgen CLK_TOP_SYSPLL_D5>;
> -
> -		clock-names = "infra_sys_audio_clk",
> -			 "top_audio_mux1_sel",
> -			 "top_audio_mux2_sel",
> -			 "top_audio_mux1_div",
> -			 "top_audio_mux2_div",
> -			 "top_audio_48k_timing",
> -			 "top_audio_44k_timing",
> -			 "top_audpll_mux_sel",
> -			 "top_apll_sel",
> -			 "top_aud1_pll_98M",
> -			 "top_aud2_pll_90M",
> -			 "top_hadds2_pll_98M",
> -			 "top_hadds2_pll_294M",
> -			 "top_audpll",
> -			 "top_audpll_d4",
> -			 "top_audpll_d8",
> -			 "top_audpll_d16",
> -			 "top_audpll_d24",
> -			 "top_audintbus_sel",
> -			 "clk_26m",
> -			 "top_syspll1_d4",
> -			 "top_aud_k1_src_sel",
> -			 "top_aud_k2_src_sel",
> -			 "top_aud_k3_src_sel",
> -			 "top_aud_k4_src_sel",
> -			 "top_aud_k5_src_sel",
> -			 "top_aud_k6_src_sel",
> -			 "top_aud_k1_src_div",
> -			 "top_aud_k2_src_div",
> -			 "top_aud_k3_src_div",
> -			 "top_aud_k4_src_div",
> -			 "top_aud_k5_src_div",
> -			 "top_aud_k6_src_div",
> -			 "top_aud_i2s1_mclk",
> -			 "top_aud_i2s2_mclk",
> -			 "top_aud_i2s3_mclk",
> -			 "top_aud_i2s4_mclk",
> -			 "top_aud_i2s5_mclk",
> -			 "top_aud_i2s6_mclk",
> -			 "top_asm_m_sel",
> -			 "top_asm_h_sel",
> -			 "top_univpll2_d4",
> -			 "top_univpll2_d2",
> -			 "top_syspll_d5";
> +		afe: audio-controller {
> +			compatible = "mediatek,mt7623-audio",
> +				     "mediatek,mt2701-audio";
> +			interrupts =  <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
> +				      <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
> +			interrupt-names	= "afe", "asys";
> +			power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
> +
> +			clocks = <&infracfg CLK_INFRA_AUDIO>,
> +				 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
> +				 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
> +				 <&topckgen CLK_TOP_AUD_48K_TIMING>,
> +				 <&topckgen CLK_TOP_AUD_44K_TIMING>,
> +				 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
> +				 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
> +				 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
> +				 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
> +				 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
> +				 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
> +				 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
> +				 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
> +				 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
> +				 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
> +				 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
> +				 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
> +				 <&audsys CLK_AUD_I2SO1>,
> +				 <&audsys CLK_AUD_I2SO2>,
> +				 <&audsys CLK_AUD_I2SO3>,
> +				 <&audsys CLK_AUD_I2SO4>,
> +				 <&audsys CLK_AUD_I2SIN1>,
> +				 <&audsys CLK_AUD_I2SIN2>,
> +				 <&audsys CLK_AUD_I2SIN3>,
> +				 <&audsys CLK_AUD_I2SIN4>,
> +				 <&audsys CLK_AUD_ASRCO1>,
> +				 <&audsys CLK_AUD_ASRCO2>,
> +				 <&audsys CLK_AUD_ASRCO3>,
> +				 <&audsys CLK_AUD_ASRCO4>,
> +				 <&audsys CLK_AUD_AFE>,
> +				 <&audsys CLK_AUD_AFE_CONN>,
> +				 <&audsys CLK_AUD_A1SYS>,
> +				 <&audsys CLK_AUD_A2SYS>,
> +				 <&audsys CLK_AUD_AFE_MRGIF>;
> +
> +			clock-names = "infra_sys_audio_clk",
> +				      "top_audio_mux1_sel",
> +				      "top_audio_mux2_sel",
> +				      "top_audio_a1sys_hp",
> +				      "top_audio_a2sys_hp",
> +				      "i2s0_src_sel",
> +				      "i2s1_src_sel",
> +				      "i2s2_src_sel",
> +				      "i2s3_src_sel",
> +				      "i2s0_src_div",
> +				      "i2s1_src_div",
> +				      "i2s2_src_div",
> +				      "i2s3_src_div",
> +				      "i2s0_mclk_en",
> +				      "i2s1_mclk_en",
> +				      "i2s2_mclk_en",
> +				      "i2s3_mclk_en",
> +				      "i2so0_hop_ck",
> +				      "i2so1_hop_ck",
> +				      "i2so2_hop_ck",
> +				      "i2so3_hop_ck",
> +				      "i2si0_hop_ck",
> +				      "i2si1_hop_ck",
> +				      "i2si2_hop_ck",
> +				      "i2si3_hop_ck",
> +				      "asrc0_out_ck",
> +				      "asrc1_out_ck",
> +				      "asrc2_out_ck",
> +				      "asrc3_out_ck",
> +				      "audio_afe_pd",
> +				      "audio_afe_conn_pd",
> +				      "audio_a1sys_pd",
> +				      "audio_a2sys_pd",
> +				      "audio_mrgif_pd";
> +
> +			assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
> +					  <&topckgen CLK_TOP_AUD_MUX2_SEL>,
> +					  <&topckgen CLK_TOP_AUD_MUX1_DIV>,
> +					  <&topckgen CLK_TOP_AUD_MUX2_DIV>;
> +			assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
> +						 <&topckgen CLK_TOP_AUD2PLL_90M>;
> +			assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
> +		};
>  	};
>  
>  	mmc0: mmc@11230000 {
>